clk-mt7981-topckgen.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (c) 2021 MediaTek Inc.
  4 * Author: Sam Shih <sam.shih@mediatek.com>
  5 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
  6 * Author: Jianhui Zhao <zhaojh329@gmail.com>
  7 */
  8
  9
 10#include <linux/clk-provider.h>
 11#include <linux/mod_devicetable.h>
 12#include <linux/platform_device.h>
 13#include "clk-mtk.h"
 14#include "clk-gate.h"
 15#include "clk-mux.h"
 16
 17#include <dt-bindings/clock/mediatek,mt7981-clk.h>
 18#include <linux/clk.h>
 19
 20static DEFINE_SPINLOCK(mt7981_clk_lock);
 21
 22static const struct mtk_fixed_factor top_divs[] = {
 23	FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
 24	FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
 25	FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
 26	FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
 27	FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
 28	FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
 29	FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
 30	FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
 31	FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
 32	FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
 33	FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3),
 34	FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
 35	FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
 36	FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6),
 37	FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
 38	FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
 39	FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
 40	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
 41	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
 42	FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1),
 43	FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
 44	FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
 45	FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
 46	FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
 47	FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
 48	FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
 49	FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
 50	FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
 51	FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
 52	FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
 53	FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
 54	FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
 55	FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
 56	FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
 57	FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
 58	FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
 59	FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
 60	FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
 61	FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
 62	FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1),
 63	FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
 64	FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
 65	FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
 66	FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
 67	FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
 68	FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1),
 69	FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
 70	FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
 71	FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1),
 72	FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
 73	FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
 74	FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1),
 75	FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
 76	FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1),
 77	FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1),
 78	FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
 79	FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1),
 80	FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1),
 81	FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
 82	FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1),
 83	FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1),
 84	FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
 85	FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
 86	FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
 87	FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1),
 88	FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
 89	FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1),
 90	FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1),
 91	FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1),
 92	FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
 93	FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
 94	FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
 95	FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
 96	FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
 97	FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
 98	FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
 99};
100
101static const char * const nfi1x_parents[] __initconst = {
102	"cb_cksq_40m",
103	"cb_mm_d4",
104	"net1_d8_d2",
105	"cb_net2_d6",
106	"cb_m_d4",
107	"cb_mm_d8",
108	"net1_d8_d4",
109	"cb_m_d8"
110};
111
112static const char * const spinfi_parents[] __initconst = {
113	"cksq_40m_d2",
114	"cb_cksq_40m",
115	"net1_d5_d4",
116	"cb_m_d4",
117	"cb_mm_d8",
118	"net1_d8_d4",
119	"mm_d6_d2",
120	"cb_m_d8"
121};
122
123static const char * const spi_parents[] __initconst = {
124	"cb_cksq_40m",
125	"cb_m_d2",
126	"cb_mm_d4",
127	"net1_d8_d2",
128	"cb_net2_d6",
129	"net1_d5_d4",
130	"cb_m_d4",
131	"net1_d8_d4"
132};
133
134static const char * const uart_parents[] __initconst = {
135	"cb_cksq_40m",
136	"cb_m_d8",
137	"m_d8_d2"
138};
139
140static const char * const pwm_parents[] __initconst = {
141	"cb_cksq_40m",
142	"net1_d8_d2",
143	"net1_d5_d4",
144	"cb_m_d4",
145	"m_d8_d2",
146	"cb_rtc_32k"
147};
148
149static const char * const i2c_parents[] __initconst = {
150	"cb_cksq_40m",
151	"net1_d5_d4",
152	"cb_m_d4",
153	"net1_d8_d4"
154};
155
156static const char * const pextp_tl_ck_parents[] __initconst = {
157	"cb_cksq_40m",
158	"net1_d5_d4",
159	"cb_m_d4",
160	"cb_rtc_32k"
161};
162
163static const char * const emmc_208m_parents[] __initconst = {
164	"cb_cksq_40m",
165	"cb_m_d2",
166	"cb_net2_d4",
167	"cb_apll2_196m",
168	"cb_mm_d4",
169	"net1_d8_d2",
170	"cb_mm_d6"
171};
172
173static const char * const emmc_400m_parents[] __initconst = {
174	"cb_cksq_40m",
175	"cb_net2_d2",
176	"cb_mm_d2",
177	"cb_net2_d2"
178};
179
180static const char * const csw_f26m_parents[] __initconst = {
181	"cksq_40m_d2",
182	"m_d8_d2"
183};
184
185static const char * const dramc_md32_parents[] __initconst = {
186	"cb_cksq_40m",
187	"cb_m_d2",
188	"cb_wedmcu_208m"
189};
190
191static const char * const sysaxi_parents[] __initconst = {
192	"cb_cksq_40m",
193	"net1_d8_d2"
194};
195
196static const char * const sysapb_parents[] __initconst = {
197	"cb_cksq_40m",
198	"m_d3_d2"
199};
200
201static const char * const arm_db_main_parents[] __initconst = {
202	"cb_cksq_40m",
203	"cb_net2_d6"
204};
205
206static const char * const ap2cnn_host_parents[] __initconst = {
207	"cb_cksq_40m",
208	"net1_d8_d4"
209};
210
211static const char * const netsys_parents[] __initconst = {
212	"cb_cksq_40m",
213	"cb_mm_d2"
214};
215
216static const char * const netsys_500m_parents[] __initconst = {
217	"cb_cksq_40m",
218	"cb_net1_d5"
219};
220
221static const char * const netsys_mcu_parents[] __initconst = {
222	"cb_cksq_40m",
223	"cb_mm_720m",
224	"cb_net1_d4",
225	"cb_net1_d5",
226	"cb_m_416m"
227};
228
229static const char * const netsys_2x_parents[] __initconst = {
230	"cb_cksq_40m",
231	"cb_net2_800m",
232	"cb_mm_720m"
233};
234
235static const char * const sgm_325m_parents[] __initconst = {
236	"cb_cksq_40m",
237	"cb_sgm_325m"
238};
239
240static const char * const sgm_reg_parents[] __initconst = {
241	"cb_cksq_40m",
242	"cb_net2_d4"
243};
244
245static const char * const eip97b_parents[] __initconst = {
246	"cb_cksq_40m",
247	"cb_net1_d5",
248	"cb_m_416m",
249	"cb_mm_d2",
250	"net1_d5_d2"
251};
252
253static const char * const aud_parents[] __initconst = {
254	"cb_cksq_40m",
255	"cb_apll2_196m"
256};
257
258static const char * const a1sys_parents[] __initconst = {
259	"cb_cksq_40m",
260	"apll2_d4"
261};
262
263static const char * const aud_l_parents[] __initconst = {
264	"cb_cksq_40m",
265	"cb_apll2_196m",
266	"m_d8_d2"
267};
268
269static const char * const a_tuner_parents[] __initconst = {
270	"cb_cksq_40m",
271	"apll2_d4",
272	"m_d8_d2"
273};
274
275static const char * const u2u3_parents[] __initconst = {
276	"cb_cksq_40m",
277	"m_d8_d2"
278};
279
280static const char * const u2u3_sys_parents[] __initconst = {
281	"cb_cksq_40m",
282	"net1_d5_d4"
283};
284
285static const char * const usb_frmcnt_parents[] __initconst = {
286	"cb_cksq_40m",
287	"cb_mm_d3_d5"
288};
289
290static const struct mtk_mux top_muxes[] = {
291	/* CLK_CFG_0 */
292	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
293			     0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
294	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
295			     0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
296	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
297			     0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
298	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
299			     0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
300	/* CLK_CFG_1 */
301	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
302			     0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
303	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
304			     0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
305	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
306			     0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
307	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
308			     pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
309			     0x1C0, 7),
310	/* CLK_CFG_2 */
311	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
312				   emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
313				   0x1C0, 8, 0),
314	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
315				   emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
316				   0x1C0, 9, 0),
317	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
318				   csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
319				   0x1C0, 10,
320				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
321	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
322				   csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1,
323				   31, 0x1C0, 11,
324				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
325	/* CLK_CFG_3 */
326	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
327				   dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2,
328				   7, 0x1C0, 12,
329				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
330	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
331				   sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15,
332				   0x1C0, 13,
333				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
334	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
335				   sysapb_parents, 0x030, 0x034, 0x038, 16, 1,
336				   23, 0x1C0, 14,
337				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
338	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
339			     arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31,
340			     0x1C0, 15),
341	/* CLK_CFG_4 */
342	MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
343			     ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7,
344			     0x1C0, 16),
345	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
346			     0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
347	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
348			     netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23,
349			     0x1C0, 18),
350	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
351			     netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
352			     0x1C0, 19),
353	/* CLK_CFG_5 */
354	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
355			     netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
356			     0x1C0, 20),
357	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
358			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
359			     0x1C0, 21),
360	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
361				   0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22,
362				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
363	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
364			     0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
365	/* CLK_CFG_6 */
366	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
367			     csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1,
368			     7, 0x1C0, 24),
369	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060,
370			     0x064, 0x068, 8, 1, 15, 0x1C0, 25),
371	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
372			     0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
373	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
374			     0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27),
375	/* CLK_CFG_7 */
376	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
377			     a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7,
378			     0x1C0, 28),
379	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070,
380			     0x074, 0x078, 8, 1, 15, 0x1C0, 29),
381	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
382			     u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23,
383			     0x1C0, 30),
384	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
385			     u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31,
386			     0x1C4, 0),
387	/* CLK_CFG_8 */
388	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
389			     usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7,
390			     0x1C4, 1),
391};
392
393static struct mtk_composite top_aud_divs[] = {
394	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
395		0x0420, 0, 0x0420, 8, 8),
396};
397
398static const struct mtk_clk_desc topck_desc = {
399	.factor_clks = top_divs,
400	.num_factor_clks = ARRAY_SIZE(top_divs),
401	.mux_clks = top_muxes,
402	.num_mux_clks = ARRAY_SIZE(top_muxes),
403	.composite_clks = top_aud_divs,
404	.num_composite_clks = ARRAY_SIZE(top_aud_divs),
405	.clk_lock = &mt7981_clk_lock,
406};
407
408static const struct of_device_id of_match_clk_mt7981_topckgen[] = {
409	{ .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc },
410	{ /* sentinel */ }
411};
412MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_topckgen);
413
414static struct platform_driver clk_mt7981_topckgen_drv = {
415	.probe = mtk_clk_simple_probe,
416	.remove = mtk_clk_simple_remove,
417	.driver = {
418		.name = "clk-mt7981-topckgen",
419		.of_match_table = of_match_clk_mt7981_topckgen,
420	},
421};
422module_platform_driver(clk_mt7981_topckgen_drv);
423
424MODULE_DESCRIPTION("MediaTek MT7981 top clock generators driver");
425MODULE_LICENSE("GPL");