clk-mt6795-vencsys.c

 1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * Copyright (c) 2022 Collabora Ltd.
 4 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
 5 */
 6
 7#include <dt-bindings/clock/mediatek,mt6795-clk.h>
 8#include <linux/module.h>
 9#include <linux/platform_device.h>
10#include "clk-gate.h"
11#include "clk-mtk.h"
12
13static const struct mtk_gate_regs venc_cg_regs = {
14	.set_ofs = 0x4,
15	.clr_ofs = 0x8,
16	.sta_ofs = 0x0,
17};
18
19#define GATE_VENC(_id, _name, _parent, _shift)			\
20	GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
21
22static const struct mtk_gate venc_clks[] = {
23	GATE_VENC(CLK_VENC_LARB, "venc_larb", "venc_sel", 0),
24	GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
25	GATE_VENC(CLK_VENC_JPGENC, "venc_jpgenc", "venc_sel", 8),
26	GATE_VENC(CLK_VENC_JPGDEC, "venc_jpgdec", "venc_sel", 12),
27};
28
29static const struct mtk_clk_desc venc_desc = {
30	.clks = venc_clks,
31	.num_clks = ARRAY_SIZE(venc_clks),
32};
33
34static const struct of_device_id of_match_clk_mt6795_vencsys[] = {
35	{ .compatible = "mediatek,mt6795-vencsys", .data = &venc_desc },
36	{ /* sentinel */ }
37};
38MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_vencsys);
39
40static struct platform_driver clk_mt6795_vencsys_drv = {
41	.driver = {
42		.name = "clk-mt6795-vencsys",
43		.of_match_table = of_match_clk_mt6795_vencsys,
44	},
45	.probe = mtk_clk_simple_probe,
46	.remove = mtk_clk_simple_remove,
47};
48module_platform_driver(clk_mt6795_vencsys_drv);
49
50MODULE_DESCRIPTION("MediaTek MT6795 vdecsys clocks driver");
51MODULE_LICENSE("GPL");