clk-mt6779-mm.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (c) 2019 MediaTek Inc.
  4 * Author: Wendell Lin <wendell.lin@mediatek.com>
  5 */
  6
  7#include <linux/module.h>
  8#include <linux/clk-provider.h>
  9#include <linux/platform_device.h>
 10#include <dt-bindings/clock/mt6779-clk.h>
 11
 12#include "clk-mtk.h"
 13#include "clk-gate.h"
 14
 15static const struct mtk_gate_regs mm0_cg_regs = {
 16	.set_ofs = 0x0104,
 17	.clr_ofs = 0x0108,
 18	.sta_ofs = 0x0100,
 19};
 20
 21static const struct mtk_gate_regs mm1_cg_regs = {
 22	.set_ofs = 0x0114,
 23	.clr_ofs = 0x0118,
 24	.sta_ofs = 0x0110,
 25};
 26
 27#define GATE_MM0(_id, _name, _parent, _shift)			\
 28	GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift,	\
 29		&mtk_clk_gate_ops_setclr)
 30#define GATE_MM1(_id, _name, _parent, _shift)			\
 31	GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift,	\
 32		&mtk_clk_gate_ops_setclr)
 33
 34static const struct mtk_gate mm_clks[] = {
 35	/* MM0 */
 36	GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
 37	GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
 38	GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2),
 39	GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3),
 40	GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4),
 41	GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5),
 42	GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6),
 43	GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7),
 44	GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8),
 45	GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9),
 46	GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10),
 47	GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11),
 48	GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
 49	GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13),
 50	GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
 51	GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
 52	GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16),
 53	GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
 54	GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 18),
 55	GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19),
 56	GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
 57	GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
 58	GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22),
 59	GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
 60	GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24),
 61	GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
 62	GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26),
 63	GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27),
 64	GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28),
 65	GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29),
 66	GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30),
 67	GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
 68	/* MM1 */
 69	GATE_MM1(CLK_MM_DSI0_MM_CK, "mm_dsi0_mmck", "mm_sel", 0),
 70	GATE_MM1(CLK_MM_DSI0_IF_CK, "mm_dsi0_ifck", "mm_sel", 1),
 71	GATE_MM1(CLK_MM_DPI_MM_CK, "mm_dpi_mmck", "mm_sel", 2),
 72	GATE_MM1(CLK_MM_DPI_IF_CK, "mm_dpi_ifck", "dpi0_sel", 3),
 73	GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4),
 74	GATE_MM1(CLK_MM_MDP_DL_RX_CK, "mm_mdp_dl_rxck", "mm_sel", 5),
 75	GATE_MM1(CLK_MM_IPU_DL_RX_CK, "mm_ipu_dl_rxck", "mm_sel", 6),
 76	GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7),
 77	GATE_MM1(CLK_MM_MM_R2Y, "mm_mmsys_r2y", "mm_sel", 8),
 78	GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9),
 79	GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10),
 80	GATE_MM1(CLK_MM_MDP_HDR, "mm_mdp_hdr", "mm_sel", 11),
 81	GATE_MM1(CLK_MM_DBI_MM_CK, "mm_dbi_mmck", "mm_sel", 12),
 82	GATE_MM1(CLK_MM_DBI_IF_CK, "mm_dbi_ifck", "dpi0_sel", 13),
 83	GATE_MM1(CLK_MM_DISP_POSTMASK0, "mm_disp_pm0", "mm_sel", 14),
 84	GATE_MM1(CLK_MM_DISP_HRT_BW, "mm_disp_hrt_bw", "mm_sel", 15),
 85	GATE_MM1(CLK_MM_DISP_OVL_FBDC, "mm_disp_ovl_fbdc", "mm_sel", 16),
 86};
 87
 88static const struct mtk_clk_desc mm_desc = {
 89	.clks = mm_clks,
 90	.num_clks = ARRAY_SIZE(mm_clks),
 91};
 92
 93static const struct platform_device_id clk_mt6779_mm_id_table[] = {
 94	{ .name = "clk-mt6779-mm", .driver_data = (kernel_ulong_t)&mm_desc },
 95	{ /* sentinel */ }
 96};
 97MODULE_DEVICE_TABLE(platform, clk_mt6779_mm_id_table);
 98
 99static struct platform_driver clk_mt6779_mm_drv = {
100	.probe = mtk_clk_pdev_probe,
101	.remove = mtk_clk_pdev_remove,
102	.driver = {
103		.name = "clk-mt6779-mm",
104	},
105	.id_table = clk_mt6779_mm_id_table,
106};
107
108module_platform_driver(clk_mt6779_mm_drv);
109
110MODULE_DESCRIPTION("MediaTek MT6779 MultiMedia mdp/ddp clocks driver");
111MODULE_LICENSE("GPL");