clk-mt6779-aud.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (c) 2019 MediaTek Inc.
  4 * Author: Wendell Lin <wendell.lin@mediatek.com>
  5 */
  6
  7#include <linux/module.h>
  8#include <linux/clk-provider.h>
  9#include <linux/mod_devicetable.h>
 10#include <linux/platform_device.h>
 11
 12#include "clk-mtk.h"
 13#include "clk-gate.h"
 14
 15#include <dt-bindings/clock/mt6779-clk.h>
 16
 17static const struct mtk_gate_regs audio0_cg_regs = {
 18	.set_ofs = 0x0,
 19	.clr_ofs = 0x0,
 20	.sta_ofs = 0x0,
 21};
 22
 23static const struct mtk_gate_regs audio1_cg_regs = {
 24	.set_ofs = 0x4,
 25	.clr_ofs = 0x4,
 26	.sta_ofs = 0x4,
 27};
 28
 29#define GATE_AUDIO0(_id, _name, _parent, _shift)		\
 30	GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift,	\
 31		&mtk_clk_gate_ops_no_setclr)
 32#define GATE_AUDIO1(_id, _name, _parent, _shift)		\
 33	GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift,	\
 34		&mtk_clk_gate_ops_no_setclr)
 35
 36static const struct mtk_gate audio_clks[] = {
 37	/* AUDIO0 */
 38	GATE_AUDIO0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2),
 39	GATE_AUDIO0(CLK_AUD_22M, "aud_22m", "aud_eng1_sel", 8),
 40	GATE_AUDIO0(CLK_AUD_24M, "aud_24m", "aud_eng2_sel", 9),
 41	GATE_AUDIO0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner",
 42		    "aud_eng2_sel", 18),
 43	GATE_AUDIO0(CLK_AUD_APLL_TUNER, "aud_apll_tuner",
 44		    "aud_eng1_sel", 19),
 45	GATE_AUDIO0(CLK_AUD_TDM, "aud_tdm", "aud_eng1_sel", 20),
 46	GATE_AUDIO0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24),
 47	GATE_AUDIO0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25),
 48	GATE_AUDIO0(CLK_AUD_DAC_PREDIS, "aud_dac_predis",
 49		    "audio_sel", 26),
 50	GATE_AUDIO0(CLK_AUD_TML, "aud_tml", "audio_sel", 27),
 51	GATE_AUDIO0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28),
 52	/* AUDIO1 */
 53	GATE_AUDIO1(CLK_AUD_I2S1_BCLK_SW, "aud_i2s1_bclk",
 54		    "audio_sel", 4),
 55	GATE_AUDIO1(CLK_AUD_I2S2_BCLK_SW, "aud_i2s2_bclk",
 56		    "audio_sel", 5),
 57	GATE_AUDIO1(CLK_AUD_I2S3_BCLK_SW, "aud_i2s3_bclk",
 58		    "audio_sel", 6),
 59	GATE_AUDIO1(CLK_AUD_I2S4_BCLK_SW, "aud_i2s4_bclk",
 60		    "audio_sel", 7),
 61	GATE_AUDIO1(CLK_AUD_I2S5_BCLK_SW, "aud_i2s5_bclk",
 62		    "audio_sel", 8),
 63	GATE_AUDIO1(CLK_AUD_CONN_I2S_ASRC, "aud_conn_i2s",
 64		    "audio_sel", 12),
 65	GATE_AUDIO1(CLK_AUD_GENERAL1_ASRC, "aud_general1",
 66		    "audio_sel", 13),
 67	GATE_AUDIO1(CLK_AUD_GENERAL2_ASRC, "aud_general2",
 68		    "audio_sel", 14),
 69	GATE_AUDIO1(CLK_AUD_DAC_HIRES, "aud_dac_hires",
 70		    "audio_h_sel", 15),
 71	GATE_AUDIO1(CLK_AUD_ADC_HIRES, "aud_adc_hires",
 72		    "audio_h_sel", 16),
 73	GATE_AUDIO1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml",
 74		    "audio_h_sel", 17),
 75	GATE_AUDIO1(CLK_AUD_PDN_ADDA6_ADC, "aud_pdn_adda6_adc",
 76		    "audio_sel", 20),
 77	GATE_AUDIO1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
 78		    "audio_h_sel",
 79		    21),
 80	GATE_AUDIO1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel",
 81		    28),
 82	GATE_AUDIO1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis",
 83		    "audio_sel", 29),
 84	GATE_AUDIO1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml",
 85		    "audio_sel", 30),
 86	GATE_AUDIO1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires",
 87		    "audio_h_sel", 31),
 88};
 89
 90static const struct mtk_clk_desc audio_desc = {
 91	.clks = audio_clks,
 92	.num_clks = ARRAY_SIZE(audio_clks),
 93};
 94
 95static const struct of_device_id of_match_clk_mt6779_aud[] = {
 96	{
 97		.compatible = "mediatek,mt6779-audio",
 98		.data = &audio_desc,
 99	}, {
100		/* sentinel */
101	}
102};
103MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_aud);
104
105static struct platform_driver clk_mt6779_aud_drv = {
106	.probe = mtk_clk_simple_probe,
107	.remove = mtk_clk_simple_remove,
108	.driver = {
109		.name = "clk-mt6779-aud",
110		.of_match_table = of_match_clk_mt6779_aud,
111	},
112};
113module_platform_driver(clk_mt6779_aud_drv);
114
115MODULE_DESCRIPTION("MediaTek MT6779 audio clocks driver");
116MODULE_LICENSE("GPL");