clk-mt6735-pericfg.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
  4 */
  5
  6#include <linux/clk-provider.h>
  7#include <linux/platform_device.h>
  8
  9#include "clk-gate.h"
 10#include "clk-mtk.h"
 11
 12#include <dt-bindings/clock/mediatek,mt6735-pericfg.h>
 13#include <dt-bindings/reset/mediatek,mt6735-pericfg.h>
 14
 15#define PERI_GLOBALCON_RST0		0x00
 16#define PERI_GLOBALCON_RST1		0x04
 17#define PERI_GLOBALCON_PDN0_SET		0x08
 18#define PERI_GLOBALCON_PDN0_CLR		0x10
 19#define PERI_GLOBALCON_PDN0_STA		0x18
 20
 21#define RST_NR_PER_BANK			32
 22
 23static struct mtk_gate_regs peri_cg_regs = {
 24	.set_ofs = PERI_GLOBALCON_PDN0_SET,
 25	.clr_ofs = PERI_GLOBALCON_PDN0_CLR,
 26	.sta_ofs = PERI_GLOBALCON_PDN0_STA,
 27};
 28
 29static const struct mtk_gate pericfg_gates[] = {
 30	GATE_MTK(CLK_PERI_DISP_PWM, "disp_pwm", "disppwm_sel", &peri_cg_regs, 0, &mtk_clk_gate_ops_setclr),
 31	GATE_MTK(CLK_PERI_THERM, "therm", "axi_sel", &peri_cg_regs, 1, &mtk_clk_gate_ops_setclr),
 32	GATE_MTK(CLK_PERI_PWM1, "pwm1", "axi_sel", &peri_cg_regs, 2, &mtk_clk_gate_ops_setclr),
 33	GATE_MTK(CLK_PERI_PWM2, "pwm2", "axi_sel", &peri_cg_regs, 3, &mtk_clk_gate_ops_setclr),
 34	GATE_MTK(CLK_PERI_PWM3, "pwm3", "axi_sel", &peri_cg_regs, 4, &mtk_clk_gate_ops_setclr),
 35	GATE_MTK(CLK_PERI_PWM4, "pwm4", "axi_sel", &peri_cg_regs, 5, &mtk_clk_gate_ops_setclr),
 36	GATE_MTK(CLK_PERI_PWM5, "pwm5", "axi_sel", &peri_cg_regs, 6, &mtk_clk_gate_ops_setclr),
 37	GATE_MTK(CLK_PERI_PWM6, "pwm6", "axi_sel", &peri_cg_regs, 7, &mtk_clk_gate_ops_setclr),
 38	GATE_MTK(CLK_PERI_PWM7, "pwm7", "axi_sel", &peri_cg_regs, 8, &mtk_clk_gate_ops_setclr),
 39	GATE_MTK(CLK_PERI_PWM, "pwm", "axi_sel", &peri_cg_regs, 9, &mtk_clk_gate_ops_setclr),
 40	GATE_MTK(CLK_PERI_USB0, "usb0", "usb20_sel", &peri_cg_regs, 10, &mtk_clk_gate_ops_setclr),
 41	GATE_MTK(CLK_PERI_IRDA, "irda", "irda_sel", &peri_cg_regs, 11, &mtk_clk_gate_ops_setclr),
 42	GATE_MTK(CLK_PERI_APDMA, "apdma", "axi_sel", &peri_cg_regs, 12, &mtk_clk_gate_ops_setclr),
 43	GATE_MTK(CLK_PERI_MSDC30_0, "msdc30_0", "msdc30_0_sel", &peri_cg_regs, 13, &mtk_clk_gate_ops_setclr),
 44	GATE_MTK(CLK_PERI_MSDC30_1, "msdc30_1", "msdc30_1_sel", &peri_cg_regs, 14, &mtk_clk_gate_ops_setclr),
 45	GATE_MTK(CLK_PERI_MSDC30_2, "msdc30_2", "msdc30_2_sel", &peri_cg_regs, 15, &mtk_clk_gate_ops_setclr),
 46	GATE_MTK(CLK_PERI_MSDC30_3, "msdc30_3", "msdc30_3_sel", &peri_cg_regs, 16, &mtk_clk_gate_ops_setclr),
 47	GATE_MTK(CLK_PERI_UART0, "uart0", "uart_sel", &peri_cg_regs, 17, &mtk_clk_gate_ops_setclr),
 48	GATE_MTK(CLK_PERI_UART1, "uart1", "uart_sel", &peri_cg_regs, 18, &mtk_clk_gate_ops_setclr),
 49	GATE_MTK(CLK_PERI_UART2, "uart2", "uart_sel", &peri_cg_regs, 19, &mtk_clk_gate_ops_setclr),
 50	GATE_MTK(CLK_PERI_UART3, "uart3", "uart_sel", &peri_cg_regs, 20, &mtk_clk_gate_ops_setclr),
 51	GATE_MTK(CLK_PERI_UART4, "uart4", "uart_sel", &peri_cg_regs, 21, &mtk_clk_gate_ops_setclr),
 52	GATE_MTK(CLK_PERI_BTIF, "btif", "axi_sel", &peri_cg_regs, 22, &mtk_clk_gate_ops_setclr),
 53	GATE_MTK(CLK_PERI_I2C0, "i2c0", "axi_sel", &peri_cg_regs, 23, &mtk_clk_gate_ops_setclr),
 54	GATE_MTK(CLK_PERI_I2C1, "i2c1", "axi_sel", &peri_cg_regs, 24, &mtk_clk_gate_ops_setclr),
 55	GATE_MTK(CLK_PERI_I2C2, "i2c2", "axi_sel", &peri_cg_regs, 25, &mtk_clk_gate_ops_setclr),
 56	GATE_MTK(CLK_PERI_I2C3, "i2c3", "axi_sel", &peri_cg_regs, 26, &mtk_clk_gate_ops_setclr),
 57	GATE_MTK(CLK_PERI_AUXADC, "auxadc", "axi_sel", &peri_cg_regs, 27, &mtk_clk_gate_ops_setclr),
 58	GATE_MTK(CLK_PERI_SPI0, "spi0", "spi_sel", &peri_cg_regs, 28, &mtk_clk_gate_ops_setclr),
 59	GATE_MTK(CLK_PERI_IRTX, "irtx", "irtx_sel", &peri_cg_regs, 29, &mtk_clk_gate_ops_setclr)
 60};
 61
 62static u16 pericfg_rst_bank_ofs[] = { PERI_GLOBALCON_RST0, PERI_GLOBALCON_RST1 };
 63
 64static u16 pericfg_rst_idx_map[] = {
 65	[MT6735_PERI_RST0_UART0]		= 0 * RST_NR_PER_BANK + 0,
 66	[MT6735_PERI_RST0_UART1]		= 0 * RST_NR_PER_BANK + 1,
 67	[MT6735_PERI_RST0_UART2]		= 0 * RST_NR_PER_BANK + 2,
 68	[MT6735_PERI_RST0_UART3]		= 0 * RST_NR_PER_BANK + 3,
 69	[MT6735_PERI_RST0_UART4]		= 0 * RST_NR_PER_BANK + 4,
 70	[MT6735_PERI_RST0_BTIF]			= 0 * RST_NR_PER_BANK + 6,
 71	[MT6735_PERI_RST0_DISP_PWM_PERI]	= 0 * RST_NR_PER_BANK + 7,
 72	[MT6735_PERI_RST0_PWM]			= 0 * RST_NR_PER_BANK + 8,
 73	[MT6735_PERI_RST0_AUXADC]		= 0 * RST_NR_PER_BANK + 10,
 74	[MT6735_PERI_RST0_DMA]			= 0 * RST_NR_PER_BANK + 11,
 75	[MT6735_PERI_RST0_IRDA]			= 0 * RST_NR_PER_BANK + 12,
 76	[MT6735_PERI_RST0_IRTX]			= 0 * RST_NR_PER_BANK + 13,
 77	[MT6735_PERI_RST0_THERM]		= 0 * RST_NR_PER_BANK + 16,
 78	[MT6735_PERI_RST0_MSDC2]		= 0 * RST_NR_PER_BANK + 17,
 79	[MT6735_PERI_RST0_MSDC3]		= 0 * RST_NR_PER_BANK + 18,
 80	[MT6735_PERI_RST0_MSDC0]		= 0 * RST_NR_PER_BANK + 19,
 81	[MT6735_PERI_RST0_MSDC1]		= 0 * RST_NR_PER_BANK + 20,
 82	[MT6735_PERI_RST0_I2C0]			= 0 * RST_NR_PER_BANK + 22,
 83	[MT6735_PERI_RST0_I2C1]			= 0 * RST_NR_PER_BANK + 23,
 84	[MT6735_PERI_RST0_I2C2]			= 0 * RST_NR_PER_BANK + 24,
 85	[MT6735_PERI_RST0_I2C3]			= 0 * RST_NR_PER_BANK + 25,
 86	[MT6735_PERI_RST0_USB]			= 0 * RST_NR_PER_BANK + 28,
 87
 88	[MT6735_PERI_RST1_SPI0]			= 1 * RST_NR_PER_BANK + 1,
 89};
 90
 91static const struct mtk_clk_rst_desc pericfg_resets = {
 92	.version = MTK_RST_SIMPLE,
 93	.rst_bank_ofs = pericfg_rst_bank_ofs,
 94	.rst_bank_nr = ARRAY_SIZE(pericfg_rst_bank_ofs),
 95	.rst_idx_map = pericfg_rst_idx_map,
 96	.rst_idx_map_nr = ARRAY_SIZE(pericfg_rst_idx_map)
 97};
 98
 99static const struct mtk_clk_desc pericfg_clks = {
100	.clks = pericfg_gates,
101	.num_clks = ARRAY_SIZE(pericfg_gates),
102
103	.rst_desc = &pericfg_resets
104};
105
106static const struct of_device_id of_match_mt6735_pericfg[] = {
107	{ .compatible = "mediatek,mt6735-pericfg", .data = &pericfg_clks },
108	{ /* sentinel */ }
109};
110MODULE_DEVICE_TABLE(of, of_match_mt6735_pericfg);
111
112static struct platform_driver clk_mt6735_pericfg = {
113	.probe = mtk_clk_simple_probe,
114	.remove = mtk_clk_simple_remove,
115	.driver = {
116		.name = "clk-mt6735-pericfg",
117		.of_match_table = of_match_mt6735_pericfg,
118	},
119};
120module_platform_driver(clk_mt6735_pericfg);
121
122MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
123MODULE_DESCRIPTION("MediaTek MT6735 pericfg clock driver");
124MODULE_LICENSE("GPL");