clk-mt6735-mfgcfg.c

 1// SPDX-License-Identifier: GPL-2.0
 2/*
 3 * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
 4 */
 5
 6#include <linux/clk-provider.h>
 7#include <linux/platform_device.h>
 8
 9#include "clk-gate.h"
10#include "clk-mtk.h"
11
12#include <dt-bindings/clock/mediatek,mt6735-mfgcfg.h>
13
14#define MFG_CG_CON			0x00
15#define MFG_CG_SET			0x04
16#define MFG_CG_CLR			0x08
17#define MFG_RESET			0x0c
18
19static struct mtk_gate_regs mfgcfg_cg_regs = {
20	.set_ofs = MFG_CG_SET,
21	.clr_ofs = MFG_CG_CLR,
22	.sta_ofs = MFG_CG_CON,
23};
24
25static const struct mtk_gate mfgcfg_gates[] = {
26	GATE_MTK(CLK_MFG_BG3D, "bg3d", "mfg_sel", &mfgcfg_cg_regs, 0, &mtk_clk_gate_ops_setclr),
27};
28
29static u16 mfgcfg_rst_ofs[] = { MFG_RESET };
30
31static const struct mtk_clk_rst_desc mfgcfg_resets = {
32	.version = MTK_RST_SIMPLE,
33	.rst_bank_ofs = mfgcfg_rst_ofs,
34	.rst_bank_nr = ARRAY_SIZE(mfgcfg_rst_ofs)
35};
36
37static const struct mtk_clk_desc mfgcfg_clks = {
38	.clks = mfgcfg_gates,
39	.num_clks = ARRAY_SIZE(mfgcfg_gates),
40
41	.rst_desc = &mfgcfg_resets
42};
43
44static const struct of_device_id of_match_mt6735_mfgcfg[] = {
45	{ .compatible = "mediatek,mt6735-mfgcfg", .data = &mfgcfg_clks },
46	{ /* sentinel */ }
47};
48
49static struct platform_driver clk_mt6735_mfgcfg = {
50	.probe = mtk_clk_simple_probe,
51	.remove = mtk_clk_simple_remove,
52	.driver = {
53		.name = "clk-mt6735-mfgcfg",
54		.of_match_table = of_match_mt6735_mfgcfg,
55	},
56};
57module_platform_driver(clk_mt6735_mfgcfg);
58
59MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
60MODULE_DESCRIPTION("Mediatek MT6735 mfgcfg clock and reset driver");
61MODULE_LICENSE("GPL");