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clk-imx8mp.c
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linux-6.19.14/drivers/clk/imx/clk-imx8mp.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright 2019 NXP. 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <linux/clk-provider.h> 8#include <linux/err.h> 9#include <linux/io.h> 10#include <linux/module.h> 11#include <linux/units.h> 12#include <linux/of_address.h> 13#include <linux/platform_device.h> 14#include <linux/slab.h> 15#include <linux/types.h> 16 17#include "clk.h" 18 19static u32 share_count_nand; 20static u32 share_count_media; 21static u32 share_count_usb; 22static u32 share_count_audio; 23 24static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; 25static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; 26static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; 27static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; 28static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; 29static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; 30static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; 31static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; 32static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; 33static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; 34static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; 35 36static const char * const imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", 37 "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", 38 "audio_pll1_out", "sys_pll3_out", }; 39 40static const char * const imx8mp_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", }; 41 42static const char * const imx8mp_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", 43 "vpu_pll_out", "sys_pll1_800m", "audio_pll1_out", 44 "video_pll1_out", "sys_pll3_out", }; 45 46static const char * const imx8mp_ml_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", 47 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", 48 "video_pll1_out", "audio_pll2_out", }; 49 50static const char * const imx8mp_gpu3d_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", 51 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", 52 "video_pll1_out", "audio_pll2_out", }; 53 54static const char * const imx8mp_gpu3d_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", 55 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", 56 "video_pll1_out", "audio_pll2_out", }; 57 58static const char * const imx8mp_gpu2d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", 59 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", 60 "video_pll1_out", "audio_pll2_out", }; 61 62static const char * const imx8mp_audio_axi_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", 63 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", 64 "video_pll1_out", "audio_pll2_out", }; 65 66static const char * const imx8mp_hsio_axi_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", 67 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", 68 "clk_ext4", "audio_pll2_out", }; 69 70static const char * const imx8mp_media_isp_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m", 71 "sys_pll3_out", "sys_pll1_400m", "audio_pll2_out", 72 "clk_ext1", "sys_pll2_500m", }; 73 74static const char * const imx8mp_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", 75 "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", 76 "video_pll1_out", "sys_pll1_100m",}; 77 78static const char * const imx8mp_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", 79 "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", 80 "video_pll1_out", "sys_pll3_out", }; 81 82static const char * const imx8mp_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", 83 "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", 84 "sys_pll2_250m", "audio_pll1_out", }; 85 86static const char * const imx8mp_vpu_bus_sels[] = {"osc_24m", "sys_pll1_800m", "vpu_pll_out", 87 "audio_pll2_out", "sys_pll3_out", "sys_pll2_1000m", 88 "sys_pll2_200m", "sys_pll1_100m", }; 89 90static const char * const imx8mp_media_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m", 91 "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out", 92 "clk_ext1", "sys_pll2_500m", }; 93 94static const char * const imx8mp_media_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m", 95 "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out", 96 "clk_ext1", "sys_pll1_133m", }; 97 98static const char * const imx8mp_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", 99 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", 100 "video_pll1_out", "audio_pll2_out", }; 101 102static const char * const imx8mp_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", 103 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", 104 "video_pll1_out", "audio_pll2_out", }; 105 106static const char * const imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", 107 "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", 108 "video_pll1_out", "audio_pll2_out", }; 109 110static const char * const imx8mp_noc_io_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", 111 "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", 112 "video_pll1_out", "audio_pll2_out", }; 113 114static const char * const imx8mp_ml_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", 115 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", 116 "video_pll1_out", "audio_pll2_out", }; 117 118static const char * const imx8mp_ml_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", 119 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", 120 "video_pll1_out", "audio_pll2_out", }; 121 122static const char * const imx8mp_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", 123 "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", 124 "audio_pll1_out", "video_pll1_out", }; 125 126static const char * const imx8mp_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", 127 "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out", 128 "audio_pll1_out", "video_pll1_out", }; 129 130static const char * const imx8mp_mipi_dsi_esc_rx_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", 131 "sys_pll1_800m", "sys_pll2_1000m", 132 "sys_pll3_out", "clk_ext3", "audio_pll2_out", }; 133 134static const char * const imx8mp_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m", 135 "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", 136 "audio_pll1_out", "sys_pll1_266m", }; 137 138static const char * const imx8mp_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", 139 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", 140 "sys_pll2_250m", "audio_pll2_out", }; 141 142static const char * const imx8mp_vpu_g1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", 143 "sys_pll2_1000m", "sys_pll1_100m", "sys_pll2_125m", 144 "sys_pll3_out", "audio_pll1_out", }; 145 146static const char * const imx8mp_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", 147 "sys_pll2_1000m", "sys_pll1_100m", "sys_pll2_125m", 148 "sys_pll3_out", "audio_pll1_out", }; 149 150static const char * const imx8mp_can1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", 151 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", 152 "sys_pll2_250m", "audio_pll2_out", }; 153 154static const char * const imx8mp_can2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", 155 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", 156 "sys_pll2_250m", "audio_pll2_out", }; 157 158static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", 159 "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", 160 "sys_pll1_160m", "sys_pll1_200m", }; 161 162static const char * const imx8mp_i2c5_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", 163 "sys_pll3_out", "audio_pll1_out", "video_pll1_out", 164 "audio_pll2_out", "sys_pll1_133m", }; 165 166static const char * const imx8mp_i2c6_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", 167 "sys_pll3_out", "audio_pll1_out", "video_pll1_out", 168 "audio_pll2_out", "sys_pll1_133m", }; 169 170static const char * const imx8mp_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", 171 "video_pll1_out", "sys_pll1_133m", "osc_hdmi", 172 "clk_ext1", "clk_ext2", }; 173 174static const char * const imx8mp_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", 175 "video_pll1_out", "sys_pll1_133m", "osc_hdmi", 176 "clk_ext2", "clk_ext3", }; 177 178static const char * const imx8mp_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", 179 "video_pll1_out", "sys_pll1_133m", "osc_hdmi", 180 "clk_ext3", "clk_ext4", }; 181 182static const char * const imx8mp_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", 183 "video_pll1_out", "sys_pll1_133m", "osc_hdmi", 184 "clk_ext2", "clk_ext3", }; 185 186static const char * const imx8mp_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", 187 "video_pll1_out", "sys_pll1_133m", "osc_hdmi", 188 "clk_ext3", "clk_ext4", }; 189 190static const char * const imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", 191 "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", 192 "video_pll1_out", "clk_ext4", }; 193 194static const char * const imx8mp_enet_qos_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", 195 "clk_ext1", "clk_ext2", "clk_ext3", 196 "clk_ext4", "video_pll1_out", }; 197 198static const char * const imx8mp_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", 199 "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", 200 "video_pll1_out", "clk_ext4", }; 201 202static const char * const imx8mp_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", 203 "clk_ext1", "clk_ext2", "clk_ext3", 204 "clk_ext4", "video_pll1_out", }; 205 206static const char * const imx8mp_enet_phy_ref_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", 207 "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", 208 "video_pll1_out", "audio_pll2_out", }; 209 210static const char * const imx8mp_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", 211 "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", 212 "sys_pll2_250m", "video_pll1_out", }; 213 214static const char * const imx8mp_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", 215 "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", 216 "sys_pll3_out", "sys_pll1_100m", }; 217 218static const char * const imx8mp_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", 219 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", 220 "audio_pll2_out", "sys_pll1_100m", }; 221 222static const char * const imx8mp_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", 223 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", 224 "audio_pll2_out", "sys_pll1_100m", }; 225 226static const char * const imx8mp_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", 227 "sys_pll3_out", "audio_pll1_out", "video_pll1_out", 228 "audio_pll2_out", "sys_pll1_133m", }; 229 230static const char * const imx8mp_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", 231 "sys_pll3_out", "audio_pll1_out", "video_pll1_out", 232 "audio_pll2_out", "sys_pll1_133m", }; 233 234static const char * const imx8mp_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", 235 "sys_pll3_out", "audio_pll1_out", "video_pll1_out", 236 "audio_pll2_out", "sys_pll1_133m", }; 237 238static const char * const imx8mp_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", 239 "sys_pll3_out", "audio_pll1_out", "video_pll1_out", 240 "audio_pll2_out", "sys_pll1_133m", }; 241 242static const char * const imx8mp_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", 243 "sys_pll2_100m", "sys_pll3_out", "clk_ext2", 244 "clk_ext4", "audio_pll2_out", }; 245 246static const char * const imx8mp_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", 247 "sys_pll2_100m", "sys_pll3_out", "clk_ext2", 248 "clk_ext3", "audio_pll2_out", }; 249 250static const char * const imx8mp_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", 251 "sys_pll2_100m", "sys_pll3_out", "clk_ext2", 252 "clk_ext4", "audio_pll2_out", }; 253 254static const char * const imx8mp_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", 255 "sys_pll2_100m", "sys_pll3_out", "clk_ext2", 256 "clk_ext3", "audio_pll2_out", }; 257 258static const char * const imx8mp_usb_core_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", 259 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", 260 "clk_ext3", "audio_pll2_out", }; 261 262static const char * const imx8mp_usb_phy_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", 263 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", 264 "clk_ext3", "audio_pll2_out", }; 265 266static const char * const imx8mp_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", 267 "sys_pll2_100m", "sys_pll1_800m", 268 "sys_pll2_500m", "clk_ext4", "audio_pll2_out" }; 269 270static const char * const imx8mp_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", 271 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", 272 "sys_pll2_250m", "audio_pll2_out", }; 273 274static const char * const imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", 275 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", 276 "sys_pll2_250m", "audio_pll2_out", }; 277 278static const char * const imx8mp_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", 279 "sys_pll1_40m", "sys_pll3_out", "clk_ext1", 280 "sys_pll1_80m", "video_pll1_out", }; 281 282static const char * const imx8mp_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", 283 "sys_pll1_40m", "sys_pll3_out", "clk_ext1", 284 "sys_pll1_80m", "video_pll1_out", }; 285 286static const char * const imx8mp_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", 287 "sys_pll1_40m", "sys_pll3_out", "clk_ext2", 288 "sys_pll1_80m", "video_pll1_out", }; 289 290static const char * const imx8mp_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", 291 "sys_pll1_40m", "sys_pll3_out", "clk_ext2", 292 "sys_pll1_80m", "video_pll1_out", }; 293 294static const char * const imx8mp_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", 295 "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", 296 "audio_pll1_out", "clk_ext1" }; 297 298static const char * const imx8mp_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", 299 "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", 300 "audio_pll1_out", "clk_ext2" }; 301 302static const char * const imx8mp_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", 303 "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", 304 "audio_pll1_out", "clk_ext3" }; 305 306static const char * const imx8mp_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", 307 "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", 308 "audio_pll1_out", "clk_ext1" }; 309 310static const char * const imx8mp_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", 311 "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", 312 "audio_pll1_out", "clk_ext2" }; 313 314static const char * const imx8mp_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", 315 "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", 316 "audio_pll1_out", "clk_ext3" }; 317 318static const char * const imx8mp_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", 319 "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", 320 "sys_pll1_80m", "sys_pll2_166m" }; 321 322static const char * const imx8mp_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out", 323 "sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m", 324 "sys_pll2_500m", "sys_pll1_100m" }; 325 326static const char * const imx8mp_ipp_do_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_133m", 327 "sys_pll1_200m", "audio_pll2_out", "sys_pll2_500m", 328 "vpu_pll_out", "sys_pll1_80m" }; 329 330static const char * const imx8mp_ipp_do_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", 331 "sys_pll1_166m", "sys_pll3_out", "audio_pll1_out", 332 "video_pll1_out", "osc_32k" }; 333 334static const char * const imx8mp_hdmi_fdcc_tst_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", 335 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", 336 "audio_pll2_out", "video_pll1_out", }; 337 338static const char * const imx8mp_hdmi_24m_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", 339 "sys_pll3_out", "audio_pll1_out", "video_pll1_out", 340 "audio_pll2_out", "sys_pll1_133m", }; 341 342static const char * const imx8mp_hdmi_ref_266m_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll3_out", 343 "sys_pll2_333m", "sys_pll1_266m", "sys_pll2_200m", 344 "audio_pll1_out", "video_pll1_out", }; 345 346static const char * const imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", 347 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", 348 "audio_pll2_out", "sys_pll1_100m", }; 349 350static const char * const imx8mp_media_cam1_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", 351 "sys_pll1_800m", "sys_pll2_1000m", 352 "sys_pll3_out", "audio_pll2_out", 353 "video_pll1_out", }; 354 355static const char * const imx8mp_media_mipi_phy1_ref_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", 356 "sys_pll1_800m", "sys_pll2_1000m", 357 "clk_ext2", "audio_pll2_out", 358 "video_pll1_out", }; 359 360static const char * const imx8mp_media_disp_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", 361 "audio_pll1_out", "sys_pll1_800m", 362 "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; 363 364static const char * const imx8mp_media_cam2_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", 365 "sys_pll1_800m", "sys_pll2_1000m", 366 "sys_pll3_out", "audio_pll2_out", 367 "video_pll1_out", }; 368 369static const char * const imx8mp_media_ldb_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", 370 "sys_pll1_800m", "sys_pll2_1000m", 371 "clk_ext2", "audio_pll2_out", 372 "video_pll1_out", }; 373 374static const char * const imx8mp_memrepair_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", 375 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", 376 "clk_ext3", "audio_pll2_out", }; 377 378static const char * const imx8mp_media_mipi_test_byte_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", 379 "sys_pll3_out", "sys_pll2_100m", 380 "sys_pll1_80m", "sys_pll1_160m", 381 "sys_pll1_200m", }; 382 383static const char * const imx8mp_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", 384 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", 385 "sys_pll2_250m", "audio_pll2_out", }; 386 387static const char * const imx8mp_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", 388 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", 389 "clk_ext3", "audio_pll2_out", }; 390 391static const char * const imx8mp_vpu_vc8000e_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", 392 "sys_pll2_1000m", "audio_pll2_out", "sys_pll2_125m", 393 "sys_pll3_out", "audio_pll1_out", }; 394 395static const char * const imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", 396 "video_pll1_out", "sys_pll1_133m", "osc_hdmi", 397 "clk_ext3", "clk_ext4", }; 398 399static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; 400 401static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out", 402 "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", 403 "arm_pll_out", "sys_pll1_out", "sys_pll2_out", 404 "sys_pll3_out", "dummy", "dummy", "osc_24m", 405 "dummy", "osc_32k"}; 406 407static struct clk_hw **hws; 408static struct clk_hw_onecell_data *clk_hw_data; 409 410struct imx8mp_clock_constraints { 411 unsigned int clkid; 412 u32 maxrate; 413}; 414 415/* 416 * Below tables are taken from IMX8MPCEC Rev. 2.1, 07/2023 417 * Table 13. Maximum frequency of modules. 418 * Probable typos fixed are marked with a comment. 419 */ 420static const struct imx8mp_clock_constraints imx8mp_clock_common_constraints[] = { 421 { IMX8MP_CLK_A53_DIV, 1000 * HZ_PER_MHZ }, 422 { IMX8MP_CLK_ENET_AXI, 266666667 }, /* Datasheet claims 266MHz */ 423 { IMX8MP_CLK_NAND_USDHC_BUS, 266666667 }, /* Datasheet claims 266MHz */ 424 { IMX8MP_CLK_MEDIA_APB, 200 * HZ_PER_MHZ }, 425 { IMX8MP_CLK_HDMI_APB, 133333333 }, /* Datasheet claims 133MHz */ 426 { IMX8MP_CLK_ML_AXI, 800 * HZ_PER_MHZ }, 427 { IMX8MP_CLK_AHB, 133333333 }, 428 { IMX8MP_CLK_IPG_ROOT, 66666667 }, 429 { IMX8MP_CLK_AUDIO_AHB, 400 * HZ_PER_MHZ }, 430 { IMX8MP_CLK_MEDIA_DISP2_PIX, 170 * HZ_PER_MHZ }, 431 { IMX8MP_CLK_DRAM_ALT, 666666667 }, 432 { IMX8MP_CLK_DRAM_APB, 200 * HZ_PER_MHZ }, 433 { IMX8MP_CLK_CAN1, 80 * HZ_PER_MHZ }, 434 { IMX8MP_CLK_CAN2, 80 * HZ_PER_MHZ }, 435 { IMX8MP_CLK_PCIE_AUX, 10 * HZ_PER_MHZ }, 436 { IMX8MP_CLK_I2C5, 66666667 }, /* Datasheet claims 66MHz */ 437 { IMX8MP_CLK_I2C6, 66666667 }, /* Datasheet claims 66MHz */ 438 { IMX8MP_CLK_SAI1, 66666667 }, /* Datasheet claims 66MHz */ 439 { IMX8MP_CLK_SAI2, 66666667 }, /* Datasheet claims 66MHz */ 440 { IMX8MP_CLK_SAI3, 66666667 }, /* Datasheet claims 66MHz */ 441 { IMX8MP_CLK_SAI5, 66666667 }, /* Datasheet claims 66MHz */ 442 { IMX8MP_CLK_SAI6, 66666667 }, /* Datasheet claims 66MHz */ 443 { IMX8MP_CLK_ENET_QOS, 125 * HZ_PER_MHZ }, 444 { IMX8MP_CLK_ENET_QOS_TIMER, 200 * HZ_PER_MHZ }, 445 { IMX8MP_CLK_ENET_REF, 125 * HZ_PER_MHZ }, 446 { IMX8MP_CLK_ENET_TIMER, 125 * HZ_PER_MHZ }, 447 { IMX8MP_CLK_ENET_PHY_REF, 125 * HZ_PER_MHZ }, 448 { IMX8MP_CLK_NAND, 500 * HZ_PER_MHZ }, 449 { IMX8MP_CLK_QSPI, 400 * HZ_PER_MHZ }, 450 { IMX8MP_CLK_USDHC1, 400 * HZ_PER_MHZ }, 451 { IMX8MP_CLK_USDHC2, 400 * HZ_PER_MHZ }, 452 { IMX8MP_CLK_I2C1, 66666667 }, /* Datasheet claims 66MHz */ 453 { IMX8MP_CLK_I2C2, 66666667 }, /* Datasheet claims 66MHz */ 454 { IMX8MP_CLK_I2C3, 66666667 }, /* Datasheet claims 66MHz */ 455 { IMX8MP_CLK_I2C4, 66666667 }, /* Datasheet claims 66MHz */ 456 { IMX8MP_CLK_UART1, 80 * HZ_PER_MHZ }, 457 { IMX8MP_CLK_UART2, 80 * HZ_PER_MHZ }, 458 { IMX8MP_CLK_UART3, 80 * HZ_PER_MHZ }, 459 { IMX8MP_CLK_UART4, 80 * HZ_PER_MHZ }, 460 { IMX8MP_CLK_ECSPI1, 80 * HZ_PER_MHZ }, 461 { IMX8MP_CLK_ECSPI2, 80 * HZ_PER_MHZ }, 462 { IMX8MP_CLK_PWM1, 66666667 }, /* Datasheet claims 66MHz */ 463 { IMX8MP_CLK_PWM2, 66666667 }, /* Datasheet claims 66MHz */ 464 { IMX8MP_CLK_PWM3, 66666667 }, /* Datasheet claims 66MHz */ 465 { IMX8MP_CLK_PWM4, 66666667 }, /* Datasheet claims 66MHz */ 466 { IMX8MP_CLK_GPT1, 100 * HZ_PER_MHZ }, 467 { IMX8MP_CLK_GPT2, 100 * HZ_PER_MHZ }, 468 { IMX8MP_CLK_GPT3, 100 * HZ_PER_MHZ }, 469 { IMX8MP_CLK_GPT4, 100 * HZ_PER_MHZ }, 470 { IMX8MP_CLK_GPT5, 100 * HZ_PER_MHZ }, 471 { IMX8MP_CLK_GPT6, 100 * HZ_PER_MHZ }, 472 { IMX8MP_CLK_WDOG, 66666667 }, /* Datasheet claims 66MHz */ 473 { IMX8MP_CLK_IPP_DO_CLKO1, 200 * HZ_PER_MHZ }, 474 { IMX8MP_CLK_IPP_DO_CLKO2, 200 * HZ_PER_MHZ }, 475 { IMX8MP_CLK_HDMI_REF_266M, 266 * HZ_PER_MHZ }, 476 { IMX8MP_CLK_USDHC3, 400 * HZ_PER_MHZ }, 477 { IMX8MP_CLK_MEDIA_MIPI_PHY1_REF, 300 * HZ_PER_MHZ }, 478 { IMX8MP_CLK_MEDIA_DISP1_PIX, 250 * HZ_PER_MHZ }, 479 { IMX8MP_CLK_MEDIA_CAM2_PIX, 277 * HZ_PER_MHZ }, 480 { IMX8MP_CLK_MEDIA_LDB, 595 * HZ_PER_MHZ }, 481 { IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE, 200 * HZ_PER_MHZ }, 482 { IMX8MP_CLK_ECSPI3, 80 * HZ_PER_MHZ }, 483 { IMX8MP_CLK_PDM, 200 * HZ_PER_MHZ }, 484 { IMX8MP_CLK_SAI7, 66666667 }, /* Datasheet claims 66MHz */ 485 { IMX8MP_CLK_MAIN_AXI, 400 * HZ_PER_MHZ }, 486 { /* Sentinel */ } 487}; 488 489static const struct imx8mp_clock_constraints imx8mp_clock_nominal_constraints[] = { 490 { IMX8MP_CLK_M7_CORE, 600 * HZ_PER_MHZ }, 491 { IMX8MP_CLK_ML_CORE, 800 * HZ_PER_MHZ }, 492 { IMX8MP_CLK_GPU3D_CORE, 800 * HZ_PER_MHZ }, 493 { IMX8MP_CLK_GPU3D_SHADER_CORE, 800 * HZ_PER_MHZ }, 494 { IMX8MP_CLK_GPU2D_CORE, 800 * HZ_PER_MHZ }, 495 { IMX8MP_CLK_AUDIO_AXI_SRC, 600 * HZ_PER_MHZ }, 496 { IMX8MP_CLK_HSIO_AXI, 400 * HZ_PER_MHZ }, 497 { IMX8MP_CLK_MEDIA_ISP, 400 * HZ_PER_MHZ }, 498 { IMX8MP_CLK_VPU_BUS, 600 * HZ_PER_MHZ }, 499 { IMX8MP_CLK_MEDIA_AXI, 400 * HZ_PER_MHZ }, 500 { IMX8MP_CLK_HDMI_AXI, 400 * HZ_PER_MHZ }, 501 { IMX8MP_CLK_GPU_AXI, 600 * HZ_PER_MHZ }, 502 { IMX8MP_CLK_GPU_AHB, 300 * HZ_PER_MHZ }, 503 { IMX8MP_CLK_NOC, 800 * HZ_PER_MHZ }, 504 { IMX8MP_CLK_NOC_IO, 600 * HZ_PER_MHZ }, 505 { IMX8MP_CLK_ML_AHB, 300 * HZ_PER_MHZ }, 506 { IMX8MP_CLK_VPU_G1, 600 * HZ_PER_MHZ }, 507 { IMX8MP_CLK_VPU_G2, 500 * HZ_PER_MHZ }, 508 { IMX8MP_CLK_MEDIA_CAM1_PIX, 400 * HZ_PER_MHZ }, 509 { IMX8MP_CLK_VPU_VC8000E, 400 * HZ_PER_MHZ }, /* Datasheet claims 500MHz */ 510 { IMX8MP_CLK_DRAM_CORE, 800 * HZ_PER_MHZ }, 511 { IMX8MP_CLK_GIC, 400 * HZ_PER_MHZ }, 512 { /* Sentinel */ } 513}; 514 515static const struct imx8mp_clock_constraints imx8mp_clock_overdrive_constraints[] = { 516 { IMX8MP_CLK_M7_CORE, 800 * HZ_PER_MHZ}, 517 { IMX8MP_CLK_ML_CORE, 1000 * HZ_PER_MHZ }, 518 { IMX8MP_CLK_GPU3D_CORE, 1000 * HZ_PER_MHZ }, 519 { IMX8MP_CLK_GPU3D_SHADER_CORE, 1000 * HZ_PER_MHZ }, 520 { IMX8MP_CLK_GPU2D_CORE, 1000 * HZ_PER_MHZ }, 521 { IMX8MP_CLK_AUDIO_AXI_SRC, 800 * HZ_PER_MHZ }, 522 { IMX8MP_CLK_HSIO_AXI, 500 * HZ_PER_MHZ }, 523 { IMX8MP_CLK_MEDIA_ISP, 500 * HZ_PER_MHZ }, 524 { IMX8MP_CLK_VPU_BUS, 800 * HZ_PER_MHZ }, 525 { IMX8MP_CLK_MEDIA_AXI, 500 * HZ_PER_MHZ }, 526 { IMX8MP_CLK_HDMI_AXI, 500 * HZ_PER_MHZ }, 527 { IMX8MP_CLK_GPU_AXI, 800 * HZ_PER_MHZ }, 528 { IMX8MP_CLK_GPU_AHB, 400 * HZ_PER_MHZ }, 529 { IMX8MP_CLK_NOC, 1000 * HZ_PER_MHZ }, 530 { IMX8MP_CLK_NOC_IO, 800 * HZ_PER_MHZ }, 531 { IMX8MP_CLK_ML_AHB, 400 * HZ_PER_MHZ }, 532 { IMX8MP_CLK_VPU_G1, 800 * HZ_PER_MHZ }, 533 { IMX8MP_CLK_VPU_G2, 700 * HZ_PER_MHZ }, 534 { IMX8MP_CLK_MEDIA_CAM1_PIX, 500 * HZ_PER_MHZ }, 535 { IMX8MP_CLK_VPU_VC8000E, 500 * HZ_PER_MHZ }, /* Datasheet claims 400MHz */ 536 { IMX8MP_CLK_DRAM_CORE, 1000 * HZ_PER_MHZ }, 537 { IMX8MP_CLK_GIC, 500 * HZ_PER_MHZ }, 538 { /* Sentinel */ } 539}; 540 541static void imx8mp_clocks_apply_constraints(const struct imx8mp_clock_constraints constraints[]) 542{ 543 const struct imx8mp_clock_constraints *constr; 544 545 for (constr = constraints; constr->clkid; constr++) 546 clk_hw_set_rate_range(hws[constr->clkid], 0, constr->maxrate); 547} 548 549static int imx8mp_clocks_probe(struct platform_device *pdev) 550{ 551 struct device *dev = &pdev->dev; 552 struct device_node *np; 553 void __iomem *anatop_base, *ccm_base; 554 const char *opmode; 555 int err; 556 557 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); 558 anatop_base = devm_of_iomap(dev, np, 0, NULL); 559 of_node_put(np); 560 if (WARN_ON(IS_ERR(anatop_base))) 561 return PTR_ERR(anatop_base); 562 563 np = dev->of_node; 564 ccm_base = devm_platform_ioremap_resource(pdev, 0); 565 if (WARN_ON(IS_ERR(ccm_base))) 566 return PTR_ERR(ccm_base); 567 568 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MP_CLK_END), GFP_KERNEL); 569 if (WARN_ON(!clk_hw_data)) 570 return -ENOMEM; 571 572 clk_hw_data->num = IMX8MP_CLK_END; 573 hws = clk_hw_data->hws; 574 575 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); 576 hws[IMX8MP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); 577 hws[IMX8MP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); 578 hws[IMX8MP_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); 579 hws[IMX8MP_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); 580 hws[IMX8MP_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); 581 hws[IMX8MP_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); 582 583 hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 584 hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 585 hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 586 hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 587 hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 588 hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 589 hws[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", anatop_base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 590 hws[IMX8MP_SYS_PLL1_REF_SEL] = imx_clk_hw_mux("sys_pll1_ref_sel", anatop_base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 591 hws[IMX8MP_SYS_PLL2_REF_SEL] = imx_clk_hw_mux("sys_pll2_ref_sel", anatop_base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 592 hws[IMX8MP_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", anatop_base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 593 594 hws[IMX8MP_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", anatop_base, &imx_1443x_pll); 595 hws[IMX8MP_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", anatop_base + 0x14, &imx_1443x_pll); 596 hws[IMX8MP_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", anatop_base + 0x28, &imx_1443x_pll); 597 hws[IMX8MP_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", anatop_base + 0x50, &imx_1443x_dram_pll); 598 hws[IMX8MP_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", anatop_base + 0x64, &imx_1416x_pll); 599 hws[IMX8MP_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", anatop_base + 0x74, &imx_1416x_pll); 600 hws[IMX8MP_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", anatop_base + 0x84, &imx_1416x_pll); 601 hws[IMX8MP_SYS_PLL1] = imx_clk_hw_pll14xx("sys_pll1", "sys_pll1_ref_sel", anatop_base + 0x94, &imx_1416x_pll); 602 hws[IMX8MP_SYS_PLL2] = imx_clk_hw_pll14xx("sys_pll2", "sys_pll2_ref_sel", anatop_base + 0x104, &imx_1416x_pll); 603 hws[IMX8MP_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", anatop_base + 0x114, &imx_1416x_pll); 604 605 hws[IMX8MP_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); 606 hws[IMX8MP_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); 607 hws[IMX8MP_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", anatop_base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT); 608 hws[IMX8MP_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", anatop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); 609 hws[IMX8MP_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", anatop_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); 610 hws[IMX8MP_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", anatop_base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT); 611 hws[IMX8MP_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", anatop_base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); 612 hws[IMX8MP_SYS_PLL1_BYPASS] = imx_clk_hw_mux_flags("sys_pll1_bypass", anatop_base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT); 613 hws[IMX8MP_SYS_PLL2_BYPASS] = imx_clk_hw_mux_flags("sys_pll2_bypass", anatop_base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT); 614 hws[IMX8MP_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", anatop_base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); 615 616 hws[IMX8MP_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", anatop_base, 13); 617 hws[IMX8MP_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", anatop_base + 0x14, 13); 618 hws[IMX8MP_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", anatop_base + 0x28, 13); 619 hws[IMX8MP_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", anatop_base + 0x50, 13); 620 hws[IMX8MP_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", anatop_base + 0x64, 11); 621 hws[IMX8MP_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", anatop_base + 0x74, 11); 622 hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11); 623 hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11); 624 625 hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11); 626 627 hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); 628 hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); 629 hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); 630 hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); 631 hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); 632 hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); 633 hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); 634 hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); 635 hws[IMX8MP_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); 636 637 hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11); 638 639 hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); 640 hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); 641 hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); 642 hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); 643 hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); 644 hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); 645 hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); 646 hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); 647 hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); 648 649 hws[IMX8MP_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", anatop_base + 0x128, 4, 4, 650 imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels)); 651 hws[IMX8MP_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", anatop_base + 0x128, 0, 4); 652 hws[IMX8MP_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", anatop_base + 0x128, 8); 653 hws[IMX8MP_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", anatop_base + 0x128, 20, 4, 654 imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels)); 655 hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128, 16, 4); 656 hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", anatop_base + 0x128, 24); 657 658 hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000); 659 hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV]; 660 hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV]; 661 hws[IMX8MP_CLK_M7_CORE] = imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base + 0x8080); 662 hws[IMX8MP_CLK_ML_CORE] = imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, ccm_base + 0x8100); 663 hws[IMX8MP_CLK_GPU3D_CORE] = imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels, ccm_base + 0x8180); 664 hws[IMX8MP_CLK_GPU3D_SHADER_CORE] = imx8m_clk_hw_composite("gpu3d_shader_core", imx8mp_gpu3d_shader_sels, ccm_base + 0x8200); 665 hws[IMX8MP_CLK_GPU2D_CORE] = imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, ccm_base + 0x8280); 666 hws[IMX8MP_CLK_AUDIO_AXI] = imx8m_clk_hw_composite("audio_axi", imx8mp_audio_axi_sels, ccm_base + 0x8300); 667 hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI]; 668 hws[IMX8MP_CLK_HSIO_AXI] = imx8m_clk_hw_composite("hsio_axi", imx8mp_hsio_axi_sels, ccm_base + 0x8380); 669 hws[IMX8MP_CLK_MEDIA_ISP] = imx8m_clk_hw_composite("media_isp", imx8mp_media_isp_sels, ccm_base + 0x8400); 670 671 /* CORE SEL */ 672 hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels)); 673 674 hws[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mp_main_axi_sels, ccm_base + 0x8800); 675 hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mp_enet_axi_sels, ccm_base + 0x8880); 676 hws[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900); 677 hws[IMX8MP_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mp_vpu_bus_sels, ccm_base + 0x8980); 678 hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite_bus("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00); 679 hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite_bus("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80); 680 hws[IMX8MP_CLK_HDMI_APB] = imx8m_clk_hw_composite_bus("hdmi_apb", imx8mp_media_apb_sels, ccm_base + 0x8b00); 681 hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite_bus("hdmi_axi", imx8mp_media_axi_sels, ccm_base + 0x8b80); 682 hws[IMX8MP_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mp_gpu_axi_sels, ccm_base + 0x8c00); 683 hws[IMX8MP_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mp_gpu_ahb_sels, ccm_base + 0x8c80); 684 hws[IMX8MP_CLK_NOC] = imx8m_clk_hw_composite_bus_critical("noc", imx8mp_noc_sels, ccm_base + 0x8d00); 685 hws[IMX8MP_CLK_NOC_IO] = imx8m_clk_hw_composite_bus_critical("noc_io", imx8mp_noc_io_sels, ccm_base + 0x8d80); 686 hws[IMX8MP_CLK_ML_AXI] = imx8m_clk_hw_composite_bus("ml_axi", imx8mp_ml_axi_sels, ccm_base + 0x8e00); 687 hws[IMX8MP_CLK_ML_AHB] = imx8m_clk_hw_composite_bus("ml_ahb", imx8mp_ml_ahb_sels, ccm_base + 0x8e80); 688 689 hws[IMX8MP_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb_root", imx8mp_ahb_sels, ccm_base + 0x9000); 690 hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100); 691 hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200); 692 hws[IMX8MP_CLK_MEDIA_DISP2_PIX] = imx8m_clk_hw_composite_bus_flags("media_disp2_pix", imx8mp_media_disp_pix_sels, ccm_base + 0x9300, CLK_SET_RATE_PARENT); 693 694 hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1); 695 696 hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000); 697 hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080); 698 hws[IMX8MP_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1_sels, ccm_base + 0xa100); 699 hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180); 700 hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200); 701 hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, ccm_base + 0xa280); 702 hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", imx8mp_pcie_aux_sels, ccm_base + 0xa400); 703 hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, ccm_base + 0xa480); 704 hws[IMX8MP_CLK_I2C6] = imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels, ccm_base + 0xa500); 705 hws[IMX8MP_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels, ccm_base + 0xa580); 706 hws[IMX8MP_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels, ccm_base + 0xa600); 707 hws[IMX8MP_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mp_sai3_sels, ccm_base + 0xa680); 708 hws[IMX8MP_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mp_sai5_sels, ccm_base + 0xa780); 709 hws[IMX8MP_CLK_SAI6] = imx8m_clk_hw_composite("sai6", imx8mp_sai6_sels, ccm_base + 0xa800); 710 hws[IMX8MP_CLK_ENET_QOS] = imx8m_clk_hw_composite("enet_qos", imx8mp_enet_qos_sels, ccm_base + 0xa880); 711 hws[IMX8MP_CLK_ENET_QOS_TIMER] = imx8m_clk_hw_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, ccm_base + 0xa900); 712 hws[IMX8MP_CLK_ENET_REF] = imx8m_clk_hw_composite("enet_ref", imx8mp_enet_ref_sels, ccm_base + 0xa980); 713 hws[IMX8MP_CLK_ENET_TIMER] = imx8m_clk_hw_composite("enet_timer", imx8mp_enet_timer_sels, ccm_base + 0xaa00); 714 hws[IMX8MP_CLK_ENET_PHY_REF] = imx8m_clk_hw_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, ccm_base + 0xaa80); 715 hws[IMX8MP_CLK_NAND] = imx8m_clk_hw_composite("nand", imx8mp_nand_sels, ccm_base + 0xab00); 716 hws[IMX8MP_CLK_QSPI] = imx8m_clk_hw_composite("qspi", imx8mp_qspi_sels, ccm_base + 0xab80); 717 hws[IMX8MP_CLK_USDHC1] = imx8m_clk_hw_composite("usdhc1", imx8mp_usdhc1_sels, ccm_base + 0xac00); 718 hws[IMX8MP_CLK_USDHC2] = imx8m_clk_hw_composite("usdhc2", imx8mp_usdhc2_sels, ccm_base + 0xac80); 719 hws[IMX8MP_CLK_I2C1] = imx8m_clk_hw_composite("i2c1", imx8mp_i2c1_sels, ccm_base + 0xad00); 720 hws[IMX8MP_CLK_I2C2] = imx8m_clk_hw_composite("i2c2", imx8mp_i2c2_sels, ccm_base + 0xad80); 721 hws[IMX8MP_CLK_I2C3] = imx8m_clk_hw_composite("i2c3", imx8mp_i2c3_sels, ccm_base + 0xae00); 722 hws[IMX8MP_CLK_I2C4] = imx8m_clk_hw_composite("i2c4", imx8mp_i2c4_sels, ccm_base + 0xae80); 723 724 hws[IMX8MP_CLK_UART1] = imx8m_clk_hw_composite("uart1", imx8mp_uart1_sels, ccm_base + 0xaf00); 725 hws[IMX8MP_CLK_UART2] = imx8m_clk_hw_composite("uart2", imx8mp_uart2_sels, ccm_base + 0xaf80); 726 hws[IMX8MP_CLK_UART3] = imx8m_clk_hw_composite("uart3", imx8mp_uart3_sels, ccm_base + 0xb000); 727 hws[IMX8MP_CLK_UART4] = imx8m_clk_hw_composite("uart4", imx8mp_uart4_sels, ccm_base + 0xb080); 728 hws[IMX8MP_CLK_USB_CORE_REF] = imx8m_clk_hw_composite("usb_core_ref", imx8mp_usb_core_ref_sels, ccm_base + 0xb100); 729 hws[IMX8MP_CLK_USB_PHY_REF] = imx8m_clk_hw_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, ccm_base + 0xb180); 730 hws[IMX8MP_CLK_GIC] = imx8m_clk_hw_composite_critical("gic", imx8mp_gic_sels, ccm_base + 0xb200); 731 hws[IMX8MP_CLK_ECSPI1] = imx8m_clk_hw_composite("ecspi1", imx8mp_ecspi1_sels, ccm_base + 0xb280); 732 hws[IMX8MP_CLK_ECSPI2] = imx8m_clk_hw_composite("ecspi2", imx8mp_ecspi2_sels, ccm_base + 0xb300); 733 hws[IMX8MP_CLK_PWM1] = imx8m_clk_hw_composite("pwm1", imx8mp_pwm1_sels, ccm_base + 0xb380); 734 hws[IMX8MP_CLK_PWM2] = imx8m_clk_hw_composite("pwm2", imx8mp_pwm2_sels, ccm_base + 0xb400); 735 hws[IMX8MP_CLK_PWM3] = imx8m_clk_hw_composite("pwm3", imx8mp_pwm3_sels, ccm_base + 0xb480); 736 hws[IMX8MP_CLK_PWM4] = imx8m_clk_hw_composite("pwm4", imx8mp_pwm4_sels, ccm_base + 0xb500); 737 738 hws[IMX8MP_CLK_GPT1] = imx8m_clk_hw_composite("gpt1", imx8mp_gpt1_sels, ccm_base + 0xb580); 739 hws[IMX8MP_CLK_GPT2] = imx8m_clk_hw_composite("gpt2", imx8mp_gpt2_sels, ccm_base + 0xb600); 740 hws[IMX8MP_CLK_GPT3] = imx8m_clk_hw_composite("gpt3", imx8mp_gpt3_sels, ccm_base + 0xb680); 741 hws[IMX8MP_CLK_GPT4] = imx8m_clk_hw_composite("gpt4", imx8mp_gpt4_sels, ccm_base + 0xb700); 742 hws[IMX8MP_CLK_GPT5] = imx8m_clk_hw_composite("gpt5", imx8mp_gpt5_sels, ccm_base + 0xb780); 743 hws[IMX8MP_CLK_GPT6] = imx8m_clk_hw_composite("gpt6", imx8mp_gpt6_sels, ccm_base + 0xb800); 744 hws[IMX8MP_CLK_WDOG] = imx8m_clk_hw_composite("wdog", imx8mp_wdog_sels, ccm_base + 0xb900); 745 hws[IMX8MP_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk", imx8mp_wrclk_sels, ccm_base + 0xb980); 746 hws[IMX8MP_CLK_IPP_DO_CLKO1] = imx8m_clk_hw_composite("ipp_do_clko1", imx8mp_ipp_do_clko1_sels, ccm_base + 0xba00); 747 hws[IMX8MP_CLK_IPP_DO_CLKO2] = imx8m_clk_hw_composite("ipp_do_clko2", imx8mp_ipp_do_clko2_sels, ccm_base + 0xba80); 748 hws[IMX8MP_CLK_HDMI_FDCC_TST] = imx8m_clk_hw_composite("hdmi_fdcc_tst", imx8mp_hdmi_fdcc_tst_sels, ccm_base + 0xbb00); 749 hws[IMX8MP_CLK_HDMI_24M] = imx8m_clk_hw_composite("hdmi_24m", imx8mp_hdmi_24m_sels, ccm_base + 0xbb80); 750 hws[IMX8MP_CLK_HDMI_REF_266M] = imx8m_clk_hw_composite("hdmi_ref_266m", imx8mp_hdmi_ref_266m_sels, ccm_base + 0xbc00); 751 hws[IMX8MP_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3_sels, ccm_base + 0xbc80); 752 hws[IMX8MP_CLK_MEDIA_CAM1_PIX] = imx8m_clk_hw_composite("media_cam1_pix", imx8mp_media_cam1_pix_sels, ccm_base + 0xbd00); 753 hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_hw_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80); 754 hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite_bus_flags("media_disp1_pix", imx8mp_media_disp_pix_sels, ccm_base + 0xbe00, CLK_SET_RATE_PARENT); 755 hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80); 756 hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00); 757 hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base + 0xbf80); 758 hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = imx8m_clk_hw_composite("media_mipi_test_byte", imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100); 759 hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", imx8mp_ecspi3_sels, ccm_base + 0xc180); 760 hws[IMX8MP_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, ccm_base + 0xc200); 761 hws[IMX8MP_CLK_VPU_VC8000E] = imx8m_clk_hw_composite("vpu_vc8000e", imx8mp_vpu_vc8000e_sels, ccm_base + 0xc280); 762 hws[IMX8MP_CLK_SAI7] = imx8m_clk_hw_composite("sai7", imx8mp_sai7_sels, ccm_base + 0xc300); 763 764 hws[IMX8MP_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4); 765 hws[IMX8MP_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", ccm_base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL); 766 767 hws[IMX8MP_CLK_DRAM1_ROOT] = imx_clk_hw_gate4_flags("dram1_root_clk", "dram_core_clk", ccm_base + 0x4050, 0, CLK_IS_CRITICAL); 768 hws[IMX8MP_CLK_ECSPI1_ROOT] = imx_clk_hw_gate4("ecspi1_root_clk", "ecspi1", ccm_base + 0x4070, 0); 769 hws[IMX8MP_CLK_ECSPI2_ROOT] = imx_clk_hw_gate4("ecspi2_root_clk", "ecspi2", ccm_base + 0x4080, 0); 770 hws[IMX8MP_CLK_ECSPI3_ROOT] = imx_clk_hw_gate4("ecspi3_root_clk", "ecspi3", ccm_base + 0x4090, 0); 771 hws[IMX8MP_CLK_ENET1_ROOT] = imx_clk_hw_gate4("enet1_root_clk", "enet_axi", ccm_base + 0x40a0, 0); 772 hws[IMX8MP_CLK_GPIO1_ROOT] = imx_clk_hw_gate4("gpio1_root_clk", "ipg_root", ccm_base + 0x40b0, 0); 773 hws[IMX8MP_CLK_GPIO2_ROOT] = imx_clk_hw_gate4("gpio2_root_clk", "ipg_root", ccm_base + 0x40c0, 0); 774 hws[IMX8MP_CLK_GPIO3_ROOT] = imx_clk_hw_gate4("gpio3_root_clk", "ipg_root", ccm_base + 0x40d0, 0); 775 hws[IMX8MP_CLK_GPIO4_ROOT] = imx_clk_hw_gate4("gpio4_root_clk", "ipg_root", ccm_base + 0x40e0, 0); 776 hws[IMX8MP_CLK_GPIO5_ROOT] = imx_clk_hw_gate4("gpio5_root_clk", "ipg_root", ccm_base + 0x40f0, 0); 777 hws[IMX8MP_CLK_GPT1_ROOT] = imx_clk_hw_gate4("gpt1_root_clk", "gpt1", ccm_base + 0x4100, 0); 778 hws[IMX8MP_CLK_GPT2_ROOT] = imx_clk_hw_gate4("gpt2_root_clk", "gpt2", ccm_base + 0x4110, 0); 779 hws[IMX8MP_CLK_GPT3_ROOT] = imx_clk_hw_gate4("gpt3_root_clk", "gpt3", ccm_base + 0x4120, 0); 780 hws[IMX8MP_CLK_GPT4_ROOT] = imx_clk_hw_gate4("gpt4_root_clk", "gpt4", ccm_base + 0x4130, 0); 781 hws[IMX8MP_CLK_GPT5_ROOT] = imx_clk_hw_gate4("gpt5_root_clk", "gpt5", ccm_base + 0x4140, 0); 782 hws[IMX8MP_CLK_GPT6_ROOT] = imx_clk_hw_gate4("gpt6_root_clk", "gpt6", ccm_base + 0x4150, 0); 783 hws[IMX8MP_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1", ccm_base + 0x4170, 0); 784 hws[IMX8MP_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", ccm_base + 0x4180, 0); 785 hws[IMX8MP_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", ccm_base + 0x4190, 0); 786 hws[IMX8MP_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", ccm_base + 0x41a0, 0); 787 hws[IMX8MP_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk", "ipg_root", ccm_base + 0x4210, 0); 788 hws[IMX8MP_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", ccm_base + 0x4220, 0); 789 hws[IMX8MP_CLK_PCIE_ROOT] = imx_clk_hw_gate4("pcie_root_clk", "pcie_aux", ccm_base + 0x4250, 0); 790 hws[IMX8MP_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", ccm_base + 0x4280, 0); 791 hws[IMX8MP_CLK_PWM2_ROOT] = imx_clk_hw_gate4("pwm2_root_clk", "pwm2", ccm_base + 0x4290, 0); 792 hws[IMX8MP_CLK_PWM3_ROOT] = imx_clk_hw_gate4("pwm3_root_clk", "pwm3", ccm_base + 0x42a0, 0); 793 hws[IMX8MP_CLK_PWM4_ROOT] = imx_clk_hw_gate4("pwm4_root_clk", "pwm4", ccm_base + 0x42b0, 0); 794 hws[IMX8MP_CLK_QOS_ROOT] = imx_clk_hw_gate4("qos_root_clk", "ipg_root", ccm_base + 0x42c0, 0); 795 hws[IMX8MP_CLK_QOS_ENET_ROOT] = imx_clk_hw_gate4("qos_enet_root_clk", "ipg_root", ccm_base + 0x42e0, 0); 796 hws[IMX8MP_CLK_QSPI_ROOT] = imx_clk_hw_gate4("qspi_root_clk", "qspi", ccm_base + 0x42f0, 0); 797 hws[IMX8MP_CLK_NAND_ROOT] = imx_clk_hw_gate2_shared2("nand_root_clk", "nand", ccm_base + 0x4300, 0, &share_count_nand); 798 hws[IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", ccm_base + 0x4300, 0, &share_count_nand); 799 hws[IMX8MP_CLK_I2C5_ROOT] = imx_clk_hw_gate2("i2c5_root_clk", "i2c5", ccm_base + 0x4330, 0); 800 hws[IMX8MP_CLK_I2C6_ROOT] = imx_clk_hw_gate2("i2c6_root_clk", "i2c6", ccm_base + 0x4340, 0); 801 hws[IMX8MP_CLK_CAN1_ROOT] = imx_clk_hw_gate2("can1_root_clk", "can1", ccm_base + 0x4350, 0); 802 hws[IMX8MP_CLK_CAN2_ROOT] = imx_clk_hw_gate2("can2_root_clk", "can2", ccm_base + 0x4360, 0); 803 hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk", "ipg_root", ccm_base + 0x43a0, 0); 804 hws[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0); 805 hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base + 0x43b0, 0); 806 hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_core", ccm_base + 0x4450, 0); 807 hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core", ccm_base + 0x4460, 0); 808 hws[IMX8MP_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", ccm_base + 0x4490, 0); 809 hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0); 810 hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", ccm_base + 0x44b0, 0); 811 hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", ccm_base + 0x44c0, 0); 812 hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate2_shared2("usb_root_clk", "hsio_axi", ccm_base + 0x44d0, 0, &share_count_usb); 813 hws[IMX8MP_CLK_USB_SUSP] = imx_clk_hw_gate2_shared2("usb_suspend_clk", "osc_32k", ccm_base + 0x44d0, 0, &share_count_usb); 814 hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk", "usb_phy_ref", ccm_base + 0x44f0, 0); 815 hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", ccm_base + 0x4510, 0); 816 hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", ccm_base + 0x4520, 0); 817 hws[IMX8MP_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk", "wdog", ccm_base + 0x4530, 0); 818 hws[IMX8MP_CLK_WDOG2_ROOT] = imx_clk_hw_gate4("wdog2_root_clk", "wdog", ccm_base + 0x4540, 0); 819 hws[IMX8MP_CLK_WDOG3_ROOT] = imx_clk_hw_gate4("wdog3_root_clk", "wdog", ccm_base + 0x4550, 0); 820 hws[IMX8MP_CLK_VPU_G1_ROOT] = imx_clk_hw_gate4("vpu_g1_root_clk", "vpu_g1", ccm_base + 0x4560, 0); 821 hws[IMX8MP_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", ccm_base + 0x4570, 0); 822 hws[IMX8MP_CLK_VPU_VC8KE_ROOT] = imx_clk_hw_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", ccm_base + 0x4590, 0); 823 hws[IMX8MP_CLK_VPU_G2_ROOT] = imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", ccm_base + 0x45a0, 0); 824 hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk", "ml_core", ccm_base + 0x45b0, 0); 825 hws[IMX8MP_CLK_HSIO_ROOT] = imx_clk_hw_gate4("hsio_root_clk", "ipg_root", ccm_base + 0x45c0, 0); 826 hws[IMX8MP_CLK_MEDIA_APB_ROOT] = imx_clk_hw_gate2_shared2("media_apb_root_clk", "media_apb", ccm_base + 0x45d0, 0, &share_count_media); 827 hws[IMX8MP_CLK_MEDIA_AXI_ROOT] = imx_clk_hw_gate2_shared2("media_axi_root_clk", "media_axi", ccm_base + 0x45d0, 0, &share_count_media); 828 hws[IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_cam1_pix_root_clk", "media_cam1_pix", ccm_base + 0x45d0, 0, &share_count_media); 829 hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix", ccm_base + 0x45d0, 0, &share_count_media); 830 hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_media); 831 hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_media); 832 hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT] = imx_clk_hw_gate2_shared2("media_mipi_phy1_ref_root", "media_mipi_phy1_ref", ccm_base + 0x45d0, 0, &share_count_media); 833 hws[IMX8MP_CLK_MEDIA_LDB_ROOT] = imx_clk_hw_gate2_shared2("media_ldb_root_clk", "media_ldb", ccm_base + 0x45d0, 0, &share_count_media); 834 hws[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", ccm_base + 0x45d0, 0, &share_count_media); 835 836 hws[IMX8MP_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0); 837 hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0); 838 hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0); 839 hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0); 840 841 hws[IMX8MP_CLK_AUDIO_AHB_ROOT] = imx_clk_hw_gate2_shared2("audio_ahb_root", "audio_ahb", ccm_base + 0x4650, 0, &share_count_audio); 842 hws[IMX8MP_CLK_AUDIO_AXI_ROOT] = imx_clk_hw_gate2_shared2("audio_axi_root", "audio_axi", ccm_base + 0x4650, 0, &share_count_audio); 843 hws[IMX8MP_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root", "sai1", ccm_base + 0x4650, 0, &share_count_audio); 844 hws[IMX8MP_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root", "sai2", ccm_base + 0x4650, 0, &share_count_audio); 845 hws[IMX8MP_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root", "sai3", ccm_base + 0x4650, 0, &share_count_audio); 846 hws[IMX8MP_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root", "sai5", ccm_base + 0x4650, 0, &share_count_audio); 847 hws[IMX8MP_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root", "sai6", ccm_base + 0x4650, 0, &share_count_audio); 848 hws[IMX8MP_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root", "sai7", ccm_base + 0x4650, 0, &share_count_audio); 849 hws[IMX8MP_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root", "pdm", ccm_base + 0x4650, 0, &share_count_audio); 850 851 hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core", 852 hws[IMX8MP_CLK_A53_CORE]->clk, 853 hws[IMX8MP_CLK_A53_CORE]->clk, 854 hws[IMX8MP_ARM_PLL_OUT]->clk, 855 hws[IMX8MP_CLK_A53_DIV]->clk); 856 857 imx_check_clk_hws(hws, IMX8MP_CLK_END); 858 859 imx8mp_clocks_apply_constraints(imx8mp_clock_common_constraints); 860 861 err = of_property_read_string(np, "fsl,operating-mode", &opmode); 862 if (!err) { 863 if (!strcmp(opmode, "nominal")) 864 imx8mp_clocks_apply_constraints(imx8mp_clock_nominal_constraints); 865 else if (!strcmp(opmode, "overdrive")) 866 imx8mp_clocks_apply_constraints(imx8mp_clock_overdrive_constraints); 867 } 868 869 err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); 870 if (err < 0) { 871 dev_err(dev, "failed to register hws for i.MX8MP\n"); 872 imx_unregister_hw_clocks(hws, IMX8MP_CLK_END); 873 return err; 874 } 875 876 imx_register_uart_clocks(); 877 878 return 0; 879} 880 881static const struct of_device_id imx8mp_clk_of_match[] = { 882 { .compatible = "fsl,imx8mp-ccm" }, 883 { /* Sentinel */ } 884}; 885MODULE_DEVICE_TABLE(of, imx8mp_clk_of_match); 886 887static struct platform_driver imx8mp_clk_driver = { 888 .probe = imx8mp_clocks_probe, 889 .driver = { 890 .name = "imx8mp-ccm", 891 /* 892 * Disable bind attributes: clocks are not removed and 893 * reloading the driver will crash or break devices. 894 */ 895 .suppress_bind_attrs = true, 896 .of_match_table = imx8mp_clk_of_match, 897 }, 898}; 899module_platform_driver(imx8mp_clk_driver); 900module_param(mcore_booted, bool, S_IRUGO); 901MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not"); 902 903MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>"); 904MODULE_DESCRIPTION("NXP i.MX8MP clock driver"); 905MODULE_LICENSE("GPL v2");
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