clk-imx8mp-audiomix.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Driver for i.MX8M Plus Audio BLK_CTRL
  4 *
  5 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
  6 */
  7
  8#include <linux/auxiliary_bus.h>
  9#include <linux/clk-provider.h>
 10#include <linux/device.h>
 11#include <linux/io.h>
 12#include <linux/mod_devicetable.h>
 13#include <linux/module.h>
 14#include <linux/of.h>
 15#include <linux/platform_device.h>
 16#include <linux/pm_runtime.h>
 17#include <linux/slab.h>
 18
 19#include <dt-bindings/clock/imx8mp-clock.h>
 20
 21#include "clk.h"
 22
 23#define CLKEN0			0x000
 24#define CLKEN1			0x004
 25#define EARC			0x200
 26#define SAI1_MCLK_SEL		0x300
 27#define SAI2_MCLK_SEL		0x304
 28#define SAI3_MCLK_SEL		0x308
 29#define SAI5_MCLK_SEL		0x30C
 30#define SAI6_MCLK_SEL		0x310
 31#define SAI7_MCLK_SEL		0x314
 32#define PDM_SEL			0x318
 33#define SAI_PLL_GNRL_CTL	0x400
 34#define SAI_PLL_FDIVL_CTL0	0x404
 35#define SAI_PLL_FDIVL_CTL1	0x408
 36#define SAI_PLL_SSCG_CTL	0x40C
 37#define SAI_PLL_MNIT_CTL	0x410
 38#define IPG_LP_CTRL		0x504
 39
 40#define SAIn_MCLK1_PARENT(n)						\
 41static const struct clk_parent_data					\
 42clk_imx8mp_audiomix_sai##n##_mclk1_parents[] = {			\
 43	{								\
 44		.fw_name = "sai"__stringify(n),				\
 45		.name = "sai"__stringify(n)				\
 46	}, {								\
 47		.fw_name = "sai"__stringify(n)"_mclk",			\
 48		.name = "sai"__stringify(n)"_mclk"			\
 49	},								\
 50}
 51
 52SAIn_MCLK1_PARENT(1);
 53SAIn_MCLK1_PARENT(2);
 54SAIn_MCLK1_PARENT(3);
 55SAIn_MCLK1_PARENT(5);
 56SAIn_MCLK1_PARENT(6);
 57SAIn_MCLK1_PARENT(7);
 58
 59static const struct clk_parent_data clk_imx8mp_audiomix_sai_mclk2_parents[] = {
 60	{ .fw_name = "sai1", .name = "sai1" },
 61	{ .fw_name = "sai2", .name = "sai2" },
 62	{ .fw_name = "sai3", .name = "sai3" },
 63	{ .name = "dummy" },
 64	{ .fw_name = "sai5", .name = "sai5" },
 65	{ .fw_name = "sai6", .name = "sai6" },
 66	{ .fw_name = "sai7", .name = "sai7" },
 67	{ .fw_name = "sai1_mclk", .name = "sai1_mclk" },
 68	{ .fw_name = "sai2_mclk", .name = "sai2_mclk" },
 69	{ .fw_name = "sai3_mclk", .name = "sai3_mclk" },
 70	{ .name = "dummy" },
 71	{ .fw_name = "sai5_mclk", .name = "sai5_mclk" },
 72	{ .fw_name = "sai6_mclk", .name = "sai6_mclk" },
 73	{ .fw_name = "sai7_mclk", .name = "sai7_mclk" },
 74	{ .fw_name = "spdif_extclk", .name = "spdif_extclk" },
 75	{ .name = "dummy" },
 76};
 77
 78static const struct clk_parent_data clk_imx8mp_audiomix_pdm_parents[] = {
 79	{ .fw_name = "pdm", .name = "pdm" },
 80	{ .name = "sai_pll_out_div2" },
 81	{ .fw_name = "sai1_mclk", .name = "sai1_mclk" },
 82	{ .name = "dummy" },
 83};
 84
 85
 86static const struct clk_parent_data clk_imx8mp_audiomix_pll_parents[] = {
 87	{ .fw_name = "osc_24m", .name = "osc_24m" },
 88	{ .name = "dummy" },
 89	{ .name = "dummy" },
 90	{ .name = "dummy" },
 91};
 92
 93static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[] = {
 94	{ .fw_name = "sai_pll", .name = "sai_pll" },
 95	{ .fw_name = "sai_pll_ref_sel", .name = "sai_pll_ref_sel" },
 96};
 97
 98#define CLK_GATE(gname, cname)						\
 99	{								\
100		gname"_cg",						\
101		IMX8MP_CLK_AUDIOMIX_##cname,				\
102		{ .fw_name = "ahb", .name = "ahb" }, NULL, 1,		\
103		CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32),	\
104		1, IMX8MP_CLK_AUDIOMIX_##cname % 32			\
105	}
106
107#define CLK_SAIn(n)							\
108	{								\
109		"sai"__stringify(n)"_mclk1_sel",			\
110		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1_SEL, {},		\
111		clk_imx8mp_audiomix_sai##n##_mclk1_parents,		\
112		ARRAY_SIZE(clk_imx8mp_audiomix_sai##n##_mclk1_parents), \
113		SAI##n##_MCLK_SEL, 1, 0					\
114	}, {								\
115		"sai"__stringify(n)"_mclk2_sel",			\
116		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2_SEL, {},		\
117		clk_imx8mp_audiomix_sai_mclk2_parents,			\
118		ARRAY_SIZE(clk_imx8mp_audiomix_sai_mclk2_parents),	\
119		SAI##n##_MCLK_SEL, 4, 1					\
120	}, {								\
121		"sai"__stringify(n)"_ipg_cg",				\
122		IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG,			\
123		{ .fw_name = "ahb", .name = "ahb" }, NULL, 1,		\
124		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG		\
125	}, {								\
126		"sai"__stringify(n)"_mclk1_cg",				\
127		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1,			\
128		{							\
129			.fw_name = "sai"__stringify(n)"_mclk1_sel",	\
130			.name = "sai"__stringify(n)"_mclk1_sel"		\
131		}, NULL, 1,						\
132		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1		\
133	}, {								\
134		"sai"__stringify(n)"_mclk2_cg",				\
135		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2,			\
136		{							\
137			.fw_name = "sai"__stringify(n)"_mclk2_sel",	\
138			.name = "sai"__stringify(n)"_mclk2_sel"		\
139		}, NULL, 1,						\
140		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2		\
141	}, {								\
142		"sai"__stringify(n)"_mclk3_cg",				\
143		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3,			\
144		{							\
145			.fw_name = "sai_pll_out_div2",			\
146			.name = "sai_pll_out_div2"			\
147		}, NULL, 1,						\
148		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3		\
149	}
150
151#define CLK_PDM								\
152	{								\
153		"pdm_sel", IMX8MP_CLK_AUDIOMIX_PDM_SEL, {},		\
154		clk_imx8mp_audiomix_pdm_parents,			\
155		ARRAY_SIZE(clk_imx8mp_audiomix_pdm_parents),		\
156		PDM_SEL, 2, 0						\
157	}
158
159#define CLK_GATE_PARENT(gname, cname, pname)						\
160	{								\
161		gname"_cg",						\
162		IMX8MP_CLK_AUDIOMIX_##cname,				\
163		{ .fw_name = pname, .name = pname }, NULL, 1,		\
164		CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32),	\
165		1, IMX8MP_CLK_AUDIOMIX_##cname % 32			\
166	}
167
168struct clk_imx8mp_audiomix_sel {
169	const char			*name;
170	int				clkid;
171	const struct clk_parent_data	parent;		/* For gate */
172	const struct clk_parent_data	*parents;	/* For mux */
173	int				num_parents;
174	u16				reg;
175	u8				width;
176	u8				shift;
177};
178
179static struct clk_imx8mp_audiomix_sel sels[] = {
180	CLK_GATE("asrc", ASRC_IPG),
181	CLK_GATE("pdm", PDM_IPG),
182	CLK_GATE("earc", EARC_IPG),
183	CLK_GATE_PARENT("ocrama", OCRAMA_IPG, "axi"),
184	CLK_GATE("aud2htx", AUD2HTX_IPG),
185	CLK_GATE_PARENT("earc_phy", EARC_PHY, "sai_pll_out_div2"),
186	CLK_GATE("sdma2", SDMA2_ROOT),
187	CLK_GATE("sdma3", SDMA3_ROOT),
188	CLK_GATE("spba2", SPBA2_ROOT),
189	CLK_GATE_PARENT("dsp", DSP_ROOT, "axi"),
190	CLK_GATE_PARENT("dspdbg", DSPDBG_ROOT, "axi"),
191	CLK_GATE("edma", EDMA_ROOT),
192	CLK_GATE_PARENT("audpll", AUDPLL_ROOT, "osc_24m"),
193	CLK_GATE("mu2", MU2_ROOT),
194	CLK_GATE("mu3", MU3_ROOT),
195	CLK_PDM,
196	CLK_SAIn(1),
197	CLK_SAIn(2),
198	CLK_SAIn(3),
199	CLK_SAIn(5),
200	CLK_SAIn(6),
201	CLK_SAIn(7)
202};
203
204static const u16 audiomix_regs[] = {
205	CLKEN0,
206	CLKEN1,
207	EARC,
208	SAI1_MCLK_SEL,
209	SAI2_MCLK_SEL,
210	SAI3_MCLK_SEL,
211	SAI5_MCLK_SEL,
212	SAI6_MCLK_SEL,
213	SAI7_MCLK_SEL,
214	PDM_SEL,
215	SAI_PLL_GNRL_CTL,
216	SAI_PLL_FDIVL_CTL0,
217	SAI_PLL_FDIVL_CTL1,
218	SAI_PLL_SSCG_CTL,
219	SAI_PLL_MNIT_CTL,
220	IPG_LP_CTRL,
221};
222
223struct clk_imx8mp_audiomix_priv {
224	void __iomem *base;
225	u32 regs_save[ARRAY_SIZE(audiomix_regs)];
226
227	/* Must be last */
228	struct clk_hw_onecell_data clk_data;
229};
230
231#if IS_ENABLED(CONFIG_RESET_CONTROLLER)
232
233static int clk_imx8mp_audiomix_reset_controller_register(struct device *dev,
234							 struct clk_imx8mp_audiomix_priv *priv)
235{
236	struct auxiliary_device *adev;
237
238	if (!of_property_present(dev->of_node, "#reset-cells"))
239		return 0;
240
241	adev = devm_auxiliary_device_create(dev, "reset", NULL);
242	if (!adev)
243		return -ENODEV;
244
245	return 0;
246}
247
248#else /* !CONFIG_RESET_CONTROLLER */
249
250static int clk_imx8mp_audiomix_reset_controller_register(struct device *dev,
251							 struct clk_imx8mp_audiomix_priv *priv)
252{
253	return 0;
254}
255
256#endif /* !CONFIG_RESET_CONTROLLER */
257
258static void clk_imx8mp_audiomix_save_restore(struct device *dev, bool save)
259{
260	struct clk_imx8mp_audiomix_priv *priv = dev_get_drvdata(dev);
261	void __iomem *base = priv->base;
262	int i;
263
264	if (save) {
265		for (i = 0; i < ARRAY_SIZE(audiomix_regs); i++)
266			priv->regs_save[i] = readl(base + audiomix_regs[i]);
267	} else {
268		for (i = 0; i < ARRAY_SIZE(audiomix_regs); i++)
269			writel(priv->regs_save[i], base + audiomix_regs[i]);
270	}
271}
272
273static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
274{
275	struct clk_imx8mp_audiomix_priv *priv;
276	struct clk_hw_onecell_data *clk_hw_data;
277	struct device *dev = &pdev->dev;
278	void __iomem *base;
279	struct clk_hw *hw;
280	int i, ret;
281
282	priv = devm_kzalloc(dev,
283			    struct_size(priv, clk_data.hws, IMX8MP_CLK_AUDIOMIX_END),
284			    GFP_KERNEL);
285	if (!priv)
286		return -ENOMEM;
287
288	clk_hw_data = &priv->clk_data;
289	clk_hw_data->num = IMX8MP_CLK_AUDIOMIX_END;
290
291	base = devm_platform_ioremap_resource(pdev, 0);
292	if (IS_ERR(base))
293		return PTR_ERR(base);
294
295	priv->base = base;
296	dev_set_drvdata(dev, priv);
297
298	/*
299	 * pm_runtime_enable needs to be called before clk register.
300	 * That is to make core->rpm_enabled to be true for clock
301	 * usage.
302	 */
303	pm_runtime_get_noresume(dev);
304	pm_runtime_set_active(dev);
305	pm_runtime_enable(dev);
306
307	for (i = 0; i < ARRAY_SIZE(sels); i++) {
308		if (sels[i].num_parents == 1) {
309			hw = devm_clk_hw_register_gate_parent_data(dev,
310				sels[i].name, &sels[i].parent, CLK_SET_RATE_PARENT,
311				base + sels[i].reg, sels[i].shift, 0, NULL);
312		} else {
313			hw = devm_clk_hw_register_mux_parent_data_table(dev,
314				sels[i].name, sels[i].parents,
315				sels[i].num_parents, CLK_SET_RATE_PARENT,
316				base + sels[i].reg,
317				sels[i].shift, sels[i].width,
318				0, NULL, NULL);
319		}
320
321		if (IS_ERR(hw)) {
322			ret = PTR_ERR(hw);
323			goto err_clk_register;
324		}
325
326		clk_hw_data->hws[sels[i].clkid] = hw;
327	}
328
329	/* SAI PLL */
330	hw = devm_clk_hw_register_mux_parent_data_table(dev,
331		"sai_pll_ref_sel", clk_imx8mp_audiomix_pll_parents,
332		ARRAY_SIZE(clk_imx8mp_audiomix_pll_parents),
333		CLK_SET_RATE_NO_REPARENT, base + SAI_PLL_GNRL_CTL,
334		0, 2, 0, NULL, NULL);
335	clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = hw;
336
337	hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel",
338				    base + 0x400, &imx_1443x_pll);
339	if (IS_ERR(hw)) {
340		ret = PTR_ERR(hw);
341		goto err_clk_register;
342	}
343	clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw;
344
345	hw = devm_clk_hw_register_mux_parent_data_table(dev,
346		"sai_pll_bypass", clk_imx8mp_audiomix_pll_bypass_sels,
347		ARRAY_SIZE(clk_imx8mp_audiomix_pll_bypass_sels),
348		CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
349		base + SAI_PLL_GNRL_CTL, 16, 1, 0, NULL, NULL);
350	if (IS_ERR(hw)) {
351		ret = PTR_ERR(hw);
352		goto err_clk_register;
353	}
354
355	clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
356
357	hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass",
358				       CLK_SET_RATE_PARENT,
359				       base + SAI_PLL_GNRL_CTL, 13,
360				       0, NULL);
361	if (IS_ERR(hw)) {
362		ret = PTR_ERR(hw);
363		goto err_clk_register;
364	}
365	clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
366
367	hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2",
368					       "sai_pll_out",
369					       CLK_SET_RATE_PARENT, 1, 2);
370	if (IS_ERR(hw)) {
371		ret = PTR_ERR(hw);
372		goto err_clk_register;
373	}
374
375	ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
376					  clk_hw_data);
377	if (ret)
378		goto err_clk_register;
379
380	ret = clk_imx8mp_audiomix_reset_controller_register(dev, priv);
381	if (ret)
382		goto err_clk_register;
383
384	pm_runtime_put_sync(dev);
385	return 0;
386
387err_clk_register:
388	pm_runtime_put_sync(dev);
389	pm_runtime_disable(dev);
390	return ret;
391}
392
393static void clk_imx8mp_audiomix_remove(struct platform_device *pdev)
394{
395	pm_runtime_disable(&pdev->dev);
396}
397
398static int clk_imx8mp_audiomix_runtime_suspend(struct device *dev)
399{
400	clk_imx8mp_audiomix_save_restore(dev, true);
401
402	return 0;
403}
404
405static int clk_imx8mp_audiomix_runtime_resume(struct device *dev)
406{
407	clk_imx8mp_audiomix_save_restore(dev, false);
408
409	return 0;
410}
411
412static const struct dev_pm_ops clk_imx8mp_audiomix_pm_ops = {
413	RUNTIME_PM_OPS(clk_imx8mp_audiomix_runtime_suspend,
414		       clk_imx8mp_audiomix_runtime_resume, NULL)
415	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
416				      pm_runtime_force_resume)
417};
418
419static const struct of_device_id clk_imx8mp_audiomix_of_match[] = {
420	{ .compatible = "fsl,imx8mp-audio-blk-ctrl" },
421	{ /* sentinel */ }
422};
423MODULE_DEVICE_TABLE(of, clk_imx8mp_audiomix_of_match);
424
425static struct platform_driver clk_imx8mp_audiomix_driver = {
426	.probe	= clk_imx8mp_audiomix_probe,
427	.remove = clk_imx8mp_audiomix_remove,
428	.driver = {
429		.name = "imx8mp-audio-blk-ctrl",
430		.of_match_table = clk_imx8mp_audiomix_of_match,
431		.pm = pm_ptr(&clk_imx8mp_audiomix_pm_ops),
432	},
433};
434
435module_platform_driver(clk_imx8mp_audiomix_driver);
436
437MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
438MODULE_DESCRIPTION("Freescale i.MX8MP Audio Block Controller driver");
439MODULE_LICENSE("GPL");