clk-fracn-gppll.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright 2021 NXP
  4 */
  5
  6#include <linux/bitfield.h>
  7#include <linux/clk-provider.h>
  8#include <linux/err.h>
  9#include <linux/export.h>
 10#include <linux/io.h>
 11#include <linux/iopoll.h>
 12#include <linux/slab.h>
 13#include <asm/div64.h>
 14
 15#include "clk.h"
 16
 17#define PLL_CTRL		0x0
 18#define HW_CTRL_SEL		BIT(16)
 19#define CLKMUX_BYPASS		BIT(2)
 20#define CLKMUX_EN		BIT(1)
 21#define POWERUP_MASK		BIT(0)
 22
 23#define PLL_ANA_PRG		0x10
 24#define PLL_SPREAD_SPECTRUM	0x30
 25
 26#define PLL_NUMERATOR		0x40
 27#define PLL_MFN_MASK		GENMASK(31, 2)
 28
 29#define PLL_DENOMINATOR		0x50
 30#define PLL_MFD_MASK		GENMASK(29, 0)
 31
 32#define PLL_DIV			0x60
 33#define PLL_MFI_MASK		GENMASK(24, 16)
 34#define PLL_RDIV_MASK		GENMASK(15, 13)
 35#define PLL_ODIV_MASK		GENMASK(7, 0)
 36
 37#define PLL_DFS_CTRL(x)		(0x70 + (x) * 0x10)
 38
 39#define PLL_STATUS		0xF0
 40#define LOCK_STATUS		BIT(0)
 41
 42#define DFS_STATUS		0xF4
 43
 44#define LOCK_TIMEOUT_US		200
 45
 46#define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv)	\
 47	{							\
 48		.rate	=	(_rate),			\
 49		.mfi	=	(_mfi),				\
 50		.mfn	=	(_mfn),				\
 51		.mfd	=	(_mfd),				\
 52		.rdiv	=	(_rdiv),			\
 53		.odiv	=	(_odiv),			\
 54	}
 55
 56#define PLL_FRACN_GP_INTEGER(_rate, _mfi, _rdiv, _odiv)		\
 57	{							\
 58		.rate	=	(_rate),			\
 59		.mfi	=	(_mfi),				\
 60		.mfn	=	0,				\
 61		.mfd	=	0,				\
 62		.rdiv	=	(_rdiv),			\
 63		.odiv	=	(_odiv),			\
 64	}
 65
 66struct clk_fracn_gppll {
 67	struct clk_hw			hw;
 68	void __iomem			*base;
 69	const struct imx_fracn_gppll_rate_table *rate_table;
 70	int rate_count;
 71	u32 flags;
 72};
 73
 74/*
 75 * Fvco = (Fref / rdiv) * (MFI + MFN / MFD)
 76 * Fout = Fvco / odiv
 77 * The (Fref / rdiv) should be in range 20MHz to 40MHz
 78 * The Fvco should be in range 2.5Ghz to 5Ghz
 79 */
 80static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
 81	PLL_FRACN_GP(1039500000U, 173, 25, 100, 1, 4),
 82	PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
 83	PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
 84	PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
 85	PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
 86	PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
 87	PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
 88	PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
 89	PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
 90	PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
 91	PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
 92};
 93
 94struct imx_fracn_gppll_clk imx_fracn_gppll = {
 95	.rate_table = fracn_tbl,
 96	.rate_count = ARRAY_SIZE(fracn_tbl),
 97};
 98EXPORT_SYMBOL_GPL(imx_fracn_gppll);
 99
100/*
101 * Fvco = (Fref / rdiv) * MFI
102 * Fout = Fvco / odiv
103 * The (Fref / rdiv) should be in range 20MHz to 40MHz
104 * The Fvco should be in range 2.5Ghz to 5Ghz
105 */
106static const struct imx_fracn_gppll_rate_table int_tbl[] = {
107	PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2),
108	PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3),
109	PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4),
110	PLL_FRACN_GP_INTEGER(800000000U, 200, 1, 6),
111};
112
113struct imx_fracn_gppll_clk imx_fracn_gppll_integer = {
114	.rate_table = int_tbl,
115	.rate_count = ARRAY_SIZE(int_tbl),
116};
117EXPORT_SYMBOL_GPL(imx_fracn_gppll_integer);
118
119static inline struct clk_fracn_gppll *to_clk_fracn_gppll(struct clk_hw *hw)
120{
121	return container_of(hw, struct clk_fracn_gppll, hw);
122}
123
124static const struct imx_fracn_gppll_rate_table *
125imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate)
126{
127	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
128	int i;
129
130	for (i = 0; i < pll->rate_count; i++)
131		if (rate == rate_table[i].rate)
132			return &rate_table[i];
133
134	return NULL;
135}
136
137static int clk_fracn_gppll_determine_rate(struct clk_hw *hw,
138					  struct clk_rate_request *req)
139{
140	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
141	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
142	int i;
143
144	/* Assuming rate_table is in descending order */
145	for (i = 0; i < pll->rate_count; i++)
146		if (req->rate >= rate_table[i].rate) {
147			req->rate = rate_table[i].rate;
148
149			return 0;
150		}
151
152	/* return minimum supported value */
153	req->rate = rate_table[pll->rate_count - 1].rate;
154
155	return 0;
156}
157
158static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
159{
160	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
161	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
162	u32 pll_numerator, pll_denominator, pll_div;
163	u32 mfi, mfn, mfd, rdiv, odiv;
164	u64 fvco = parent_rate;
165	long rate = 0;
166	int i;
167
168	pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR);
169	mfn = FIELD_GET(PLL_MFN_MASK, pll_numerator);
170
171	pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR);
172	mfd = FIELD_GET(PLL_MFD_MASK, pll_denominator);
173
174	pll_div = readl_relaxed(pll->base + PLL_DIV);
175	mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
176
177	rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
178	odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
179
180	/*
181	 * Sometimes, the recalculated rate has deviation due to
182	 * the frac part. So find the accurate pll rate from the table
183	 * first, if no match rate in the table, use the rate calculated
184	 * from the equation below.
185	 */
186	for (i = 0; i < pll->rate_count; i++) {
187		if (rate_table[i].mfn == mfn && rate_table[i].mfi == mfi &&
188		    rate_table[i].mfd == mfd && rate_table[i].rdiv == rdiv &&
189		    rate_table[i].odiv == odiv)
190			rate = rate_table[i].rate;
191	}
192
193	if (rate)
194		return (unsigned long)rate;
195
196	if (!rdiv)
197		rdiv = rdiv + 1;
198
199	switch (odiv) {
200	case 0:
201		odiv = 2;
202		break;
203	case 1:
204		odiv = 3;
205		break;
206	default:
207		break;
208	}
209
210	if (pll->flags & CLK_FRACN_GPPLL_INTEGER) {
211		/* Fvco = (Fref / rdiv) * MFI */
212		fvco = fvco * mfi;
213		do_div(fvco, rdiv * odiv);
214	} else {
215		/* Fvco = (Fref / rdiv) * (MFI + MFN / MFD) */
216		fvco = fvco * mfi * mfd + fvco * mfn;
217		do_div(fvco, mfd * rdiv * odiv);
218	}
219
220	return (unsigned long)fvco;
221}
222
223static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll)
224{
225	u32 val;
226
227	return readl_poll_timeout(pll->base + PLL_STATUS, val,
228				  val & LOCK_STATUS, 0, LOCK_TIMEOUT_US);
229}
230
231static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate,
232				    unsigned long prate)
233{
234	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
235	const struct imx_fracn_gppll_rate_table *rate;
236	u32 tmp, pll_div, ana_mfn;
237	int ret;
238
239	rate = imx_get_pll_settings(pll, drate);
240
241	/* Hardware control select disable. PLL is control by register */
242	tmp = readl_relaxed(pll->base + PLL_CTRL);
243	tmp &= ~HW_CTRL_SEL;
244	writel_relaxed(tmp, pll->base + PLL_CTRL);
245
246	/* Disable output */
247	tmp = readl_relaxed(pll->base + PLL_CTRL);
248	tmp &= ~CLKMUX_EN;
249	writel_relaxed(tmp, pll->base + PLL_CTRL);
250
251	/* Power Down */
252	tmp &= ~POWERUP_MASK;
253	writel_relaxed(tmp, pll->base + PLL_CTRL);
254
255	/* Disable BYPASS */
256	tmp &= ~CLKMUX_BYPASS;
257	writel_relaxed(tmp, pll->base + PLL_CTRL);
258
259	pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv |
260		FIELD_PREP(PLL_MFI_MASK, rate->mfi);
261	writel_relaxed(pll_div, pll->base + PLL_DIV);
262	readl(pll->base + PLL_DIV);
263	if (pll->flags & CLK_FRACN_GPPLL_FRACN) {
264		writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);
265		writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);
266		readl(pll->base + PLL_NUMERATOR);
267	}
268
269	/* Wait for 5us according to fracn mode pll doc */
270	udelay(5);
271
272	/* Enable Powerup */
273	tmp |= POWERUP_MASK;
274	writel_relaxed(tmp, pll->base + PLL_CTRL);
275	readl(pll->base + PLL_CTRL);
276
277	/* Wait Lock */
278	ret = clk_fracn_gppll_wait_lock(pll);
279	if (ret)
280		return ret;
281
282	/* Enable output */
283	tmp |= CLKMUX_EN;
284	writel_relaxed(tmp, pll->base + PLL_CTRL);
285
286	ana_mfn = readl_relaxed(pll->base + PLL_STATUS);
287	ana_mfn = FIELD_GET(PLL_MFN_MASK, ana_mfn);
288
289	WARN(ana_mfn != rate->mfn, "ana_mfn != rate->mfn\n");
290
291	return 0;
292}
293
294static int clk_fracn_gppll_prepare(struct clk_hw *hw)
295{
296	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
297	u32 val;
298	int ret;
299
300	val = readl_relaxed(pll->base + PLL_CTRL);
301	if (val & POWERUP_MASK)
302		return 0;
303
304	if (pll->flags & CLK_FRACN_GPPLL_FRACN)
305		writel_relaxed(readl_relaxed(pll->base + PLL_NUMERATOR),
306			       pll->base + PLL_NUMERATOR);
307
308	val |= CLKMUX_BYPASS;
309	writel_relaxed(val, pll->base + PLL_CTRL);
310
311	val |= POWERUP_MASK;
312	writel_relaxed(val, pll->base + PLL_CTRL);
313	readl(pll->base + PLL_CTRL);
314
315	ret = clk_fracn_gppll_wait_lock(pll);
316	if (ret)
317		return ret;
318
319	val |= CLKMUX_EN;
320	writel_relaxed(val, pll->base + PLL_CTRL);
321
322	val &= ~CLKMUX_BYPASS;
323	writel_relaxed(val, pll->base + PLL_CTRL);
324
325	return 0;
326}
327
328static int clk_fracn_gppll_is_prepared(struct clk_hw *hw)
329{
330	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
331	u32 val;
332
333	val = readl_relaxed(pll->base + PLL_CTRL);
334
335	return (val & POWERUP_MASK) ? 1 : 0;
336}
337
338static void clk_fracn_gppll_unprepare(struct clk_hw *hw)
339{
340	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
341	u32 val;
342
343	val = readl_relaxed(pll->base + PLL_CTRL);
344	val &= ~POWERUP_MASK;
345	writel_relaxed(val, pll->base + PLL_CTRL);
346}
347
348static const struct clk_ops clk_fracn_gppll_ops = {
349	.prepare	= clk_fracn_gppll_prepare,
350	.unprepare	= clk_fracn_gppll_unprepare,
351	.is_prepared	= clk_fracn_gppll_is_prepared,
352	.recalc_rate	= clk_fracn_gppll_recalc_rate,
353	.determine_rate = clk_fracn_gppll_determine_rate,
354	.set_rate	= clk_fracn_gppll_set_rate,
355};
356
357static struct clk_hw *_imx_clk_fracn_gppll(const char *name, const char *parent_name,
358					   void __iomem *base,
359					   const struct imx_fracn_gppll_clk *pll_clk,
360					   u32 pll_flags)
361{
362	struct clk_fracn_gppll *pll;
363	struct clk_hw *hw;
364	struct clk_init_data init;
365	int ret;
366
367	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
368	if (!pll)
369		return ERR_PTR(-ENOMEM);
370
371	init.name = name;
372	init.flags = pll_clk->flags;
373	init.parent_names = &parent_name;
374	init.num_parents = 1;
375	init.ops = &clk_fracn_gppll_ops;
376
377	pll->base = base;
378	pll->hw.init = &init;
379	pll->rate_table = pll_clk->rate_table;
380	pll->rate_count = pll_clk->rate_count;
381	pll->flags = pll_flags;
382
383	hw = &pll->hw;
384
385	ret = clk_hw_register(NULL, hw);
386	if (ret) {
387		pr_err("%s: failed to register pll %s %d\n", __func__, name, ret);
388		kfree(pll);
389		return ERR_PTR(ret);
390	}
391
392	return hw;
393}
394
395struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
396				   const struct imx_fracn_gppll_clk *pll_clk)
397{
398	return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_FRACN);
399}
400EXPORT_SYMBOL_GPL(imx_clk_fracn_gppll);
401
402struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name,
403					   void __iomem *base,
404					   const struct imx_fracn_gppll_clk *pll_clk)
405{
406	return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_INTEGER);
407}
408EXPORT_SYMBOL_GPL(imx_clk_fracn_gppll_integer);