clk-frac-pll.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright 2018 NXP.
  4 *
  5 * This driver supports the fractional plls found in the imx8m SOCs
  6 *
  7 * Documentation for this fractional pll can be found at:
  8 *   https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
  9 */
 10
 11#include <linux/clk-provider.h>
 12#include <linux/err.h>
 13#include <linux/export.h>
 14#include <linux/io.h>
 15#include <linux/iopoll.h>
 16#include <linux/slab.h>
 17#include <linux/bitfield.h>
 18
 19#include "clk.h"
 20
 21#define PLL_CFG0		0x0
 22#define PLL_CFG1		0x4
 23
 24#define PLL_LOCK_STATUS		BIT(31)
 25#define PLL_PD_MASK		BIT(19)
 26#define PLL_BYPASS_MASK		BIT(14)
 27#define PLL_NEWDIV_VAL		BIT(12)
 28#define PLL_NEWDIV_ACK		BIT(11)
 29#define PLL_FRAC_DIV_MASK	GENMASK(30, 7)
 30#define PLL_INT_DIV_MASK	GENMASK(6, 0)
 31#define PLL_OUTPUT_DIV_MASK	GENMASK(4, 0)
 32#define PLL_FRAC_DENOM		0x1000000
 33
 34#define PLL_FRAC_LOCK_TIMEOUT	10000
 35#define PLL_FRAC_ACK_TIMEOUT	500000
 36
 37struct clk_frac_pll {
 38	struct clk_hw	hw;
 39	void __iomem	*base;
 40};
 41
 42#define to_clk_frac_pll(_hw) container_of(_hw, struct clk_frac_pll, hw)
 43
 44static int clk_wait_lock(struct clk_frac_pll *pll)
 45{
 46	u32 val;
 47
 48	return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0,
 49					PLL_FRAC_LOCK_TIMEOUT);
 50}
 51
 52static int clk_wait_ack(struct clk_frac_pll *pll)
 53{
 54	u32 val;
 55
 56	/* return directly if the pll is in powerdown or in bypass */
 57	if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK))
 58		return 0;
 59
 60	/* Wait for the pll's divfi and divff to be reloaded */
 61	return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0,
 62					PLL_FRAC_ACK_TIMEOUT);
 63}
 64
 65static int clk_pll_prepare(struct clk_hw *hw)
 66{
 67	struct clk_frac_pll *pll = to_clk_frac_pll(hw);
 68	u32 val;
 69
 70	val = readl_relaxed(pll->base + PLL_CFG0);
 71	val &= ~PLL_PD_MASK;
 72	writel_relaxed(val, pll->base + PLL_CFG0);
 73
 74	return clk_wait_lock(pll);
 75}
 76
 77static void clk_pll_unprepare(struct clk_hw *hw)
 78{
 79	struct clk_frac_pll *pll = to_clk_frac_pll(hw);
 80	u32 val;
 81
 82	val = readl_relaxed(pll->base + PLL_CFG0);
 83	val |= PLL_PD_MASK;
 84	writel_relaxed(val, pll->base + PLL_CFG0);
 85}
 86
 87static int clk_pll_is_prepared(struct clk_hw *hw)
 88{
 89	struct clk_frac_pll *pll = to_clk_frac_pll(hw);
 90	u32 val;
 91
 92	val = readl_relaxed(pll->base + PLL_CFG0);
 93	return (val & PLL_PD_MASK) ? 0 : 1;
 94}
 95
 96static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 97					 unsigned long parent_rate)
 98{
 99	struct clk_frac_pll *pll = to_clk_frac_pll(hw);
100	u32 val, divff, divfi, divq;
101	u64 temp64 = parent_rate;
102	u64 rate;
103
104	val = readl_relaxed(pll->base + PLL_CFG0);
105	divq = (FIELD_GET(PLL_OUTPUT_DIV_MASK, val) + 1) * 2;
106	val = readl_relaxed(pll->base + PLL_CFG1);
107	divff = FIELD_GET(PLL_FRAC_DIV_MASK, val);
108	divfi = FIELD_GET(PLL_INT_DIV_MASK, val);
109
110	temp64 *= 8;
111	temp64 *= divff;
112	do_div(temp64, PLL_FRAC_DENOM);
113	do_div(temp64, divq);
114
115	rate = parent_rate * 8 * (divfi + 1);
116	do_div(rate, divq);
117	rate += temp64;
118
119	return rate;
120}
121
122static int clk_pll_determine_rate(struct clk_hw *hw,
123				  struct clk_rate_request *req)
124{
125	u64 parent_rate = req->best_parent_rate;
126	u32 divff, divfi;
127	u64 temp64;
128
129	parent_rate *= 8;
130	req->rate *= 2;
131	temp64 = req->rate;
132	do_div(temp64, parent_rate);
133	divfi = temp64;
134	temp64 = req->rate - divfi * parent_rate;
135	temp64 *= PLL_FRAC_DENOM;
136	do_div(temp64, parent_rate);
137	divff = temp64;
138
139	temp64 = parent_rate;
140	temp64 *= divff;
141	do_div(temp64, PLL_FRAC_DENOM);
142
143	req->rate = parent_rate * divfi + temp64;
144
145	req->rate = req->rate / 2;
146
147	return 0;
148}
149
150/*
151 * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero
152 * (means the PLL output will be divided by 2). So the PLL output can use
153 * the below formula:
154 * pllout = parent_rate * 8 / 2 * DIVF_VAL;
155 * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24.
156 */
157static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
158			    unsigned long parent_rate)
159{
160	struct clk_frac_pll *pll = to_clk_frac_pll(hw);
161	u32 val, divfi, divff;
162	u64 temp64;
163	int ret;
164
165	parent_rate *= 8;
166	rate *= 2;
167	divfi = rate / parent_rate;
168	temp64 = parent_rate * divfi;
169	temp64 = rate - temp64;
170	temp64 *= PLL_FRAC_DENOM;
171	do_div(temp64, parent_rate);
172	divff = temp64;
173
174	val = readl_relaxed(pll->base + PLL_CFG1);
175	val &= ~(PLL_FRAC_DIV_MASK | PLL_INT_DIV_MASK);
176	val |= (divff << 7) | (divfi - 1);
177	writel_relaxed(val, pll->base + PLL_CFG1);
178
179	val = readl_relaxed(pll->base + PLL_CFG0);
180	val &= ~0x1f;
181	writel_relaxed(val, pll->base + PLL_CFG0);
182
183	/* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */
184	val = readl_relaxed(pll->base + PLL_CFG0);
185	val |= PLL_NEWDIV_VAL;
186	writel_relaxed(val, pll->base + PLL_CFG0);
187
188	ret = clk_wait_ack(pll);
189
190	/* clear the NEV_DIV_VAL */
191	val = readl_relaxed(pll->base + PLL_CFG0);
192	val &= ~PLL_NEWDIV_VAL;
193	writel_relaxed(val, pll->base + PLL_CFG0);
194
195	return ret;
196}
197
198static const struct clk_ops clk_frac_pll_ops = {
199	.prepare	= clk_pll_prepare,
200	.unprepare	= clk_pll_unprepare,
201	.is_prepared	= clk_pll_is_prepared,
202	.recalc_rate	= clk_pll_recalc_rate,
203	.determine_rate = clk_pll_determine_rate,
204	.set_rate	= clk_pll_set_rate,
205};
206
207struct clk_hw *imx_clk_hw_frac_pll(const char *name,
208				   const char *parent_name,
209				   void __iomem *base)
210{
211	struct clk_init_data init;
212	struct clk_frac_pll *pll;
213	struct clk_hw *hw;
214	int ret;
215
216	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
217	if (!pll)
218		return ERR_PTR(-ENOMEM);
219
220	init.name = name;
221	init.ops = &clk_frac_pll_ops;
222	init.flags = 0;
223	init.parent_names = &parent_name;
224	init.num_parents = 1;
225
226	pll->base = base;
227	pll->hw.init = &init;
228
229	hw = &pll->hw;
230
231	ret = clk_hw_register(NULL, hw);
232	if (ret) {
233		kfree(pll);
234		return ERR_PTR(ret);
235	}
236
237	return hw;
238}
239EXPORT_SYMBOL_GPL(imx_clk_hw_frac_pll);