psc.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Clock driver for TI Davinci PSC controllers
  4 *
  5 * Copyright (C) 2017 David Lechner <david@lechnology.com>
  6 *
  7 * Based on: drivers/clk/keystone/gate.c
  8 * Copyright (C) 2013 Texas Instruments.
  9 *	Murali Karicheri <m-karicheri2@ti.com>
 10 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 11 *
 12 * And: arch/arm/mach-davinci/psc.c
 13 * Copyright (C) 2006 Texas Instruments.
 14 */
 15
 16#include <linux/clk-provider.h>
 17#include <linux/clk.h>
 18#include <linux/clk/davinci.h>
 19#include <linux/clkdev.h>
 20#include <linux/err.h>
 21#include <linux/of.h>
 22#include <linux/platform_device.h>
 23#include <linux/property.h>
 24#include <linux/pm_clock.h>
 25#include <linux/pm_domain.h>
 26#include <linux/regmap.h>
 27#include <linux/reset-controller.h>
 28#include <linux/slab.h>
 29#include <linux/types.h>
 30
 31#include "psc.h"
 32
 33/* PSC register offsets */
 34#define EPCPR			0x070
 35#define PTCMD			0x120
 36#define PTSTAT			0x128
 37#define PDSTAT(n)		(0x200 + 4 * (n))
 38#define PDCTL(n)		(0x300 + 4 * (n))
 39#define MDSTAT(n)		(0x800 + 4 * (n))
 40#define MDCTL(n)		(0xa00 + 4 * (n))
 41
 42/* PSC module states */
 43enum davinci_lpsc_state {
 44	LPSC_STATE_SWRSTDISABLE	= 0,
 45	LPSC_STATE_SYNCRST	= 1,
 46	LPSC_STATE_DISABLE	= 2,
 47	LPSC_STATE_ENABLE	= 3,
 48};
 49
 50#define MDSTAT_STATE_MASK	GENMASK(5, 0)
 51#define MDSTAT_MCKOUT		BIT(12)
 52#define PDSTAT_STATE_MASK	GENMASK(4, 0)
 53#define MDCTL_FORCE		BIT(31)
 54#define MDCTL_LRESET		BIT(8)
 55#define PDCTL_EPCGOOD		BIT(8)
 56#define PDCTL_NEXT		BIT(0)
 57
 58struct davinci_psc_data {
 59	struct clk_onecell_data clk_data;
 60	struct genpd_onecell_data pm_data;
 61	struct reset_controller_dev rcdev;
 62};
 63
 64/**
 65 * struct davinci_lpsc_clk - LPSC clock structure
 66 * @dev: the device that provides this LPSC or NULL
 67 * @hw: clk_hw for the LPSC
 68 * @pm_domain: power domain for the LPSC
 69 * @genpd_clk: clock reference owned by @pm_domain
 70 * @regmap: PSC MMIO region
 71 * @md: Module domain (LPSC module id)
 72 * @pd: Power domain
 73 * @flags: LPSC_* quirk flags
 74 */
 75struct davinci_lpsc_clk {
 76	struct device *dev;
 77	struct clk_hw hw;
 78	struct generic_pm_domain pm_domain;
 79	struct clk *genpd_clk;
 80	struct regmap *regmap;
 81	u32 md;
 82	u32 pd;
 83	u32 flags;
 84};
 85
 86#define to_davinci_psc_data(x) container_of(x, struct davinci_psc_data, x)
 87#define to_davinci_lpsc_clk(x) container_of(x, struct davinci_lpsc_clk, x)
 88
 89/**
 90 * best_dev_name - get the "best" device name.
 91 * @dev: the device
 92 *
 93 * Returns the device tree compatible name if the device has a DT node,
 94 * otherwise return the device name. This is mainly needed because clkdev
 95 * lookups are limited to 20 chars for dev_id and when using device tree,
 96 * dev_name(dev) is much longer than that.
 97 */
 98static inline const char *best_dev_name(struct device *dev)
 99{
100	const char *compatible;
101
102	if (!of_property_read_string(dev->of_node, "compatible", &compatible))
103		return compatible;
104
105	return dev_name(dev);
106}
107
108static void davinci_lpsc_config(struct davinci_lpsc_clk *lpsc,
109				enum davinci_lpsc_state next_state)
110{
111	u32 epcpr, pdstat, mdstat, ptstat;
112
113	regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDSTAT_STATE_MASK,
114			  next_state);
115
116	if (lpsc->flags & LPSC_FORCE)
117		regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_FORCE,
118				  MDCTL_FORCE);
119
120	regmap_read(lpsc->regmap, PDSTAT(lpsc->pd), &pdstat);
121	if ((pdstat & PDSTAT_STATE_MASK) == 0) {
122		regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_NEXT,
123				  PDCTL_NEXT);
124
125		regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd));
126
127		regmap_read_poll_timeout(lpsc->regmap, EPCPR, epcpr,
128					 epcpr & BIT(lpsc->pd), 0, 0);
129
130		regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_EPCGOOD,
131				  PDCTL_EPCGOOD);
132	} else {
133		regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd));
134	}
135
136	regmap_read_poll_timeout(lpsc->regmap, PTSTAT, ptstat,
137				 !(ptstat & BIT(lpsc->pd)), 0, 0);
138
139	regmap_read_poll_timeout(lpsc->regmap, MDSTAT(lpsc->md), mdstat,
140				 (mdstat & MDSTAT_STATE_MASK) == next_state,
141				 0, 0);
142}
143
144static int davinci_lpsc_clk_enable(struct clk_hw *hw)
145{
146	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
147
148	davinci_lpsc_config(lpsc, LPSC_STATE_ENABLE);
149
150	return 0;
151}
152
153static void davinci_lpsc_clk_disable(struct clk_hw *hw)
154{
155	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
156
157	davinci_lpsc_config(lpsc, LPSC_STATE_DISABLE);
158}
159
160static int davinci_lpsc_clk_is_enabled(struct clk_hw *hw)
161{
162	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
163	u32 mdstat;
164
165	regmap_read(lpsc->regmap, MDSTAT(lpsc->md), &mdstat);
166
167	return (mdstat & MDSTAT_MCKOUT) ? 1 : 0;
168}
169
170static const struct clk_ops davinci_lpsc_clk_ops = {
171	.enable		= davinci_lpsc_clk_enable,
172	.disable	= davinci_lpsc_clk_disable,
173	.is_enabled	= davinci_lpsc_clk_is_enabled,
174};
175
176static int davinci_psc_genpd_attach_dev(struct generic_pm_domain *pm_domain,
177					struct device *dev)
178{
179	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain);
180	struct clk *clk;
181	int ret;
182
183	/*
184	 * pm_clk_remove_clk() will call clk_put(), so we have to use clk_get()
185	 * to get the clock instead of using lpsc->hw.clk directly.
186	 */
187	clk = clk_get_sys(best_dev_name(lpsc->dev), clk_hw_get_name(&lpsc->hw));
188	if (IS_ERR(clk))
189		return (PTR_ERR(clk));
190
191	ret = pm_clk_create(dev);
192	if (ret < 0)
193		goto fail_clk_put;
194
195	ret = pm_clk_add_clk(dev, clk);
196	if (ret < 0)
197		goto fail_pm_clk_destroy;
198
199	lpsc->genpd_clk = clk;
200
201	return 0;
202
203fail_pm_clk_destroy:
204	pm_clk_destroy(dev);
205fail_clk_put:
206	clk_put(clk);
207
208	return ret;
209}
210
211static void davinci_psc_genpd_detach_dev(struct generic_pm_domain *pm_domain,
212					 struct device *dev)
213{
214	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain);
215
216	pm_clk_remove_clk(dev, lpsc->genpd_clk);
217	pm_clk_destroy(dev);
218
219	lpsc->genpd_clk = NULL;
220}
221
222/**
223 * davinci_lpsc_clk_register - register LPSC clock
224 * @dev: the clocks's device or NULL
225 * @name: name of this clock
226 * @parent_name: name of clock's parent
227 * @regmap: PSC MMIO region
228 * @md: local PSC number
229 * @pd: power domain
230 * @flags: LPSC_* flags
231 */
232static struct davinci_lpsc_clk *
233davinci_lpsc_clk_register(struct device *dev, const char *name,
234			  const char *parent_name, struct regmap *regmap,
235			  u32 md, u32 pd, u32 flags)
236{
237	struct clk_init_data init;
238	struct davinci_lpsc_clk *lpsc;
239	int ret;
240	bool is_on;
241
242	lpsc = kzalloc(sizeof(*lpsc), GFP_KERNEL);
243	if (!lpsc)
244		return ERR_PTR(-ENOMEM);
245
246	init.name = name;
247	init.ops = &davinci_lpsc_clk_ops;
248	init.parent_names = (parent_name ? &parent_name : NULL);
249	init.num_parents = (parent_name ? 1 : 0);
250	init.flags = 0;
251
252	if (flags & LPSC_ALWAYS_ENABLED)
253		init.flags |= CLK_IS_CRITICAL;
254
255	if (flags & LPSC_SET_RATE_PARENT)
256		init.flags |= CLK_SET_RATE_PARENT;
257
258	lpsc->dev = dev;
259	lpsc->regmap = regmap;
260	lpsc->hw.init = &init;
261	lpsc->md = md;
262	lpsc->pd = pd;
263	lpsc->flags = flags;
264
265	ret = clk_hw_register(dev, &lpsc->hw);
266	if (ret < 0) {
267		kfree(lpsc);
268		return ERR_PTR(ret);
269	}
270
271	/* for now, genpd is only registered when using device-tree */
272	if (!dev || !dev->of_node)
273		return lpsc;
274
275	/* genpd attach needs a way to look up this clock */
276	ret = clk_hw_register_clkdev(&lpsc->hw, name, best_dev_name(dev));
277
278	lpsc->pm_domain.name = devm_kasprintf(dev, GFP_KERNEL, "%s: %s",
279					      best_dev_name(dev), name);
280	if (!lpsc->pm_domain.name) {
281		clk_hw_unregister(&lpsc->hw);
282		kfree(lpsc);
283		return ERR_PTR(-ENOMEM);
284	}
285	lpsc->pm_domain.attach_dev = davinci_psc_genpd_attach_dev;
286	lpsc->pm_domain.detach_dev = davinci_psc_genpd_detach_dev;
287	lpsc->pm_domain.flags = GENPD_FLAG_PM_CLK;
288
289	is_on = davinci_lpsc_clk_is_enabled(&lpsc->hw);
290	pm_genpd_init(&lpsc->pm_domain, NULL, is_on);
291
292	return lpsc;
293}
294
295static int davinci_lpsc_clk_reset(struct clk *clk, bool reset)
296{
297	struct clk_hw *hw = __clk_get_hw(clk);
298	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
299	u32 mdctl;
300
301	if (IS_ERR_OR_NULL(lpsc))
302		return -EINVAL;
303
304	mdctl = reset ? 0 : MDCTL_LRESET;
305	regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_LRESET, mdctl);
306
307	return 0;
308}
309
310static int davinci_psc_reset_assert(struct reset_controller_dev *rcdev,
311				    unsigned long id)
312{
313	struct davinci_psc_data *psc = to_davinci_psc_data(rcdev);
314	struct clk *clk = psc->clk_data.clks[id];
315
316	return davinci_lpsc_clk_reset(clk, true);
317}
318
319static int davinci_psc_reset_deassert(struct reset_controller_dev *rcdev,
320				      unsigned long id)
321{
322	struct davinci_psc_data *psc = to_davinci_psc_data(rcdev);
323	struct clk *clk = psc->clk_data.clks[id];
324
325	return davinci_lpsc_clk_reset(clk, false);
326}
327
328static const struct reset_control_ops davinci_psc_reset_ops = {
329	.assert		= davinci_psc_reset_assert,
330	.deassert	= davinci_psc_reset_deassert,
331};
332
333static int davinci_psc_reset_of_xlate(struct reset_controller_dev *rcdev,
334				      const struct of_phandle_args *reset_spec)
335{
336	struct of_phandle_args clkspec = *reset_spec; /* discard const qualifier */
337	struct clk *clk;
338	struct clk_hw *hw;
339	struct davinci_lpsc_clk *lpsc;
340
341	/* the clock node is the same as the reset node */
342	clk = of_clk_get_from_provider(&clkspec);
343	if (IS_ERR(clk))
344		return PTR_ERR(clk);
345
346	hw = __clk_get_hw(clk);
347	lpsc = to_davinci_lpsc_clk(hw);
348	clk_put(clk);
349
350	/* not all modules support local reset */
351	if (!(lpsc->flags & LPSC_LOCAL_RESET))
352		return -EINVAL;
353
354	return lpsc->md;
355}
356
357static const struct regmap_config davinci_psc_regmap_config = {
358	.reg_bits	= 32,
359	.reg_stride	= 4,
360	.val_bits	= 32,
361};
362
363static struct davinci_psc_data *
364__davinci_psc_register_clocks(struct device *dev,
365			      const struct davinci_lpsc_clk_info *info,
366			      int num_clks,
367			      void __iomem *base)
368{
369	struct davinci_psc_data *psc;
370	struct clk **clks;
371	struct generic_pm_domain **pm_domains;
372	struct regmap *regmap;
373	int i, ret;
374
375	psc = kzalloc(sizeof(*psc), GFP_KERNEL);
376	if (!psc)
377		return ERR_PTR(-ENOMEM);
378
379	clks = kmalloc_array(num_clks, sizeof(*clks), GFP_KERNEL);
380	if (!clks) {
381		ret = -ENOMEM;
382		goto err_free_psc;
383	}
384
385	psc->clk_data.clks = clks;
386	psc->clk_data.clk_num = num_clks;
387
388	/*
389	 * init array with error so that of_clk_src_onecell_get() doesn't
390	 * return NULL for gaps in the sparse array
391	 */
392	for (i = 0; i < num_clks; i++)
393		clks[i] = ERR_PTR(-ENOENT);
394
395	pm_domains = kcalloc(num_clks, sizeof(*pm_domains), GFP_KERNEL);
396	if (!pm_domains) {
397		ret = -ENOMEM;
398		goto err_free_clks;
399	}
400
401	psc->pm_data.domains = pm_domains;
402	psc->pm_data.num_domains = num_clks;
403
404	regmap = regmap_init_mmio(dev, base, &davinci_psc_regmap_config);
405	if (IS_ERR(regmap)) {
406		ret = PTR_ERR(regmap);
407		goto err_free_pm_domains;
408	}
409
410	for (; info->name; info++) {
411		struct davinci_lpsc_clk *lpsc;
412
413		lpsc = davinci_lpsc_clk_register(dev, info->name, info->parent,
414						 regmap, info->md, info->pd,
415						 info->flags);
416		if (IS_ERR(lpsc)) {
417			dev_warn(dev, "Failed to register %s (%ld)\n",
418				 info->name, PTR_ERR(lpsc));
419			continue;
420		}
421
422		clks[info->md] = lpsc->hw.clk;
423		pm_domains[info->md] = &lpsc->pm_domain;
424	}
425
426	/*
427	 * for now, a reset controller is only registered when there is a device
428	 * to associate it with.
429	 */
430	if (!dev)
431		return psc;
432
433	psc->rcdev.ops = &davinci_psc_reset_ops;
434	psc->rcdev.owner = THIS_MODULE;
435	psc->rcdev.dev = dev;
436	psc->rcdev.of_node = dev->of_node;
437	psc->rcdev.of_reset_n_cells = 1;
438	psc->rcdev.of_xlate = davinci_psc_reset_of_xlate;
439	psc->rcdev.nr_resets = num_clks;
440
441	ret = devm_reset_controller_register(dev, &psc->rcdev);
442	if (ret < 0)
443		dev_warn(dev, "Failed to register reset controller (%d)\n", ret);
444
445	return psc;
446
447err_free_pm_domains:
448	kfree(pm_domains);
449err_free_clks:
450	kfree(clks);
451err_free_psc:
452	kfree(psc);
453
454	return ERR_PTR(ret);
455}
456
457int davinci_psc_register_clocks(struct device *dev,
458				const struct davinci_lpsc_clk_info *info,
459				u8 num_clks,
460				void __iomem *base)
461{
462	struct davinci_psc_data *psc;
463
464	psc = __davinci_psc_register_clocks(dev, info, num_clks, base);
465	if (IS_ERR(psc))
466		return PTR_ERR(psc);
467
468	for (; info->name; info++) {
469		const struct davinci_lpsc_clkdev_info *cdevs = info->cdevs;
470		struct clk *clk = psc->clk_data.clks[info->md];
471
472		if (!cdevs || IS_ERR_OR_NULL(clk))
473			continue;
474
475		for (; cdevs->con_id || cdevs->dev_id; cdevs++)
476			clk_register_clkdev(clk, cdevs->con_id, cdevs->dev_id);
477	}
478
479	return 0;
480}
481
482int of_davinci_psc_clk_init(struct device *dev,
483			    const struct davinci_lpsc_clk_info *info,
484			    u8 num_clks,
485			    void __iomem *base)
486{
487	struct device_node *node = dev->of_node;
488	struct davinci_psc_data *psc;
489
490	psc = __davinci_psc_register_clocks(dev, info, num_clks, base);
491	if (IS_ERR(psc))
492		return PTR_ERR(psc);
493
494	of_genpd_add_provider_onecell(node, &psc->pm_data);
495
496	of_clk_add_provider(node, of_clk_src_onecell_get, &psc->clk_data);
497
498	return 0;
499}
500
501static const struct of_device_id davinci_psc_of_match[] = {
502	{ .compatible = "ti,da850-psc0", .data = &of_da850_psc0_init_data },
503	{ .compatible = "ti,da850-psc1", .data = &of_da850_psc1_init_data },
504	{ }
505};
506
507static const struct platform_device_id davinci_psc_id_table[] = {
508	{ .name = "da850-psc0", .driver_data = (kernel_ulong_t)&da850_psc0_init_data },
509	{ .name = "da850-psc1", .driver_data = (kernel_ulong_t)&da850_psc1_init_data },
510	{ }
511};
512
513static int davinci_psc_probe(struct platform_device *pdev)
514{
515	struct device *dev = &pdev->dev;
516	const struct davinci_psc_init_data *init_data = NULL;
517	void __iomem *base;
518	int ret;
519
520	init_data = device_get_match_data(dev);
521	if (!init_data && pdev->id_entry)
522		init_data = (void *)pdev->id_entry->driver_data;
523
524	if (!init_data) {
525		dev_err(dev, "unable to find driver init data\n");
526		return -EINVAL;
527	}
528
529	base = devm_platform_ioremap_resource(pdev, 0);
530	if (IS_ERR(base))
531		return PTR_ERR(base);
532
533	ret = devm_clk_bulk_get(dev, init_data->num_parent_clks,
534				init_data->parent_clks);
535	if (ret < 0)
536		return ret;
537
538	return init_data->psc_init(dev, base);
539}
540
541static struct platform_driver davinci_psc_driver = {
542	.probe		= davinci_psc_probe,
543	.driver		= {
544		.name		= "davinci-psc-clk",
545		.of_match_table	= davinci_psc_of_match,
546	},
547	.id_table	= davinci_psc_id_table,
548};
549
550static int __init davinci_psc_driver_init(void)
551{
552	return platform_driver_register(&davinci_psc_driver);
553}
554
555/* has to be postcore_initcall because davinci_gpio depend on PSC clocks */
556postcore_initcall(davinci_psc_driver_init);