pll.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * PLL clock driver for TI Davinci SoCs
  4 *
  5 * Copyright (C) 2018 David Lechner <david@lechnology.com>
  6 *
  7 * Based on arch/arm/mach-davinci/clock.c
  8 * Copyright (C) 2006-2007 Texas Instruments.
  9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
 10 */
 11
 12#include <linux/clk-provider.h>
 13#include <linux/clk.h>
 14#include <linux/clk/davinci.h>
 15#include <linux/delay.h>
 16#include <linux/err.h>
 17#include <linux/io.h>
 18#include <linux/kernel.h>
 19#include <linux/mfd/syscon.h>
 20#include <linux/notifier.h>
 21#include <linux/of.h>
 22#include <linux/platform_device.h>
 23#include <linux/property.h>
 24#include <linux/regmap.h>
 25#include <linux/slab.h>
 26#include <linux/types.h>
 27
 28#include "pll.h"
 29
 30#define MAX_NAME_SIZE	20
 31#define OSCIN_CLK_NAME	"oscin"
 32
 33#define REVID		0x000
 34#define PLLCTL		0x100
 35#define OCSEL		0x104
 36#define PLLSECCTL	0x108
 37#define PLLM		0x110
 38#define PREDIV		0x114
 39#define PLLDIV1		0x118
 40#define PLLDIV2		0x11c
 41#define PLLDIV3		0x120
 42#define OSCDIV		0x124
 43#define POSTDIV		0x128
 44#define BPDIV		0x12c
 45#define PLLCMD		0x138
 46#define PLLSTAT		0x13c
 47#define ALNCTL		0x140
 48#define DCHANGE		0x144
 49#define CKEN		0x148
 50#define CKSTAT		0x14c
 51#define SYSTAT		0x150
 52#define PLLDIV4		0x160
 53#define PLLDIV5		0x164
 54#define PLLDIV6		0x168
 55#define PLLDIV7		0x16c
 56#define PLLDIV8		0x170
 57#define PLLDIV9		0x174
 58
 59#define PLLCTL_PLLEN		BIT(0)
 60#define PLLCTL_PLLPWRDN		BIT(1)
 61#define PLLCTL_PLLRST		BIT(3)
 62#define PLLCTL_PLLDIS		BIT(4)
 63#define PLLCTL_PLLENSRC		BIT(5)
 64#define PLLCTL_CLKMODE		BIT(8)
 65
 66/* shared by most *DIV registers */
 67#define DIV_RATIO_SHIFT		0
 68#define DIV_RATIO_WIDTH		5
 69#define DIV_ENABLE_SHIFT	15
 70
 71#define PLLCMD_GOSET		BIT(0)
 72#define PLLSTAT_GOSTAT		BIT(0)
 73
 74#define CKEN_OBSCLK_SHIFT	1
 75#define CKEN_AUXEN_SHIFT	0
 76
 77/*
 78 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
 79 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
 80 * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
 81 * is ~25MHz. Units are micro seconds.
 82 */
 83#define PLL_BYPASS_TIME		1
 84
 85/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
 86#define PLL_RESET_TIME		1
 87
 88/*
 89 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
 90 * Units are micro seconds.
 91 */
 92#define PLL_LOCK_TIME		20
 93
 94/**
 95 * struct davinci_pll_clk - Main PLL clock (aka PLLOUT)
 96 * @hw: clk_hw for the pll
 97 * @base: Base memory address
 98 * @pllm_min: The minimum allowable PLLM[PLLM] value
 99 * @pllm_max: The maximum allowable PLLM[PLLM] value
100 * @pllm_mask: Bitmask for PLLM[PLLM] value
101 */
102struct davinci_pll_clk {
103	struct clk_hw hw;
104	void __iomem *base;
105	u32 pllm_min;
106	u32 pllm_max;
107	u32 pllm_mask;
108};
109
110#define to_davinci_pll_clk(_hw) \
111	container_of((_hw), struct davinci_pll_clk, hw)
112
113static unsigned long davinci_pll_recalc_rate(struct clk_hw *hw,
114					     unsigned long parent_rate)
115{
116	struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
117	unsigned long rate = parent_rate;
118	u32 mult;
119
120	mult = readl(pll->base + PLLM) & pll->pllm_mask;
121	rate *= mult + 1;
122
123	return rate;
124}
125
126static int davinci_pll_determine_rate(struct clk_hw *hw,
127				      struct clk_rate_request *req)
128{
129	struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
130	struct clk_hw *parent = req->best_parent_hw;
131	unsigned long parent_rate = req->best_parent_rate;
132	unsigned long rate = req->rate;
133	unsigned long best_rate, r;
134	u32 mult;
135
136	/* there is a limited range of valid outputs (see datasheet) */
137	if (rate < req->min_rate)
138		return -EINVAL;
139
140	rate = min(rate, req->max_rate);
141	mult = rate / parent_rate;
142	best_rate = parent_rate * mult;
143
144	/* easy case when there is no PREDIV */
145	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
146		if (best_rate < req->min_rate)
147			return -EINVAL;
148
149		if (mult < pll->pllm_min || mult > pll->pllm_max)
150			return -EINVAL;
151
152		req->rate = best_rate;
153
154		return 0;
155	}
156
157	/* see if the PREDIV clock can help us */
158	best_rate = 0;
159
160	for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) {
161		parent_rate = clk_hw_round_rate(parent, rate / mult);
162		r = parent_rate * mult;
163		if (r < req->min_rate)
164			continue;
165		if (r > rate || r > req->max_rate)
166			break;
167		if (r > best_rate) {
168			best_rate = r;
169			req->rate = best_rate;
170			req->best_parent_rate = parent_rate;
171			if (best_rate == rate)
172				break;
173		}
174	}
175
176	return 0;
177}
178
179static int davinci_pll_set_rate(struct clk_hw *hw, unsigned long rate,
180				unsigned long parent_rate)
181{
182	struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
183	u32 mult;
184
185	mult = rate / parent_rate;
186	writel(mult - 1, pll->base + PLLM);
187
188	return 0;
189}
190
191#ifdef CONFIG_DEBUG_FS
192static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry);
193#else
194#define davinci_pll_debug_init NULL
195#endif
196
197static const struct clk_ops davinci_pll_ops = {
198	.recalc_rate	= davinci_pll_recalc_rate,
199	.determine_rate	= davinci_pll_determine_rate,
200	.set_rate	= davinci_pll_set_rate,
201	.debug_init	= davinci_pll_debug_init,
202};
203
204/* PLLM works differently on DM365 */
205static unsigned long dm365_pll_recalc_rate(struct clk_hw *hw,
206					   unsigned long parent_rate)
207{
208	struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
209	unsigned long rate = parent_rate;
210	u32 mult;
211
212	mult = readl(pll->base + PLLM) & pll->pllm_mask;
213	rate *= mult * 2;
214
215	return rate;
216}
217
218static const struct clk_ops dm365_pll_ops = {
219	.recalc_rate	= dm365_pll_recalc_rate,
220	.debug_init	= davinci_pll_debug_init,
221};
222
223/**
224 * davinci_pll_div_register - common *DIV clock implementation
225 * @dev: The PLL platform device or NULL
226 * @name: the clock name
227 * @parent_name: the parent clock name
228 * @reg: the *DIV register
229 * @fixed: if true, the divider is a fixed value
230 * @flags: bitmap of CLK_* flags from clock-provider.h
231 */
232static struct clk *davinci_pll_div_register(struct device *dev,
233					    const char *name,
234					    const char *parent_name,
235					    void __iomem *reg,
236					    bool fixed, u32 flags)
237{
238	const char * const *parent_names = parent_name ? &parent_name : NULL;
239	int num_parents = parent_name ? 1 : 0;
240	const struct clk_ops *divider_ops = &clk_divider_ops;
241	struct clk_gate *gate;
242	struct clk_divider *divider;
243	struct clk *clk;
244	int ret;
245
246	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
247	if (!gate)
248		return ERR_PTR(-ENOMEM);
249
250	gate->reg = reg;
251	gate->bit_idx = DIV_ENABLE_SHIFT;
252
253	divider = kzalloc(sizeof(*divider), GFP_KERNEL);
254	if (!divider) {
255		ret = -ENOMEM;
256		goto err_free_gate;
257	}
258
259	divider->reg = reg;
260	divider->shift = DIV_RATIO_SHIFT;
261	divider->width = DIV_RATIO_WIDTH;
262
263	if (fixed) {
264		divider->flags |= CLK_DIVIDER_READ_ONLY;
265		divider_ops = &clk_divider_ro_ops;
266	}
267
268	clk = clk_register_composite(dev, name, parent_names, num_parents,
269				     NULL, NULL, &divider->hw, divider_ops,
270				     &gate->hw, &clk_gate_ops, flags);
271	if (IS_ERR(clk)) {
272		ret = PTR_ERR(clk);
273		goto err_free_divider;
274	}
275
276	return clk;
277
278err_free_divider:
279	kfree(divider);
280err_free_gate:
281	kfree(gate);
282
283	return ERR_PTR(ret);
284}
285
286struct davinci_pllen_clk {
287	struct clk_hw hw;
288	void __iomem *base;
289};
290
291#define to_davinci_pllen_clk(_hw) \
292	container_of((_hw), struct davinci_pllen_clk, hw)
293
294static const struct clk_ops davinci_pllen_ops = {
295	/* this clocks just uses the clock notification feature */
296};
297
298/*
299 * The PLL has to be switched into bypass mode while we are chaning the rate,
300 * so we do that on the PLLEN clock since it is the end of the line. This will
301 * switch to bypass before any of the parent clocks (PREDIV, PLL, POSTDIV) are
302 * changed and will switch back to the PLL after the changes have been made.
303 */
304static int davinci_pllen_rate_change(struct notifier_block *nb,
305				     unsigned long flags, void *data)
306{
307	struct clk_notifier_data *cnd = data;
308	struct clk_hw *hw = __clk_get_hw(cnd->clk);
309	struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw);
310	u32 ctrl;
311
312	ctrl = readl(pll->base + PLLCTL);
313
314	if (flags == PRE_RATE_CHANGE) {
315		/* Switch the PLL to bypass mode */
316		ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
317		writel(ctrl, pll->base + PLLCTL);
318
319		udelay(PLL_BYPASS_TIME);
320
321		/* Reset and enable PLL */
322		ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
323		writel(ctrl, pll->base + PLLCTL);
324	} else {
325		udelay(PLL_RESET_TIME);
326
327		/* Bring PLL out of reset */
328		ctrl |= PLLCTL_PLLRST;
329		writel(ctrl, pll->base + PLLCTL);
330
331		udelay(PLL_LOCK_TIME);
332
333		/* Remove PLL from bypass mode */
334		ctrl |= PLLCTL_PLLEN;
335		writel(ctrl, pll->base + PLLCTL);
336	}
337
338	return NOTIFY_OK;
339}
340
341static struct notifier_block davinci_pllen_notifier = {
342	.notifier_call = davinci_pllen_rate_change,
343};
344
345/**
346 * davinci_pll_clk_register - Register a PLL clock
347 * @dev: The PLL platform device or NULL
348 * @info: The device-specific clock info
349 * @parent_name: The parent clock name
350 * @base: The PLL's memory region
351 * @cfgchip: CFGCHIP syscon regmap for info->unlock_reg or NULL
352 *
353 * This creates a series of clocks that represent the PLL.
354 *
355 *     OSCIN > [PREDIV >] PLL > [POSTDIV >] PLLEN
356 *
357 * - OSCIN is the parent clock (on secondary PLL, may come from primary PLL)
358 * - PREDIV and POSTDIV are optional (depends on the PLL controller)
359 * - PLL is the PLL output (aka PLLOUT)
360 * - PLLEN is the bypass multiplexer
361 *
362 * Returns: The PLLOUT clock or a negative error code.
363 */
364struct clk *davinci_pll_clk_register(struct device *dev,
365				     const struct davinci_pll_clk_info *info,
366				     const char *parent_name,
367				     void __iomem *base,
368				     struct regmap *cfgchip)
369{
370	char prediv_name[MAX_NAME_SIZE];
371	char pllout_name[MAX_NAME_SIZE];
372	char postdiv_name[MAX_NAME_SIZE];
373	char pllen_name[MAX_NAME_SIZE];
374	struct clk_init_data init;
375	struct davinci_pll_clk *pllout;
376	struct davinci_pllen_clk *pllen;
377	struct clk *oscin_clk = NULL;
378	struct clk *prediv_clk = NULL;
379	struct clk *pllout_clk;
380	struct clk *postdiv_clk = NULL;
381	struct clk *pllen_clk;
382	int ret;
383
384	if (info->flags & PLL_HAS_CLKMODE) {
385		/*
386		 * If a PLL has PLLCTL[CLKMODE], then it is the primary PLL.
387		 * We register a clock named "oscin" that serves as the internal
388		 * "input clock" domain shared by both PLLs (if there are 2)
389		 * and will be the parent clock to the AUXCLK, SYSCLKBP and
390		 * OBSCLK domains. NB: The various TRMs use "OSCIN" to mean
391		 * a number of different things. In this driver we use it to
392		 * mean the signal after the PLLCTL[CLKMODE] switch.
393		 */
394		oscin_clk = clk_register_fixed_factor(dev, OSCIN_CLK_NAME,
395						      parent_name, 0, 1, 1);
396		if (IS_ERR(oscin_clk))
397			return oscin_clk;
398
399		parent_name = OSCIN_CLK_NAME;
400	}
401
402	if (info->flags & PLL_HAS_PREDIV) {
403		bool fixed = info->flags & PLL_PREDIV_FIXED_DIV;
404		u32 flags = 0;
405
406		snprintf(prediv_name, MAX_NAME_SIZE, "%s_prediv", info->name);
407
408		if (info->flags & PLL_PREDIV_ALWAYS_ENABLED)
409			flags |= CLK_IS_CRITICAL;
410
411		/* Some? DM355 chips don't correctly report the PREDIV value */
412		if (info->flags & PLL_PREDIV_FIXED8)
413			prediv_clk = clk_register_fixed_factor(dev, prediv_name,
414							parent_name, flags, 1, 8);
415		else
416			prediv_clk = davinci_pll_div_register(dev, prediv_name,
417				parent_name, base + PREDIV, fixed, flags);
418		if (IS_ERR(prediv_clk)) {
419			ret = PTR_ERR(prediv_clk);
420			goto err_unregister_oscin;
421		}
422
423		parent_name = prediv_name;
424	}
425
426	/* Unlock writing to PLL registers */
427	if (info->unlock_reg) {
428		if (IS_ERR_OR_NULL(cfgchip))
429			dev_warn(dev, "Failed to get CFGCHIP (%ld)\n",
430				 PTR_ERR(cfgchip));
431		else
432			regmap_write_bits(cfgchip, info->unlock_reg,
433					  info->unlock_mask, 0);
434	}
435
436	pllout = kzalloc(sizeof(*pllout), GFP_KERNEL);
437	if (!pllout) {
438		ret = -ENOMEM;
439		goto err_unregister_prediv;
440	}
441
442	snprintf(pllout_name, MAX_NAME_SIZE, "%s_pllout", info->name);
443
444	init.name = pllout_name;
445	if (info->flags & PLL_PLLM_2X)
446		init.ops = &dm365_pll_ops;
447	else
448		init.ops = &davinci_pll_ops;
449	init.parent_names = &parent_name;
450	init.num_parents = 1;
451	init.flags = 0;
452
453	if (info->flags & PLL_HAS_PREDIV)
454		init.flags |= CLK_SET_RATE_PARENT;
455
456	pllout->hw.init = &init;
457	pllout->base = base;
458	pllout->pllm_mask = info->pllm_mask;
459	pllout->pllm_min = info->pllm_min;
460	pllout->pllm_max = info->pllm_max;
461
462	pllout_clk = clk_register(dev, &pllout->hw);
463	if (IS_ERR(pllout_clk)) {
464		ret = PTR_ERR(pllout_clk);
465		goto err_free_pllout;
466	}
467
468	clk_hw_set_rate_range(&pllout->hw, info->pllout_min_rate,
469			      info->pllout_max_rate);
470
471	parent_name = pllout_name;
472
473	if (info->flags & PLL_HAS_POSTDIV) {
474		bool fixed = info->flags & PLL_POSTDIV_FIXED_DIV;
475		u32 flags = CLK_SET_RATE_PARENT;
476
477		snprintf(postdiv_name, MAX_NAME_SIZE, "%s_postdiv", info->name);
478
479		if (info->flags & PLL_POSTDIV_ALWAYS_ENABLED)
480			flags |= CLK_IS_CRITICAL;
481
482		postdiv_clk = davinci_pll_div_register(dev, postdiv_name,
483				parent_name, base + POSTDIV, fixed, flags);
484		if (IS_ERR(postdiv_clk)) {
485			ret = PTR_ERR(postdiv_clk);
486			goto err_unregister_pllout;
487		}
488
489		parent_name = postdiv_name;
490	}
491
492	pllen = kzalloc(sizeof(*pllen), GFP_KERNEL);
493	if (!pllen) {
494		ret = -ENOMEM;
495		goto err_unregister_postdiv;
496	}
497
498	snprintf(pllen_name, MAX_NAME_SIZE, "%s_pllen", info->name);
499
500	init.name = pllen_name;
501	init.ops = &davinci_pllen_ops;
502	init.parent_names = &parent_name;
503	init.num_parents = 1;
504	init.flags = CLK_SET_RATE_PARENT;
505
506	pllen->hw.init = &init;
507	pllen->base = base;
508
509	pllen_clk = clk_register(dev, &pllen->hw);
510	if (IS_ERR(pllen_clk)) {
511		ret = PTR_ERR(pllen_clk);
512		goto err_free_pllen;
513	}
514
515	clk_notifier_register(pllen_clk, &davinci_pllen_notifier);
516
517	return pllout_clk;
518
519err_free_pllen:
520	kfree(pllen);
521err_unregister_postdiv:
522	clk_unregister(postdiv_clk);
523err_unregister_pllout:
524	clk_unregister(pllout_clk);
525err_free_pllout:
526	kfree(pllout);
527err_unregister_prediv:
528	clk_unregister(prediv_clk);
529err_unregister_oscin:
530	clk_unregister(oscin_clk);
531
532	return ERR_PTR(ret);
533}
534
535/**
536 * davinci_pll_auxclk_register - Register bypass clock (AUXCLK)
537 * @dev: The PLL platform device or NULL
538 * @name: The clock name
539 * @base: The PLL memory region
540 */
541struct clk *davinci_pll_auxclk_register(struct device *dev,
542					const char *name,
543					void __iomem *base)
544{
545	return clk_register_gate(dev, name, OSCIN_CLK_NAME, 0, base + CKEN,
546				 CKEN_AUXEN_SHIFT, 0, NULL);
547}
548
549/**
550 * davinci_pll_sysclkbp_clk_register - Register bypass divider clock (SYSCLKBP)
551 * @dev: The PLL platform device or NULL
552 * @name: The clock name
553 * @base: The PLL memory region
554 */
555struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev,
556					      const char *name,
557					      void __iomem *base)
558{
559	return clk_register_divider(dev, name, OSCIN_CLK_NAME, 0, base + BPDIV,
560				    DIV_RATIO_SHIFT, DIV_RATIO_WIDTH,
561				    CLK_DIVIDER_READ_ONLY, NULL);
562}
563
564/**
565 * davinci_pll_obsclk_register - Register oscillator divider clock (OBSCLK)
566 * @dev: The PLL platform device or NULL
567 * @info: The clock info
568 * @base: The PLL memory region
569 */
570struct clk *
571davinci_pll_obsclk_register(struct device *dev,
572			    const struct davinci_pll_obsclk_info *info,
573			    void __iomem *base)
574{
575	struct clk_mux *mux;
576	struct clk_gate *gate;
577	struct clk_divider *divider;
578	struct clk *clk;
579	u32 oscdiv;
580	int ret;
581
582	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
583	if (!mux)
584		return ERR_PTR(-ENOMEM);
585
586	mux->reg = base + OCSEL;
587	mux->table = info->table;
588	mux->mask = info->ocsrc_mask;
589
590	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
591	if (!gate) {
592		ret = -ENOMEM;
593		goto err_free_mux;
594	}
595
596	gate->reg = base + CKEN;
597	gate->bit_idx = CKEN_OBSCLK_SHIFT;
598
599	divider = kzalloc(sizeof(*divider), GFP_KERNEL);
600	if (!divider) {
601		ret = -ENOMEM;
602		goto err_free_gate;
603	}
604
605	divider->reg = base + OSCDIV;
606	divider->shift = DIV_RATIO_SHIFT;
607	divider->width = DIV_RATIO_WIDTH;
608
609	/* make sure divider is enabled just in case bootloader disabled it */
610	oscdiv = readl(base + OSCDIV);
611	oscdiv |= BIT(DIV_ENABLE_SHIFT);
612	writel(oscdiv, base + OSCDIV);
613
614	clk = clk_register_composite(dev, info->name, info->parent_names,
615				     info->num_parents,
616				     &mux->hw, &clk_mux_ops,
617				     &divider->hw, &clk_divider_ops,
618				     &gate->hw, &clk_gate_ops, 0);
619
620	if (IS_ERR(clk)) {
621		ret = PTR_ERR(clk);
622		goto err_free_divider;
623	}
624
625	return clk;
626
627err_free_divider:
628	kfree(divider);
629err_free_gate:
630	kfree(gate);
631err_free_mux:
632	kfree(mux);
633
634	return ERR_PTR(ret);
635}
636
637/* The PLL SYSCLKn clocks have a mechanism for synchronizing rate changes. */
638static int davinci_pll_sysclk_rate_change(struct notifier_block *nb,
639					  unsigned long flags, void *data)
640{
641	struct clk_notifier_data *cnd = data;
642	struct clk_hw *hw = __clk_get_hw(clk_get_parent(cnd->clk));
643	struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw);
644	u32 pllcmd, pllstat;
645
646	switch (flags) {
647	case POST_RATE_CHANGE:
648		/* apply the changes */
649		pllcmd = readl(pll->base + PLLCMD);
650		pllcmd |= PLLCMD_GOSET;
651		writel(pllcmd, pll->base + PLLCMD);
652		fallthrough;
653	case PRE_RATE_CHANGE:
654		/* Wait until for outstanding changes to take effect */
655		do {
656			pllstat = readl(pll->base + PLLSTAT);
657		} while (pllstat & PLLSTAT_GOSTAT);
658		break;
659	}
660
661	return NOTIFY_OK;
662}
663
664static struct notifier_block davinci_pll_sysclk_notifier = {
665	.notifier_call = davinci_pll_sysclk_rate_change,
666};
667
668/**
669 * davinci_pll_sysclk_register - Register divider clocks (SYSCLKn)
670 * @dev: The PLL platform device or NULL
671 * @info: The clock info
672 * @base: The PLL memory region
673 */
674struct clk *
675davinci_pll_sysclk_register(struct device *dev,
676			    const struct davinci_pll_sysclk_info *info,
677			    void __iomem *base)
678{
679	const struct clk_ops *divider_ops = &clk_divider_ops;
680	struct clk_gate *gate;
681	struct clk_divider *divider;
682	struct clk *clk;
683	u32 reg;
684	u32 flags = 0;
685	int ret;
686
687	/* PLLDIVn registers are not entirely consecutive */
688	if (info->id < 4)
689		reg = PLLDIV1 + 4 * (info->id - 1);
690	else
691		reg = PLLDIV4 + 4 * (info->id - 4);
692
693	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
694	if (!gate)
695		return ERR_PTR(-ENOMEM);
696
697	gate->reg = base + reg;
698	gate->bit_idx = DIV_ENABLE_SHIFT;
699
700	divider = kzalloc(sizeof(*divider), GFP_KERNEL);
701	if (!divider) {
702		ret = -ENOMEM;
703		goto err_free_gate;
704	}
705
706	divider->reg = base + reg;
707	divider->shift = DIV_RATIO_SHIFT;
708	divider->width = info->ratio_width;
709	divider->flags = 0;
710
711	if (info->flags & SYSCLK_FIXED_DIV) {
712		divider->flags |= CLK_DIVIDER_READ_ONLY;
713		divider_ops = &clk_divider_ro_ops;
714	}
715
716	/* Only the ARM clock can change the parent PLL rate */
717	if (info->flags & SYSCLK_ARM_RATE)
718		flags |= CLK_SET_RATE_PARENT;
719
720	if (info->flags & SYSCLK_ALWAYS_ENABLED)
721		flags |= CLK_IS_CRITICAL;
722
723	clk = clk_register_composite(dev, info->name, &info->parent_name, 1,
724				     NULL, NULL, &divider->hw, divider_ops,
725				     &gate->hw, &clk_gate_ops, flags);
726	if (IS_ERR(clk)) {
727		ret = PTR_ERR(clk);
728		goto err_free_divider;
729	}
730
731	clk_notifier_register(clk, &davinci_pll_sysclk_notifier);
732
733	return clk;
734
735err_free_divider:
736	kfree(divider);
737err_free_gate:
738	kfree(gate);
739
740	return ERR_PTR(ret);
741}
742
743int of_davinci_pll_init(struct device *dev, struct device_node *node,
744			const struct davinci_pll_clk_info *info,
745			const struct davinci_pll_obsclk_info *obsclk_info,
746			const struct davinci_pll_sysclk_info **div_info,
747			u8 max_sysclk_id,
748			void __iomem *base,
749			struct regmap *cfgchip)
750{
751	struct device_node *child;
752	const char *parent_name;
753	struct clk *clk;
754
755	if (info->flags & PLL_HAS_CLKMODE)
756		parent_name = of_clk_get_parent_name(node, 0);
757	else
758		parent_name = OSCIN_CLK_NAME;
759
760	clk = davinci_pll_clk_register(dev, info, parent_name, base, cfgchip);
761	if (IS_ERR(clk)) {
762		dev_err(dev, "failed to register %s\n", info->name);
763		return PTR_ERR(clk);
764	}
765
766	child = of_get_available_child_by_name(node, "pllout");
767	if (child) {
768		of_clk_add_provider(child, of_clk_src_simple_get, clk);
769		of_node_put(child);
770	}
771
772	child = of_get_available_child_by_name(node, "sysclk");
773	if (child) {
774		struct clk_onecell_data *clk_data;
775		struct clk **clks;
776		int n_clks =  max_sysclk_id + 1;
777		int i;
778
779		clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
780		if (!clk_data) {
781			of_node_put(child);
782			return -ENOMEM;
783		}
784
785		clks = kmalloc_array(n_clks, sizeof(*clks), GFP_KERNEL);
786		if (!clks) {
787			kfree(clk_data);
788			of_node_put(child);
789			return -ENOMEM;
790		}
791
792		clk_data->clks = clks;
793		clk_data->clk_num = n_clks;
794
795		for (i = 0; i < n_clks; i++)
796			clks[i] = ERR_PTR(-ENOENT);
797
798		for (; *div_info; div_info++) {
799			clk = davinci_pll_sysclk_register(dev, *div_info, base);
800			if (IS_ERR(clk))
801				dev_warn(dev, "failed to register %s (%ld)\n",
802					 (*div_info)->name, PTR_ERR(clk));
803			else
804				clks[(*div_info)->id] = clk;
805		}
806		of_clk_add_provider(child, of_clk_src_onecell_get, clk_data);
807		of_node_put(child);
808	}
809
810	child = of_get_available_child_by_name(node, "auxclk");
811	if (child) {
812		char child_name[MAX_NAME_SIZE];
813
814		snprintf(child_name, MAX_NAME_SIZE, "%s_auxclk", info->name);
815
816		clk = davinci_pll_auxclk_register(dev, child_name, base);
817		if (IS_ERR(clk))
818			dev_warn(dev, "failed to register %s (%ld)\n",
819				 child_name, PTR_ERR(clk));
820		else
821			of_clk_add_provider(child, of_clk_src_simple_get, clk);
822
823		of_node_put(child);
824	}
825
826	child = of_get_available_child_by_name(node, "obsclk");
827	if (child) {
828		if (obsclk_info)
829			clk = davinci_pll_obsclk_register(dev, obsclk_info, base);
830		else
831			clk = ERR_PTR(-EINVAL);
832
833		if (IS_ERR(clk))
834			dev_warn(dev, "failed to register obsclk (%ld)\n",
835				 PTR_ERR(clk));
836		else
837			of_clk_add_provider(child, of_clk_src_simple_get, clk);
838		of_node_put(child);
839	}
840
841	return 0;
842}
843
844/* needed in early boot for clocksource/clockevent */
845CLK_OF_DECLARE(da850_pll0, "ti,da850-pll0", of_da850_pll0_init);
846
847static const struct of_device_id davinci_pll_of_match[] = {
848	{ .compatible = "ti,da850-pll1", .data = of_da850_pll1_init },
849	{ }
850};
851
852static const struct platform_device_id davinci_pll_id_table[] = {
853	{ .name = "da850-pll0",  .driver_data = (kernel_ulong_t)da850_pll0_init  },
854	{ .name = "da850-pll1",  .driver_data = (kernel_ulong_t)da850_pll1_init  },
855	{ }
856};
857
858typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base,
859				struct regmap *cfgchip);
860
861static int davinci_pll_probe(struct platform_device *pdev)
862{
863	struct device *dev = &pdev->dev;
864	davinci_pll_init pll_init = NULL;
865	struct regmap *cfgchip;
866	void __iomem *base;
867
868	pll_init = device_get_match_data(dev);
869	if (!pll_init && pdev->id_entry)
870		pll_init = (void *)pdev->id_entry->driver_data;
871
872	if (!pll_init) {
873		dev_err(dev, "unable to find driver data\n");
874		return -EINVAL;
875	}
876
877	cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
878
879	base = devm_platform_ioremap_resource(pdev, 0);
880	if (IS_ERR(base))
881		return PTR_ERR(base);
882
883	return pll_init(dev, base, cfgchip);
884}
885
886static struct platform_driver davinci_pll_driver = {
887	.probe		= davinci_pll_probe,
888	.driver		= {
889		.name		= "davinci-pll-clk",
890		.of_match_table	= davinci_pll_of_match,
891	},
892	.id_table	= davinci_pll_id_table,
893};
894
895static int __init davinci_pll_driver_init(void)
896{
897	return platform_driver_register(&davinci_pll_driver);
898}
899
900/* has to be postcore_initcall because PSC devices depend on PLL parent clocks */
901postcore_initcall(davinci_pll_driver_init);
902
903#ifdef CONFIG_DEBUG_FS
904#include <linux/debugfs.h>
905
906#define DEBUG_REG(n)	\
907{			\
908	.name	= #n,	\
909	.offset	= n,	\
910}
911
912static const struct debugfs_reg32 davinci_pll_regs[] = {
913	DEBUG_REG(REVID),
914	DEBUG_REG(PLLCTL),
915	DEBUG_REG(OCSEL),
916	DEBUG_REG(PLLSECCTL),
917	DEBUG_REG(PLLM),
918	DEBUG_REG(PREDIV),
919	DEBUG_REG(PLLDIV1),
920	DEBUG_REG(PLLDIV2),
921	DEBUG_REG(PLLDIV3),
922	DEBUG_REG(OSCDIV),
923	DEBUG_REG(POSTDIV),
924	DEBUG_REG(BPDIV),
925	DEBUG_REG(PLLCMD),
926	DEBUG_REG(PLLSTAT),
927	DEBUG_REG(ALNCTL),
928	DEBUG_REG(DCHANGE),
929	DEBUG_REG(CKEN),
930	DEBUG_REG(CKSTAT),
931	DEBUG_REG(SYSTAT),
932	DEBUG_REG(PLLDIV4),
933	DEBUG_REG(PLLDIV5),
934	DEBUG_REG(PLLDIV6),
935	DEBUG_REG(PLLDIV7),
936	DEBUG_REG(PLLDIV8),
937	DEBUG_REG(PLLDIV9),
938};
939
940static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
941{
942	struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
943	struct debugfs_regset32 *regset;
944
945	regset = kzalloc(sizeof(*regset), GFP_KERNEL);
946	if (!regset)
947		return;
948
949	regset->regs = davinci_pll_regs;
950	regset->nregs = ARRAY_SIZE(davinci_pll_regs);
951	regset->base = pll->base;
952
953	debugfs_create_regset32("registers", 0400, dentry, regset);
954}
955#endif