clk-wm831x.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * WM831x clock control
  4 *
  5 * Copyright 2011-2 Wolfson Microelectronics PLC.
  6 *
  7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  8 */
  9
 10#include <linux/clk-provider.h>
 11#include <linux/delay.h>
 12#include <linux/module.h>
 13#include <linux/slab.h>
 14#include <linux/platform_device.h>
 15#include <linux/mfd/wm831x/core.h>
 16
 17struct wm831x_clk {
 18	struct wm831x *wm831x;
 19	struct clk_hw xtal_hw;
 20	struct clk_hw fll_hw;
 21	struct clk_hw clkout_hw;
 22	bool xtal_ena;
 23};
 24
 25static int wm831x_xtal_is_prepared(struct clk_hw *hw)
 26{
 27	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
 28						  xtal_hw);
 29
 30	return clkdata->xtal_ena;
 31}
 32
 33static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw,
 34					     unsigned long parent_rate)
 35{
 36	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
 37						  xtal_hw);
 38
 39	if (clkdata->xtal_ena)
 40		return 32768;
 41	else
 42		return 0;
 43}
 44
 45static const struct clk_ops wm831x_xtal_ops = {
 46	.is_prepared = wm831x_xtal_is_prepared,
 47	.recalc_rate = wm831x_xtal_recalc_rate,
 48};
 49
 50static const struct clk_init_data wm831x_xtal_init = {
 51	.name = "xtal",
 52	.ops = &wm831x_xtal_ops,
 53};
 54
 55static const unsigned long wm831x_fll_auto_rates[] = {
 56	 2048000,
 57	11289600,
 58	12000000,
 59	12288000,
 60	19200000,
 61	22579600,
 62	24000000,
 63	24576000,
 64};
 65
 66static int wm831x_fll_is_prepared(struct clk_hw *hw)
 67{
 68	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
 69						  fll_hw);
 70	struct wm831x *wm831x = clkdata->wm831x;
 71	int ret;
 72
 73	ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1);
 74	if (ret < 0) {
 75		dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n",
 76			ret);
 77		return true;
 78	}
 79
 80	return (ret & WM831X_FLL_ENA) != 0;
 81}
 82
 83static int wm831x_fll_prepare(struct clk_hw *hw)
 84{
 85	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
 86						  fll_hw);
 87	struct wm831x *wm831x = clkdata->wm831x;
 88	int ret;
 89
 90	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1,
 91			      WM831X_FLL_ENA, WM831X_FLL_ENA);
 92	if (ret != 0)
 93		dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
 94
 95	/* wait 2-3 ms for new frequency taking effect */
 96	usleep_range(2000, 3000);
 97
 98	return ret;
 99}
100
101static void wm831x_fll_unprepare(struct clk_hw *hw)
102{
103	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
104						  fll_hw);
105	struct wm831x *wm831x = clkdata->wm831x;
106	int ret;
107
108	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, WM831X_FLL_ENA, 0);
109	if (ret != 0)
110		dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret);
111}
112
113static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
114					    unsigned long parent_rate)
115{
116	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
117						  fll_hw);
118	struct wm831x *wm831x = clkdata->wm831x;
119	int ret;
120
121	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
122	if (ret < 0) {
123		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
124			ret);
125		return 0;
126	}
127
128	if (ret & WM831X_FLL_AUTO)
129		return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK];
130
131	dev_err(wm831x->dev, "FLL only supported in AUTO mode\n");
132
133	return 0;
134}
135
136static int wm831x_fll_determine_rate(struct clk_hw *hw,
137				     struct clk_rate_request *req)
138{
139	int best = 0;
140	int i;
141
142	for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
143		if (abs(wm831x_fll_auto_rates[i] - req->rate) <
144		    abs(wm831x_fll_auto_rates[best] - req->rate))
145			best = i;
146
147	req->rate = wm831x_fll_auto_rates[best];
148
149	return 0;
150}
151
152static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate,
153			       unsigned long parent_rate)
154{
155	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
156						  fll_hw);
157	struct wm831x *wm831x = clkdata->wm831x;
158	int i;
159
160	for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
161		if (wm831x_fll_auto_rates[i] == rate)
162			break;
163	if (i == ARRAY_SIZE(wm831x_fll_auto_rates))
164		return -EINVAL;
165
166	if (wm831x_fll_is_prepared(hw))
167		return -EPERM;
168
169	return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2,
170			       WM831X_FLL_AUTO_FREQ_MASK, i);
171}
172
173static const char *wm831x_fll_parents[] = {
174	"xtal",
175	"clkin",
176};
177
178static u8 wm831x_fll_get_parent(struct clk_hw *hw)
179{
180	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
181						  fll_hw);
182	struct wm831x *wm831x = clkdata->wm831x;
183	int ret;
184
185	/* AUTO mode is always clocked from the crystal */
186	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
187	if (ret < 0) {
188		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
189			ret);
190		return 0;
191	}
192
193	if (ret & WM831X_FLL_AUTO)
194		return 0;
195
196	ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5);
197	if (ret < 0) {
198		dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n",
199			ret);
200		return 0;
201	}
202
203	switch (ret & WM831X_FLL_CLK_SRC_MASK) {
204	case 0:
205		return 0;
206	case 1:
207		return 1;
208	default:
209		dev_err(wm831x->dev, "Unsupported FLL clock source %d\n",
210			ret & WM831X_FLL_CLK_SRC_MASK);
211		return 0;
212	}
213}
214
215static const struct clk_ops wm831x_fll_ops = {
216	.is_prepared = wm831x_fll_is_prepared,
217	.prepare = wm831x_fll_prepare,
218	.unprepare = wm831x_fll_unprepare,
219	.determine_rate = wm831x_fll_determine_rate,
220	.recalc_rate = wm831x_fll_recalc_rate,
221	.set_rate = wm831x_fll_set_rate,
222	.get_parent = wm831x_fll_get_parent,
223};
224
225static const struct clk_init_data wm831x_fll_init = {
226	.name = "fll",
227	.ops = &wm831x_fll_ops,
228	.parent_names = wm831x_fll_parents,
229	.num_parents = ARRAY_SIZE(wm831x_fll_parents),
230	.flags = CLK_SET_RATE_GATE,
231};
232
233static int wm831x_clkout_is_prepared(struct clk_hw *hw)
234{
235	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
236						  clkout_hw);
237	struct wm831x *wm831x = clkdata->wm831x;
238	int ret;
239
240	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
241	if (ret < 0) {
242		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
243			ret);
244		return false;
245	}
246
247	return (ret & WM831X_CLKOUT_ENA) != 0;
248}
249
250static int wm831x_clkout_prepare(struct clk_hw *hw)
251{
252	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
253						  clkout_hw);
254	struct wm831x *wm831x = clkdata->wm831x;
255	int ret;
256
257	ret = wm831x_reg_unlock(wm831x);
258	if (ret != 0) {
259		dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
260		return ret;
261	}
262
263	ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
264			      WM831X_CLKOUT_ENA, WM831X_CLKOUT_ENA);
265	if (ret != 0)
266		dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret);
267
268	wm831x_reg_lock(wm831x);
269
270	return ret;
271}
272
273static void wm831x_clkout_unprepare(struct clk_hw *hw)
274{
275	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
276						  clkout_hw);
277	struct wm831x *wm831x = clkdata->wm831x;
278	int ret;
279
280	ret = wm831x_reg_unlock(wm831x);
281	if (ret != 0) {
282		dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
283		return;
284	}
285
286	ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
287			      WM831X_CLKOUT_ENA, 0);
288	if (ret != 0)
289		dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret);
290
291	wm831x_reg_lock(wm831x);
292}
293
294static const char *wm831x_clkout_parents[] = {
295	"fll",
296	"xtal",
297};
298
299static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
300{
301	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
302						  clkout_hw);
303	struct wm831x *wm831x = clkdata->wm831x;
304	int ret;
305
306	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
307	if (ret < 0) {
308		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
309			ret);
310		return 0;
311	}
312
313	if (ret & WM831X_CLKOUT_SRC)
314		return 1;
315	else
316		return 0;
317}
318
319static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
320{
321	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
322						  clkout_hw);
323	struct wm831x *wm831x = clkdata->wm831x;
324
325	return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
326			       WM831X_CLKOUT_SRC,
327			       parent << WM831X_CLKOUT_SRC_SHIFT);
328}
329
330static const struct clk_ops wm831x_clkout_ops = {
331	.is_prepared = wm831x_clkout_is_prepared,
332	.prepare = wm831x_clkout_prepare,
333	.unprepare = wm831x_clkout_unprepare,
334	.determine_rate = clk_hw_determine_rate_no_reparent,
335	.get_parent = wm831x_clkout_get_parent,
336	.set_parent = wm831x_clkout_set_parent,
337};
338
339static const struct clk_init_data wm831x_clkout_init = {
340	.name = "clkout",
341	.ops = &wm831x_clkout_ops,
342	.parent_names = wm831x_clkout_parents,
343	.num_parents = ARRAY_SIZE(wm831x_clkout_parents),
344	.flags = CLK_SET_RATE_PARENT,
345};
346
347static int wm831x_clk_probe(struct platform_device *pdev)
348{
349	struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
350	struct wm831x_clk *clkdata;
351	int ret;
352
353	clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
354	if (!clkdata)
355		return -ENOMEM;
356
357	clkdata->wm831x = wm831x;
358
359	/* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
360	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
361	if (ret < 0) {
362		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
363			ret);
364		return ret;
365	}
366	clkdata->xtal_ena = ret & WM831X_XTAL_ENA;
367
368	clkdata->xtal_hw.init = &wm831x_xtal_init;
369	ret = devm_clk_hw_register(&pdev->dev, &clkdata->xtal_hw);
370	if (ret)
371		return ret;
372
373	clkdata->fll_hw.init = &wm831x_fll_init;
374	ret = devm_clk_hw_register(&pdev->dev, &clkdata->fll_hw);
375	if (ret)
376		return ret;
377
378	clkdata->clkout_hw.init = &wm831x_clkout_init;
379	ret = devm_clk_hw_register(&pdev->dev, &clkdata->clkout_hw);
380	if (ret)
381		return ret;
382
383	platform_set_drvdata(pdev, clkdata);
384
385	return 0;
386}
387
388static struct platform_driver wm831x_clk_driver = {
389	.probe = wm831x_clk_probe,
390	.driver		= {
391		.name	= "wm831x-clk",
392	},
393};
394
395module_platform_driver(wm831x_clk_driver);
396
397/* Module information */
398MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
399MODULE_DESCRIPTION("WM831x clock driver");
400MODULE_LICENSE("GPL");
401MODULE_ALIAS("platform:wm831x-clk");