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clk-versaclock3.c
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linux-6.19.14/drivers/clk/clk-versaclock3.c
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Driver for Renesas Versaclock 3 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 7 8#include <linux/clk-provider.h> 9#include <linux/i2c.h> 10#include <linux/limits.h> 11#include <linux/module.h> 12#include <linux/regmap.h> 13 14#define NUM_CONFIG_REGISTERS 37 15 16#define VC3_GENERAL_CTR 0x0 17#define VC3_GENERAL_CTR_DIV1_SRC_SEL BIT(3) 18#define VC3_GENERAL_CTR_PLL3_REFIN_SEL BIT(2) 19 20#define VC3_PLL3_M_DIVIDER 0x3 21#define VC3_PLL3_M_DIV1 BIT(7) 22#define VC3_PLL3_M_DIV2 BIT(6) 23#define VC3_PLL3_M_DIV(n) ((n) & GENMASK(5, 0)) 24 25#define VC3_PLL3_N_DIVIDER 0x4 26#define VC3_PLL3_LOOP_FILTER_N_DIV_MSB 0x5 27 28#define VC3_PLL3_CHARGE_PUMP_CTRL 0x6 29#define VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL BIT(7) 30 31#define VC3_PLL1_CTRL_OUTDIV5 0x7 32#define VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER BIT(7) 33 34#define VC3_PLL1_M_DIVIDER 0x8 35#define VC3_PLL1_M_DIV1 BIT(7) 36#define VC3_PLL1_M_DIV2 BIT(6) 37#define VC3_PLL1_M_DIV(n) ((n) & GENMASK(5, 0)) 38 39#define VC3_PLL1_VCO_N_DIVIDER 0x9 40#define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0xa 41 42#define VC3_OUT_DIV1_DIV2_CTRL 0xf 43 44#define VC3_PLL2_FB_INT_DIV_MSB 0x10 45#define VC3_PLL2_FB_INT_DIV_LSB 0x11 46#define VC3_PLL2_FB_FRC_DIV_MSB 0x12 47#define VC3_PLL2_FB_FRC_DIV_LSB 0x13 48 49#define VC3_PLL2_M_DIVIDER 0x1a 50#define VC3_PLL2_MDIV_DOUBLER BIT(7) 51#define VC3_PLL2_M_DIV1 BIT(6) 52#define VC3_PLL2_M_DIV2 BIT(5) 53#define VC3_PLL2_M_DIV(n) ((n) & GENMASK(4, 0)) 54 55#define VC3_OUT_DIV3_DIV4_CTRL 0x1b 56 57#define VC3_PLL_OP_CTRL 0x1c 58#define VC3_PLL_OP_CTRL_PLL2_REFIN_SEL 6 59 60#define VC3_OUTPUT_CTR 0x1d 61#define VC3_OUTPUT_CTR_DIV4_SRC_SEL BIT(3) 62 63#define VC3_SE2_CTRL_REG0 0x1f 64#define VC3_SE2_CTRL_REG0_SE2_CLK_SEL BIT(6) 65 66#define VC3_SE3_DIFF1_CTRL_REG 0x21 67#define VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL BIT(6) 68 69#define VC3_DIFF1_CTRL_REG 0x22 70#define VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL BIT(7) 71 72#define VC3_DIFF2_CTRL_REG 0x23 73#define VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL BIT(7) 74 75#define VC3_SE1_DIV4_CTRL 0x24 76#define VC3_SE1_DIV4_CTRL_SE1_CLK_SEL BIT(3) 77 78#define VC3_PLL1_VCO_MIN 300000000UL 79#define VC3_PLL1_VCO_MAX 600000000UL 80 81#define VC3_PLL3_VCO_MIN 300000000UL 82#define VC3_PLL3_VCO_MAX 800000000UL 83 84#define VC3_2_POW_16 (U16_MAX + 1) 85#define VC3_DIV_MASK(width) ((1 << (width)) - 1) 86 87enum vc3_pfd_mux { 88 VC3_PFD2_MUX, 89 VC3_PFD3_MUX, 90}; 91 92enum vc3_pfd { 93 VC3_PFD1, 94 VC3_PFD2, 95 VC3_PFD3, 96}; 97 98enum vc3_pll { 99 VC3_PLL1, 100 VC3_PLL2, 101 VC3_PLL3, 102}; 103 104enum vc3_div_mux { 105 VC3_DIV1_MUX, 106 VC3_DIV3_MUX, 107 VC3_DIV4_MUX, 108}; 109 110enum vc3_div { 111 VC3_DIV1, 112 VC3_DIV2, 113 VC3_DIV3, 114 VC3_DIV4, 115 VC3_DIV5, 116}; 117 118enum vc3_clk { 119 VC3_REF, 120 VC3_SE1, 121 VC3_SE2, 122 VC3_SE3, 123 VC3_DIFF1, 124 VC3_DIFF2, 125}; 126 127enum vc3_clk_mux { 128 VC3_SE1_MUX = VC3_SE1 - 1, 129 VC3_SE2_MUX = VC3_SE2 - 1, 130 VC3_SE3_MUX = VC3_SE3 - 1, 131 VC3_DIFF1_MUX = VC3_DIFF1 - 1, 132 VC3_DIFF2_MUX = VC3_DIFF2 - 1, 133}; 134 135struct vc3_clk_data { 136 u8 offs; 137 u8 bitmsk; 138}; 139 140struct vc3_pfd_data { 141 u8 num; 142 u8 offs; 143 u8 mdiv1_bitmsk; 144 u8 mdiv2_bitmsk; 145}; 146 147struct vc3_vco { 148 unsigned long min; 149 unsigned long max; 150}; 151 152struct vc3_pll_data { 153 struct vc3_vco vco; 154 u8 num; 155 u8 int_div_msb_offs; 156 u8 int_div_lsb_offs; 157}; 158 159struct vc3_div_data { 160 const struct clk_div_table *table; 161 u8 offs; 162 u8 shift; 163 u8 width; 164 u8 flags; 165}; 166 167struct vc3_hw_data { 168 struct clk_hw hw; 169 struct regmap *regmap; 170 void *data; 171 172 u32 div_int; 173 u32 div_frc; 174}; 175 176struct vc3_hw_cfg { 177 struct vc3_vco pll2_vco; 178 u32 se2_clk_sel_msk; 179}; 180 181static const struct clk_div_table div1_divs[] = { 182 { .val = 0, .div = 1, }, { .val = 1, .div = 4, }, 183 { .val = 2, .div = 5, }, { .val = 3, .div = 6, }, 184 { .val = 4, .div = 2, }, { .val = 5, .div = 8, }, 185 { .val = 6, .div = 10, }, { .val = 7, .div = 12, }, 186 { .val = 8, .div = 4, }, { .val = 9, .div = 16, }, 187 { .val = 10, .div = 20, }, { .val = 11, .div = 24, }, 188 { .val = 12, .div = 8, }, { .val = 13, .div = 32, }, 189 { .val = 14, .div = 40, }, { .val = 15, .div = 48, }, 190 {} 191}; 192 193static const struct clk_div_table div245_divs[] = { 194 { .val = 0, .div = 1, }, { .val = 1, .div = 3, }, 195 { .val = 2, .div = 5, }, { .val = 3, .div = 10, }, 196 { .val = 4, .div = 2, }, { .val = 5, .div = 6, }, 197 { .val = 6, .div = 10, }, { .val = 7, .div = 20, }, 198 { .val = 8, .div = 4, }, { .val = 9, .div = 12, }, 199 { .val = 10, .div = 20, }, { .val = 11, .div = 40, }, 200 { .val = 12, .div = 5, }, { .val = 13, .div = 15, }, 201 { .val = 14, .div = 25, }, { .val = 15, .div = 50, }, 202 {} 203}; 204 205static const struct clk_div_table div3_divs[] = { 206 { .val = 0, .div = 1, }, { .val = 1, .div = 3, }, 207 { .val = 2, .div = 5, }, { .val = 3, .div = 10, }, 208 { .val = 4, .div = 2, }, { .val = 5, .div = 6, }, 209 { .val = 6, .div = 10, }, { .val = 7, .div = 20, }, 210 { .val = 8, .div = 4, }, { .val = 9, .div = 12, }, 211 { .val = 10, .div = 20, }, { .val = 11, .div = 40, }, 212 { .val = 12, .div = 8, }, { .val = 13, .div = 24, }, 213 { .val = 14, .div = 40, }, { .val = 15, .div = 80, }, 214 {} 215}; 216 217static struct clk_hw *clk_out[6]; 218 219static u8 vc3_pfd_mux_get_parent(struct clk_hw *hw) 220{ 221 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 222 const struct vc3_clk_data *pfd_mux = vc3->data; 223 u32 src; 224 225 regmap_read(vc3->regmap, pfd_mux->offs, &src); 226 227 return !!(src & pfd_mux->bitmsk); 228} 229 230static int vc3_pfd_mux_set_parent(struct clk_hw *hw, u8 index) 231{ 232 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 233 const struct vc3_clk_data *pfd_mux = vc3->data; 234 235 return regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk, 236 index ? pfd_mux->bitmsk : 0); 237} 238 239static const struct clk_ops vc3_pfd_mux_ops = { 240 .determine_rate = clk_hw_determine_rate_no_reparent, 241 .set_parent = vc3_pfd_mux_set_parent, 242 .get_parent = vc3_pfd_mux_get_parent, 243}; 244 245static unsigned long vc3_pfd_recalc_rate(struct clk_hw *hw, 246 unsigned long parent_rate) 247{ 248 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 249 const struct vc3_pfd_data *pfd = vc3->data; 250 unsigned int prediv, premul; 251 unsigned long rate; 252 u8 mdiv; 253 254 regmap_read(vc3->regmap, pfd->offs, &prediv); 255 if (pfd->num == VC3_PFD1) { 256 /* The bypass_prediv is set, PLL fed from Ref_in directly. */ 257 if (prediv & pfd->mdiv1_bitmsk) { 258 /* check doubler is set or not */ 259 regmap_read(vc3->regmap, VC3_PLL1_CTRL_OUTDIV5, &premul); 260 if (premul & VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER) 261 parent_rate *= 2; 262 return parent_rate; 263 } 264 mdiv = VC3_PLL1_M_DIV(prediv); 265 } else if (pfd->num == VC3_PFD2) { 266 /* The bypass_prediv is set, PLL fed from Ref_in directly. */ 267 if (prediv & pfd->mdiv1_bitmsk) { 268 regmap_read(vc3->regmap, VC3_PLL2_M_DIVIDER, &premul); 269 /* check doubler is set or not */ 270 if (premul & VC3_PLL2_MDIV_DOUBLER) 271 parent_rate *= 2; 272 return parent_rate; 273 } 274 275 mdiv = VC3_PLL2_M_DIV(prediv); 276 } else { 277 /* The bypass_prediv is set, PLL fed from Ref_in directly. */ 278 if (prediv & pfd->mdiv1_bitmsk) 279 return parent_rate; 280 281 mdiv = VC3_PLL3_M_DIV(prediv); 282 } 283 284 if (prediv & pfd->mdiv2_bitmsk) 285 rate = parent_rate / 2; 286 else 287 rate = parent_rate / mdiv; 288 289 return rate; 290} 291 292static int vc3_pfd_determine_rate(struct clk_hw *hw, 293 struct clk_rate_request *req) 294{ 295 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 296 const struct vc3_pfd_data *pfd = vc3->data; 297 unsigned long idiv; 298 299 /* PLL cannot operate with input clock above 50 MHz. */ 300 if (req->rate > 50000000) 301 return -EINVAL; 302 303 /* CLKIN within range of PLL input, feed directly to PLL. */ 304 if (req->best_parent_rate <= 50000000) { 305 req->rate = req->best_parent_rate; 306 307 return 0; 308 } 309 310 idiv = DIV_ROUND_UP(req->best_parent_rate, req->rate); 311 if (pfd->num == VC3_PFD1 || pfd->num == VC3_PFD3) { 312 if (idiv > 63) 313 return -EINVAL; 314 } else { 315 if (idiv > 31) 316 return -EINVAL; 317 } 318 319 req->rate = req->best_parent_rate / idiv; 320 321 return 0; 322} 323 324static int vc3_pfd_set_rate(struct clk_hw *hw, unsigned long rate, 325 unsigned long parent_rate) 326{ 327 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 328 const struct vc3_pfd_data *pfd = vc3->data; 329 unsigned long idiv; 330 u8 div; 331 332 /* CLKIN within range of PLL input, feed directly to PLL. */ 333 if (parent_rate <= 50000000) { 334 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk, 335 pfd->mdiv1_bitmsk); 336 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk, 0); 337 return 0; 338 } 339 340 idiv = DIV_ROUND_UP(parent_rate, rate); 341 /* We have dedicated div-2 predivider. */ 342 if (idiv == 2) { 343 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk, 344 pfd->mdiv2_bitmsk); 345 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk, 0); 346 } else { 347 if (pfd->num == VC3_PFD1) 348 div = VC3_PLL1_M_DIV(idiv); 349 else if (pfd->num == VC3_PFD2) 350 div = VC3_PLL2_M_DIV(idiv); 351 else 352 div = VC3_PLL3_M_DIV(idiv); 353 354 regmap_write(vc3->regmap, pfd->offs, div); 355 } 356 357 return 0; 358} 359 360static const struct clk_ops vc3_pfd_ops = { 361 .recalc_rate = vc3_pfd_recalc_rate, 362 .determine_rate = vc3_pfd_determine_rate, 363 .set_rate = vc3_pfd_set_rate, 364}; 365 366static unsigned long vc3_pll_recalc_rate(struct clk_hw *hw, 367 unsigned long parent_rate) 368{ 369 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 370 const struct vc3_pll_data *pll = vc3->data; 371 u32 div_int, div_frc, val; 372 unsigned long rate; 373 374 regmap_read(vc3->regmap, pll->int_div_msb_offs, &val); 375 div_int = (val & GENMASK(2, 0)) << 8; 376 regmap_read(vc3->regmap, pll->int_div_lsb_offs, &val); 377 div_int |= val; 378 379 if (pll->num == VC3_PLL2) { 380 regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB, &val); 381 div_frc = val << 8; 382 regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_LSB, &val); 383 div_frc |= val; 384 rate = (parent_rate * 385 (div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16); 386 } else { 387 rate = parent_rate * div_int; 388 } 389 390 return rate; 391} 392 393static int vc3_pll_determine_rate(struct clk_hw *hw, 394 struct clk_rate_request *req) 395{ 396 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 397 const struct vc3_pll_data *pll = vc3->data; 398 u64 div_frc; 399 400 if (req->rate < pll->vco.min) 401 req->rate = pll->vco.min; 402 if (req->rate > pll->vco.max) 403 req->rate = pll->vco.max; 404 405 vc3->div_int = req->rate / req->best_parent_rate; 406 407 if (pll->num == VC3_PLL2) { 408 if (vc3->div_int > 0x7ff) 409 req->rate = req->best_parent_rate * 0x7ff; 410 411 /* Determine best fractional part, which is 16 bit wide */ 412 div_frc = req->rate % req->best_parent_rate; 413 div_frc *= BIT(16) - 1; 414 415 vc3->div_frc = min_t(u64, 416 div64_ul(div_frc, req->best_parent_rate), 417 U16_MAX); 418 req->rate = (req->best_parent_rate * 419 (vc3->div_int * VC3_2_POW_16 + vc3->div_frc) / VC3_2_POW_16); 420 } else { 421 req->rate = req->best_parent_rate * vc3->div_int; 422 } 423 424 return 0; 425} 426 427static int vc3_pll_set_rate(struct clk_hw *hw, unsigned long rate, 428 unsigned long parent_rate) 429{ 430 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 431 const struct vc3_pll_data *pll = vc3->data; 432 u32 val; 433 434 regmap_read(vc3->regmap, pll->int_div_msb_offs, &val); 435 val = (val & 0xf8) | ((vc3->div_int >> 8) & 0x7); 436 regmap_write(vc3->regmap, pll->int_div_msb_offs, val); 437 regmap_write(vc3->regmap, pll->int_div_lsb_offs, vc3->div_int & 0xff); 438 439 if (pll->num == VC3_PLL2) { 440 regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB, 441 vc3->div_frc >> 8); 442 regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_LSB, 443 vc3->div_frc & 0xff); 444 } 445 446 return 0; 447} 448 449static const struct clk_ops vc3_pll_ops = { 450 .recalc_rate = vc3_pll_recalc_rate, 451 .determine_rate = vc3_pll_determine_rate, 452 .set_rate = vc3_pll_set_rate, 453}; 454 455static u8 vc3_div_mux_get_parent(struct clk_hw *hw) 456{ 457 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 458 const struct vc3_clk_data *div_mux = vc3->data; 459 u32 src; 460 461 regmap_read(vc3->regmap, div_mux->offs, &src); 462 463 return !!(src & div_mux->bitmsk); 464} 465 466static int vc3_div_mux_set_parent(struct clk_hw *hw, u8 index) 467{ 468 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 469 const struct vc3_clk_data *div_mux = vc3->data; 470 471 return regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk, 472 index ? div_mux->bitmsk : 0); 473} 474 475static const struct clk_ops vc3_div_mux_ops = { 476 .determine_rate = clk_hw_determine_rate_no_reparent, 477 .set_parent = vc3_div_mux_set_parent, 478 .get_parent = vc3_div_mux_get_parent, 479}; 480 481static unsigned int vc3_get_div(const struct clk_div_table *table, 482 unsigned int val, unsigned long flag) 483{ 484 const struct clk_div_table *clkt; 485 486 for (clkt = table; clkt->div; clkt++) 487 if (clkt->val == val) 488 return clkt->div; 489 490 return 1; 491} 492 493static unsigned long vc3_div_recalc_rate(struct clk_hw *hw, 494 unsigned long parent_rate) 495{ 496 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 497 const struct vc3_div_data *div_data = vc3->data; 498 unsigned int val; 499 500 regmap_read(vc3->regmap, div_data->offs, &val); 501 val >>= div_data->shift; 502 val &= VC3_DIV_MASK(div_data->width); 503 504 return divider_recalc_rate(hw, parent_rate, val, div_data->table, 505 div_data->flags, div_data->width); 506} 507 508static int vc3_div_determine_rate(struct clk_hw *hw, 509 struct clk_rate_request *req) 510{ 511 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 512 const struct vc3_div_data *div_data = vc3->data; 513 unsigned int bestdiv; 514 515 /* if read only, just return current value */ 516 if (div_data->flags & CLK_DIVIDER_READ_ONLY) { 517 regmap_read(vc3->regmap, div_data->offs, &bestdiv); 518 bestdiv >>= div_data->shift; 519 bestdiv &= VC3_DIV_MASK(div_data->width); 520 bestdiv = vc3_get_div(div_data->table, bestdiv, div_data->flags); 521 req->rate = DIV_ROUND_UP(req->best_parent_rate, bestdiv); 522 523 return 0; 524 } 525 526 return divider_determine_rate(hw, req, div_data->table, div_data->width, 527 div_data->flags); 528} 529 530static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate, 531 unsigned long parent_rate) 532{ 533 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 534 const struct vc3_div_data *div_data = vc3->data; 535 unsigned int value; 536 537 value = divider_get_val(rate, parent_rate, div_data->table, 538 div_data->width, div_data->flags); 539 return regmap_update_bits(vc3->regmap, div_data->offs, 540 VC3_DIV_MASK(div_data->width) << div_data->shift, 541 value << div_data->shift); 542} 543 544static const struct clk_ops vc3_div_ops = { 545 .recalc_rate = vc3_div_recalc_rate, 546 .determine_rate = vc3_div_determine_rate, 547 .set_rate = vc3_div_set_rate, 548}; 549 550static int vc3_clk_mux_determine_rate(struct clk_hw *hw, 551 struct clk_rate_request *req) 552{ 553 int frc; 554 555 if (clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT)) { 556 /* The below check is equivalent to (best_parent_rate/rate) */ 557 if (req->best_parent_rate >= req->rate) { 558 frc = DIV_ROUND_CLOSEST_ULL(req->best_parent_rate, 559 req->rate); 560 req->rate *= frc; 561 return clk_mux_determine_rate_flags(hw, req, 562 CLK_SET_RATE_PARENT); 563 } 564 } 565 566 return 0; 567} 568 569static u8 vc3_clk_mux_get_parent(struct clk_hw *hw) 570{ 571 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 572 const struct vc3_clk_data *clk_mux = vc3->data; 573 u32 val; 574 575 regmap_read(vc3->regmap, clk_mux->offs, &val); 576 577 return !!(val & clk_mux->bitmsk); 578} 579 580static int vc3_clk_mux_set_parent(struct clk_hw *hw, u8 index) 581{ 582 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 583 const struct vc3_clk_data *clk_mux = vc3->data; 584 585 return regmap_update_bits(vc3->regmap, clk_mux->offs, clk_mux->bitmsk, 586 index ? clk_mux->bitmsk : 0); 587} 588 589static const struct clk_ops vc3_clk_mux_ops = { 590 .determine_rate = vc3_clk_mux_determine_rate, 591 .set_parent = vc3_clk_mux_set_parent, 592 .get_parent = vc3_clk_mux_get_parent, 593}; 594 595static const struct regmap_config vc3_regmap_config = { 596 .reg_bits = 8, 597 .val_bits = 8, 598 .cache_type = REGCACHE_MAPLE, 599 .max_register = 0x24, 600}; 601 602static struct vc3_hw_data clk_div[5]; 603 604static const struct clk_parent_data pfd_mux_parent_data[] = { 605 { .index = 0, }, 606 { .hw = &clk_div[VC3_DIV2].hw } 607}; 608 609static struct vc3_hw_data clk_pfd_mux[] = { 610 [VC3_PFD2_MUX] = { 611 .data = &(struct vc3_clk_data) { 612 .offs = VC3_PLL_OP_CTRL, 613 .bitmsk = BIT(VC3_PLL_OP_CTRL_PLL2_REFIN_SEL) 614 }, 615 .hw.init = &(struct clk_init_data) { 616 .name = "pfd2_mux", 617 .ops = &vc3_pfd_mux_ops, 618 .parent_data = pfd_mux_parent_data, 619 .num_parents = 2, 620 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT 621 } 622 }, 623 [VC3_PFD3_MUX] = { 624 .data = &(struct vc3_clk_data) { 625 .offs = VC3_GENERAL_CTR, 626 .bitmsk = BIT(VC3_GENERAL_CTR_PLL3_REFIN_SEL) 627 }, 628 .hw.init = &(struct clk_init_data) { 629 .name = "pfd3_mux", 630 .ops = &vc3_pfd_mux_ops, 631 .parent_data = pfd_mux_parent_data, 632 .num_parents = 2, 633 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT 634 } 635 } 636}; 637 638static struct vc3_hw_data clk_pfd[] = { 639 [VC3_PFD1] = { 640 .data = &(struct vc3_pfd_data) { 641 .num = VC3_PFD1, 642 .offs = VC3_PLL1_M_DIVIDER, 643 .mdiv1_bitmsk = VC3_PLL1_M_DIV1, 644 .mdiv2_bitmsk = VC3_PLL1_M_DIV2 645 }, 646 .hw.init = &(struct clk_init_data) { 647 .name = "pfd1", 648 .ops = &vc3_pfd_ops, 649 .parent_data = &(const struct clk_parent_data) { 650 .index = 0 651 }, 652 .num_parents = 1, 653 .flags = CLK_SET_RATE_PARENT 654 } 655 }, 656 [VC3_PFD2] = { 657 .data = &(struct vc3_pfd_data) { 658 .num = VC3_PFD2, 659 .offs = VC3_PLL2_M_DIVIDER, 660 .mdiv1_bitmsk = VC3_PLL2_M_DIV1, 661 .mdiv2_bitmsk = VC3_PLL2_M_DIV2 662 }, 663 .hw.init = &(struct clk_init_data) { 664 .name = "pfd2", 665 .ops = &vc3_pfd_ops, 666 .parent_hws = (const struct clk_hw *[]) { 667 &clk_pfd_mux[VC3_PFD2_MUX].hw 668 }, 669 .num_parents = 1, 670 .flags = CLK_SET_RATE_PARENT 671 } 672 }, 673 [VC3_PFD3] = { 674 .data = &(struct vc3_pfd_data) { 675 .num = VC3_PFD3, 676 .offs = VC3_PLL3_M_DIVIDER, 677 .mdiv1_bitmsk = VC3_PLL3_M_DIV1, 678 .mdiv2_bitmsk = VC3_PLL3_M_DIV2 679 }, 680 .hw.init = &(struct clk_init_data) { 681 .name = "pfd3", 682 .ops = &vc3_pfd_ops, 683 .parent_hws = (const struct clk_hw *[]) { 684 &clk_pfd_mux[VC3_PFD3_MUX].hw 685 }, 686 .num_parents = 1, 687 .flags = CLK_SET_RATE_PARENT 688 } 689 } 690}; 691 692static struct vc3_hw_data clk_pll[] = { 693 [VC3_PLL1] = { 694 .data = &(struct vc3_pll_data) { 695 .num = VC3_PLL1, 696 .int_div_msb_offs = VC3_PLL1_LOOP_FILTER_N_DIV_MSB, 697 .int_div_lsb_offs = VC3_PLL1_VCO_N_DIVIDER, 698 .vco = { 699 .min = VC3_PLL1_VCO_MIN, 700 .max = VC3_PLL1_VCO_MAX 701 } 702 }, 703 .hw.init = &(struct clk_init_data) { 704 .name = "pll1", 705 .ops = &vc3_pll_ops, 706 .parent_hws = (const struct clk_hw *[]) { 707 &clk_pfd[VC3_PFD1].hw 708 }, 709 .num_parents = 1, 710 .flags = CLK_SET_RATE_PARENT 711 } 712 }, 713 [VC3_PLL2] = { 714 .data = &(struct vc3_pll_data) { 715 .num = VC3_PLL2, 716 .int_div_msb_offs = VC3_PLL2_FB_INT_DIV_MSB, 717 .int_div_lsb_offs = VC3_PLL2_FB_INT_DIV_LSB, 718 }, 719 .hw.init = &(struct clk_init_data) { 720 .name = "pll2", 721 .ops = &vc3_pll_ops, 722 .parent_hws = (const struct clk_hw *[]) { 723 &clk_pfd[VC3_PFD2].hw 724 }, 725 .num_parents = 1, 726 .flags = CLK_SET_RATE_PARENT 727 } 728 }, 729 [VC3_PLL3] = { 730 .data = &(struct vc3_pll_data) { 731 .num = VC3_PLL3, 732 .int_div_msb_offs = VC3_PLL3_LOOP_FILTER_N_DIV_MSB, 733 .int_div_lsb_offs = VC3_PLL3_N_DIVIDER, 734 .vco = { 735 .min = VC3_PLL3_VCO_MIN, 736 .max = VC3_PLL3_VCO_MAX 737 } 738 }, 739 .hw.init = &(struct clk_init_data) { 740 .name = "pll3", 741 .ops = &vc3_pll_ops, 742 .parent_hws = (const struct clk_hw *[]) { 743 &clk_pfd[VC3_PFD3].hw 744 }, 745 .num_parents = 1, 746 .flags = CLK_SET_RATE_PARENT 747 } 748 } 749}; 750 751static const struct clk_parent_data div_mux_parent_data[][2] = { 752 [VC3_DIV1_MUX] = { 753 { .hw = &clk_pll[VC3_PLL1].hw }, 754 { .index = 0 } 755 }, 756 [VC3_DIV3_MUX] = { 757 { .hw = &clk_pll[VC3_PLL2].hw }, 758 { .hw = &clk_pll[VC3_PLL3].hw } 759 }, 760 [VC3_DIV4_MUX] = { 761 { .hw = &clk_pll[VC3_PLL2].hw }, 762 { .index = 0 } 763 } 764}; 765 766static struct vc3_hw_data clk_div_mux[] = { 767 [VC3_DIV1_MUX] = { 768 .data = &(struct vc3_clk_data) { 769 .offs = VC3_GENERAL_CTR, 770 .bitmsk = VC3_GENERAL_CTR_DIV1_SRC_SEL 771 }, 772 .hw.init = &(struct clk_init_data) { 773 .name = "div1_mux", 774 .ops = &vc3_div_mux_ops, 775 .parent_data = div_mux_parent_data[VC3_DIV1_MUX], 776 .num_parents = 2, 777 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT 778 } 779 }, 780 [VC3_DIV3_MUX] = { 781 .data = &(struct vc3_clk_data) { 782 .offs = VC3_PLL3_CHARGE_PUMP_CTRL, 783 .bitmsk = VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL 784 }, 785 .hw.init = &(struct clk_init_data) { 786 .name = "div3_mux", 787 .ops = &vc3_div_mux_ops, 788 .parent_data = div_mux_parent_data[VC3_DIV3_MUX], 789 .num_parents = 2, 790 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT 791 } 792 }, 793 [VC3_DIV4_MUX] = { 794 .data = &(struct vc3_clk_data) { 795 .offs = VC3_OUTPUT_CTR, 796 .bitmsk = VC3_OUTPUT_CTR_DIV4_SRC_SEL 797 }, 798 .hw.init = &(struct clk_init_data) { 799 .name = "div4_mux", 800 .ops = &vc3_div_mux_ops, 801 .parent_data = div_mux_parent_data[VC3_DIV4_MUX], 802 .num_parents = 2, 803 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT 804 } 805 } 806}; 807 808static struct vc3_hw_data clk_div[] = { 809 [VC3_DIV1] = { 810 .data = &(struct vc3_div_data) { 811 .offs = VC3_OUT_DIV1_DIV2_CTRL, 812 .table = div1_divs, 813 .shift = 4, 814 .width = 4, 815 .flags = CLK_DIVIDER_READ_ONLY 816 }, 817 .hw.init = &(struct clk_init_data) { 818 .name = "div1", 819 .ops = &vc3_div_ops, 820 .parent_hws = (const struct clk_hw *[]) { 821 &clk_div_mux[VC3_DIV1_MUX].hw 822 }, 823 .num_parents = 1, 824 .flags = CLK_SET_RATE_PARENT 825 } 826 }, 827 [VC3_DIV2] = { 828 .data = &(struct vc3_div_data) { 829 .offs = VC3_OUT_DIV1_DIV2_CTRL, 830 .table = div245_divs, 831 .shift = 0, 832 .width = 4, 833 .flags = CLK_DIVIDER_READ_ONLY 834 }, 835 .hw.init = &(struct clk_init_data) { 836 .name = "div2", 837 .ops = &vc3_div_ops, 838 .parent_hws = (const struct clk_hw *[]) { 839 &clk_pll[VC3_PLL1].hw 840 }, 841 .num_parents = 1, 842 .flags = CLK_SET_RATE_PARENT 843 } 844 }, 845 [VC3_DIV3] = { 846 .data = &(struct vc3_div_data) { 847 .offs = VC3_OUT_DIV3_DIV4_CTRL, 848 .table = div3_divs, 849 .shift = 4, 850 .width = 4, 851 .flags = CLK_DIVIDER_READ_ONLY 852 }, 853 .hw.init = &(struct clk_init_data) { 854 .name = "div3", 855 .ops = &vc3_div_ops, 856 .parent_hws = (const struct clk_hw *[]) { 857 &clk_div_mux[VC3_DIV3_MUX].hw 858 }, 859 .num_parents = 1, 860 .flags = CLK_SET_RATE_PARENT 861 } 862 }, 863 [VC3_DIV4] = { 864 .data = &(struct vc3_div_data) { 865 .offs = VC3_OUT_DIV3_DIV4_CTRL, 866 .table = div245_divs, 867 .shift = 0, 868 .width = 4, 869 .flags = CLK_DIVIDER_READ_ONLY 870 }, 871 .hw.init = &(struct clk_init_data) { 872 .name = "div4", 873 .ops = &vc3_div_ops, 874 .parent_hws = (const struct clk_hw *[]) { 875 &clk_div_mux[VC3_DIV4_MUX].hw 876 }, 877 .num_parents = 1, 878 .flags = CLK_SET_RATE_PARENT 879 } 880 }, 881 [VC3_DIV5] = { 882 .data = &(struct vc3_div_data) { 883 .offs = VC3_PLL1_CTRL_OUTDIV5, 884 .table = div245_divs, 885 .shift = 0, 886 .width = 4, 887 .flags = CLK_DIVIDER_READ_ONLY 888 }, 889 .hw.init = &(struct clk_init_data) { 890 .name = "div5", 891 .ops = &vc3_div_ops, 892 .parent_hws = (const struct clk_hw *[]) { 893 &clk_pll[VC3_PLL3].hw 894 }, 895 .num_parents = 1, 896 .flags = CLK_SET_RATE_PARENT 897 } 898 } 899}; 900 901static struct vc3_hw_data clk_mux[] = { 902 [VC3_SE1_MUX] = { 903 .data = &(struct vc3_clk_data) { 904 .offs = VC3_SE1_DIV4_CTRL, 905 .bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL 906 }, 907 .hw.init = &(struct clk_init_data) { 908 .name = "se1_mux", 909 .ops = &vc3_clk_mux_ops, 910 .parent_hws = (const struct clk_hw *[]) { 911 &clk_div[VC3_DIV5].hw, 912 &clk_div[VC3_DIV4].hw 913 }, 914 .num_parents = 2, 915 .flags = CLK_SET_RATE_PARENT 916 } 917 }, 918 [VC3_SE2_MUX] = { 919 .data = &(struct vc3_clk_data) { 920 .offs = VC3_SE2_CTRL_REG0, 921 }, 922 .hw.init = &(struct clk_init_data) { 923 .name = "se2_mux", 924 .ops = &vc3_clk_mux_ops, 925 .parent_hws = (const struct clk_hw *[]) { 926 &clk_div[VC3_DIV5].hw, 927 &clk_div[VC3_DIV4].hw 928 }, 929 .num_parents = 2, 930 .flags = CLK_SET_RATE_PARENT 931 } 932 }, 933 [VC3_SE3_MUX] = { 934 .data = &(struct vc3_clk_data) { 935 .offs = VC3_SE3_DIFF1_CTRL_REG, 936 .bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL 937 }, 938 .hw.init = &(struct clk_init_data) { 939 .name = "se3_mux", 940 .ops = &vc3_clk_mux_ops, 941 .parent_hws = (const struct clk_hw *[]) { 942 &clk_div[VC3_DIV2].hw, 943 &clk_div[VC3_DIV4].hw 944 }, 945 .num_parents = 2, 946 .flags = CLK_SET_RATE_PARENT 947 } 948 }, 949 [VC3_DIFF1_MUX] = { 950 .data = &(struct vc3_clk_data) { 951 .offs = VC3_DIFF1_CTRL_REG, 952 .bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL 953 }, 954 .hw.init = &(struct clk_init_data) { 955 .name = "diff1_mux", 956 .ops = &vc3_clk_mux_ops, 957 .parent_hws = (const struct clk_hw *[]) { 958 &clk_div[VC3_DIV1].hw, 959 &clk_div[VC3_DIV3].hw 960 }, 961 .num_parents = 2, 962 .flags = CLK_SET_RATE_PARENT 963 } 964 }, 965 [VC3_DIFF2_MUX] = { 966 .data = &(struct vc3_clk_data) { 967 .offs = VC3_DIFF2_CTRL_REG, 968 .bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL 969 }, 970 .hw.init = &(struct clk_init_data) { 971 .name = "diff2_mux", 972 .ops = &vc3_clk_mux_ops, 973 .parent_hws = (const struct clk_hw *[]) { 974 &clk_div[VC3_DIV1].hw, 975 &clk_div[VC3_DIV3].hw 976 }, 977 .num_parents = 2, 978 .flags = CLK_SET_RATE_PARENT 979 } 980 } 981}; 982 983static struct clk_hw *vc3_of_clk_get(struct of_phandle_args *clkspec, 984 void *data) 985{ 986 unsigned int idx = clkspec->args[0]; 987 struct clk_hw **clkout_hw = data; 988 989 if (idx >= ARRAY_SIZE(clk_out)) { 990 pr_err("invalid clk index %u for provider %pOF\n", idx, clkspec->np); 991 return ERR_PTR(-EINVAL); 992 } 993 994 return clkout_hw[idx]; 995} 996 997static int vc3_probe(struct i2c_client *client) 998{ 999 struct device *dev = &client->dev; 1000 u8 settings[NUM_CONFIG_REGISTERS]; 1001 const struct vc3_hw_cfg *data; 1002 struct regmap *regmap; 1003 const char *name; 1004 int ret, i; 1005 1006 regmap = devm_regmap_init_i2c(client, &vc3_regmap_config); 1007 if (IS_ERR(regmap)) 1008 return dev_err_probe(dev, PTR_ERR(regmap), 1009 "failed to allocate register map\n"); 1010 1011 ret = of_property_read_u8_array(dev->of_node, "renesas,settings", 1012 settings, ARRAY_SIZE(settings)); 1013 if (!ret) { 1014 /* 1015 * A raw settings array was specified in the DT. Write the 1016 * settings to the device immediately. 1017 */ 1018 for (i = 0; i < NUM_CONFIG_REGISTERS; i++) { 1019 ret = regmap_write(regmap, i, settings[i]); 1020 if (ret) { 1021 dev_err(dev, "error writing to chip (%i)\n", ret); 1022 return ret; 1023 } 1024 } 1025 } else if (ret == -EOVERFLOW) { 1026 dev_err(&client->dev, "EOVERFLOW reg settings. ARRAY_SIZE: %zu\n", 1027 ARRAY_SIZE(settings)); 1028 return ret; 1029 } 1030 1031 /* Register pfd muxes */ 1032 for (i = 0; i < ARRAY_SIZE(clk_pfd_mux); i++) { 1033 clk_pfd_mux[i].regmap = regmap; 1034 ret = devm_clk_hw_register(dev, &clk_pfd_mux[i].hw); 1035 if (ret) 1036 return dev_err_probe(dev, ret, "%s failed\n", 1037 clk_pfd_mux[i].hw.init->name); 1038 } 1039 1040 /* Register pfd's */ 1041 for (i = 0; i < ARRAY_SIZE(clk_pfd); i++) { 1042 clk_pfd[i].regmap = regmap; 1043 ret = devm_clk_hw_register(dev, &clk_pfd[i].hw); 1044 if (ret) 1045 return dev_err_probe(dev, ret, "%s failed\n", 1046 clk_pfd[i].hw.init->name); 1047 } 1048 1049 data = i2c_get_match_data(client); 1050 1051 /* Register pll's */ 1052 for (i = 0; i < ARRAY_SIZE(clk_pll); i++) { 1053 clk_pll[i].regmap = regmap; 1054 if (i == VC3_PLL2) { 1055 struct vc3_pll_data *pll_data = clk_pll[i].data; 1056 1057 pll_data->vco = data->pll2_vco; 1058 } 1059 ret = devm_clk_hw_register(dev, &clk_pll[i].hw); 1060 if (ret) 1061 return dev_err_probe(dev, ret, "%s failed\n", 1062 clk_pll[i].hw.init->name); 1063 } 1064 1065 /* Register divider muxes */ 1066 for (i = 0; i < ARRAY_SIZE(clk_div_mux); i++) { 1067 clk_div_mux[i].regmap = regmap; 1068 ret = devm_clk_hw_register(dev, &clk_div_mux[i].hw); 1069 if (ret) 1070 return dev_err_probe(dev, ret, "%s failed\n", 1071 clk_div_mux[i].hw.init->name); 1072 } 1073 1074 /* Register dividers */ 1075 for (i = 0; i < ARRAY_SIZE(clk_div); i++) { 1076 clk_div[i].regmap = regmap; 1077 ret = devm_clk_hw_register(dev, &clk_div[i].hw); 1078 if (ret) 1079 return dev_err_probe(dev, ret, "%s failed\n", 1080 clk_div[i].hw.init->name); 1081 } 1082 1083 /* Register clk muxes */ 1084 for (i = 0; i < ARRAY_SIZE(clk_mux); i++) { 1085 clk_mux[i].regmap = regmap; 1086 if (i == VC3_SE2_MUX) { 1087 struct vc3_clk_data *clk_data = clk_mux[i].data; 1088 1089 clk_data->bitmsk = data->se2_clk_sel_msk; 1090 } 1091 ret = devm_clk_hw_register(dev, &clk_mux[i].hw); 1092 if (ret) 1093 return dev_err_probe(dev, ret, "%s failed\n", 1094 clk_mux[i].hw.init->name); 1095 } 1096 1097 /* Register clk outputs */ 1098 for (i = 0; i < ARRAY_SIZE(clk_out); i++) { 1099 switch (i) { 1100 case VC3_DIFF2: 1101 name = "diff2"; 1102 break; 1103 case VC3_DIFF1: 1104 name = "diff1"; 1105 break; 1106 case VC3_SE3: 1107 name = "se3"; 1108 break; 1109 case VC3_SE2: 1110 name = "se2"; 1111 break; 1112 case VC3_SE1: 1113 name = "se1"; 1114 break; 1115 case VC3_REF: 1116 name = "ref"; 1117 break; 1118 default: 1119 return dev_err_probe(dev, -EINVAL, "invalid clk output %d\n", i); 1120 } 1121 1122 if (i == VC3_REF) 1123 clk_out[i] = devm_clk_hw_register_fixed_factor_index(dev, 1124 name, 0, CLK_SET_RATE_PARENT, 1, 1); 1125 else 1126 clk_out[i] = devm_clk_hw_register_fixed_factor_parent_hw(dev, 1127 name, &clk_mux[i - 1].hw, CLK_SET_RATE_PARENT, 1, 1); 1128 1129 if (IS_ERR(clk_out[i])) 1130 return PTR_ERR(clk_out[i]); 1131 } 1132 1133 ret = devm_of_clk_add_hw_provider(dev, vc3_of_clk_get, clk_out); 1134 if (ret) 1135 return dev_err_probe(dev, ret, "unable to add clk provider\n"); 1136 1137 return ret; 1138} 1139 1140static const struct vc3_hw_cfg vc3_5p = { 1141 .pll2_vco = { .min = 400000000UL, .max = 1200000000UL }, 1142 .se2_clk_sel_msk = BIT(6), 1143}; 1144 1145static const struct vc3_hw_cfg vc3_5l = { 1146 .pll2_vco = { .min = 30000000UL, .max = 130000000UL }, 1147 .se2_clk_sel_msk = BIT(0), 1148}; 1149 1150static const struct of_device_id dev_ids[] = { 1151 { .compatible = "renesas,5p35023", .data = &vc3_5p }, 1152 { .compatible = "renesas,5l35023", .data = &vc3_5l }, 1153 { /* Sentinel */ } 1154}; 1155MODULE_DEVICE_TABLE(of, dev_ids); 1156 1157static struct i2c_driver vc3_driver = { 1158 .driver = { 1159 .name = "vc3", 1160 .of_match_table = of_match_ptr(dev_ids), 1161 }, 1162 .probe = vc3_probe, 1163}; 1164module_i2c_driver(vc3_driver); 1165 1166MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); 1167MODULE_DESCRIPTION("Renesas VersaClock 3 driver"); 1168MODULE_LICENSE("GPL");
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