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clk-sp7021.c
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linux-6.19.14/drivers/clk/clk-sp7021.c
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) Sunplus Technology Co., Ltd. 4 * All rights reserved. 5 */ 6#include <linux/module.h> 7#include <linux/clk-provider.h> 8#include <linux/of.h> 9#include <linux/bitfield.h> 10#include <linux/hw_bitfield.h> 11#include <linux/slab.h> 12#include <linux/io.h> 13#include <linux/err.h> 14#include <linux/platform_device.h> 15 16#include <dt-bindings/clock/sunplus,sp7021-clkc.h> 17 18/* special div_width values for PLLTV/PLLA */ 19#define DIV_TV 33 20#define DIV_A 34 21 22/* PLLTV parameters */ 23enum { 24 SEL_FRA, 25 SDM_MOD, 26 PH_SEL, 27 NFRA, 28 DIVR, 29 DIVN, 30 DIVM, 31 P_MAX 32}; 33 34#define MASK_SEL_FRA GENMASK(1, 1) 35#define MASK_SDM_MOD GENMASK(2, 2) 36#define MASK_PH_SEL GENMASK(4, 4) 37#define MASK_NFRA GENMASK(12, 6) 38#define MASK_DIVR GENMASK(8, 7) 39#define MASK_DIVN GENMASK(7, 0) 40#define MASK_DIVM GENMASK(14, 8) 41 42struct sp_pll { 43 struct clk_hw hw; 44 void __iomem *reg; 45 spinlock_t lock; /* lock for reg */ 46 int div_shift; 47 int div_width; 48 int pd_bit; /* power down bit idx */ 49 int bp_bit; /* bypass bit idx */ 50 unsigned long brate; /* base rate, TODO: replace brate with muldiv */ 51 u32 p[P_MAX]; /* for hold PLLTV/PLLA parameters */ 52}; 53 54#define to_sp_pll(_hw) container_of(_hw, struct sp_pll, hw) 55 56struct sp_clk_gate_info { 57 u16 reg; /* reg_index_shift */ 58 u16 ext_parent; /* parent is extclk */ 59}; 60 61static const struct sp_clk_gate_info sp_clk_gates[] = { 62 { 0x02 }, 63 { 0x05 }, 64 { 0x06 }, 65 { 0x07 }, 66 { 0x09 }, 67 { 0x0b, 1 }, 68 { 0x0f, 1 }, 69 { 0x14 }, 70 { 0x15 }, 71 { 0x16 }, 72 { 0x17 }, 73 { 0x18, 1 }, 74 { 0x19, 1 }, 75 { 0x1a, 1 }, 76 { 0x1b, 1 }, 77 { 0x1c, 1 }, 78 { 0x1d, 1 }, 79 { 0x1e }, 80 { 0x1f, 1 }, 81 { 0x20 }, 82 { 0x21 }, 83 { 0x22 }, 84 { 0x23 }, 85 { 0x24 }, 86 { 0x25 }, 87 { 0x26 }, 88 { 0x2a }, 89 { 0x2b }, 90 { 0x2d }, 91 { 0x2e }, 92 { 0x30 }, 93 { 0x31 }, 94 { 0x32 }, 95 { 0x33 }, 96 { 0x3d }, 97 { 0x3e }, 98 { 0x3f }, 99 { 0x42 }, 100 { 0x44 }, 101 { 0x4b }, 102 { 0x4c }, 103 { 0x4d }, 104 { 0x4e }, 105 { 0x4f }, 106 { 0x50 }, 107 { 0x55 }, 108 { 0x60 }, 109 { 0x61 }, 110 { 0x6a }, 111 { 0x73 }, 112 { 0x86 }, 113 { 0x8a }, 114 { 0x8b }, 115 { 0x8d }, 116 { 0x8e }, 117 { 0x8f }, 118 { 0x90 }, 119 { 0x92 }, 120 { 0x93 }, 121 { 0x95 }, 122 { 0x96 }, 123 { 0x97 }, 124 { 0x98 }, 125 { 0x99 }, 126}; 127 128#define _M 1000000UL 129#define F_27M (27 * _M) 130 131/*********************************** PLL_TV **********************************/ 132 133/* TODO: set proper FVCO range */ 134#define FVCO_MIN (100 * _M) 135#define FVCO_MAX (200 * _M) 136 137#define F_MIN (FVCO_MIN / 8) 138#define F_MAX (FVCO_MAX) 139 140static long plltv_integer_div(struct sp_pll *clk, unsigned long freq) 141{ 142 /* valid m values: 27M must be divisible by m */ 143 static const u32 m_table[] = { 144 1, 2, 3, 4, 5, 6, 8, 9, 10, 12, 15, 16, 18, 20, 24, 25, 27, 30, 32 145 }; 146 u32 m, n, r; 147 unsigned long fvco, nf; 148 long ret; 149 150 freq = clamp(freq, F_MIN, F_MAX); 151 152 /* DIVR 0~3 */ 153 for (r = 0; r <= 3; r++) { 154 fvco = freq << r; 155 if (fvco <= FVCO_MAX) 156 break; 157 } 158 159 /* DIVM */ 160 for (m = 0; m < ARRAY_SIZE(m_table); m++) { 161 nf = fvco * m_table[m]; 162 n = nf / F_27M; 163 if ((n * F_27M) == nf) 164 break; 165 } 166 if (m >= ARRAY_SIZE(m_table)) { 167 ret = -EINVAL; 168 goto err_not_found; 169 } 170 171 /* save parameters */ 172 clk->p[SEL_FRA] = 0; 173 clk->p[DIVR] = r; 174 clk->p[DIVN] = n; 175 clk->p[DIVM] = m_table[m]; 176 177 return freq; 178 179err_not_found: 180 pr_err("%s: %s freq:%lu not found a valid setting\n", 181 __func__, clk_hw_get_name(&clk->hw), freq); 182 183 return ret; 184} 185 186/* parameters for PLLTV fractional divider */ 187static const u32 pt[][5] = { 188 /* conventional fractional */ 189 { 190 1, /* factor */ 191 5, /* 5 * p0 (nint) */ 192 1, /* 1 * p0 */ 193 F_27M, /* F_27M / p0 */ 194 1, /* p0 / p2 */ 195 }, 196 /* phase rotation */ 197 { 198 10, /* factor */ 199 54, /* 5.4 * p0 (nint) */ 200 2, /* 0.2 * p0 */ 201 F_27M / 10, /* F_27M / p0 */ 202 5, /* p0 / p2 */ 203 }, 204}; 205 206static const u32 sdm_mod_vals[] = { 91, 55 }; 207 208static long plltv_fractional_div(struct sp_pll *clk, unsigned long freq) 209{ 210 u32 m, r; 211 u32 nint, nfra; 212 u32 df_quotient_min = 210000000; 213 u32 df_remainder_min = 0; 214 unsigned long fvco, nf, f, fout = 0; 215 int sdm, ph; 216 217 freq = clamp(freq, F_MIN, F_MAX); 218 219 /* DIVR 0~3 */ 220 for (r = 0; r <= 3; r++) { 221 fvco = freq << r; 222 if (fvco <= FVCO_MAX) 223 break; 224 } 225 f = F_27M >> r; 226 227 /* PH_SEL */ 228 for (ph = ARRAY_SIZE(pt) - 1; ph >= 0; ph--) { 229 const u32 *pp = pt[ph]; 230 231 /* SDM_MOD */ 232 for (sdm = 0; sdm < ARRAY_SIZE(sdm_mod_vals); sdm++) { 233 u32 mod = sdm_mod_vals[sdm]; 234 235 /* DIVM 1~32 */ 236 for (m = 1; m <= 32; m++) { 237 u32 df; /* diff freq */ 238 u32 df_quotient, df_remainder; 239 240 nf = fvco * m; 241 nint = nf / pp[3]; 242 243 if (nint < pp[1]) 244 continue; 245 if (nint > pp[1]) 246 break; 247 248 nfra = (((nf % pp[3]) * mod * pp[4]) + (F_27M / 2)) / F_27M; 249 if (nfra) { 250 u32 df0 = f * (nint + pp[2]) / pp[0]; 251 u32 df1 = f * (mod - nfra) / mod / pp[4]; 252 253 df = df0 - df1; 254 } else { 255 df = f * (nint) / pp[0]; 256 } 257 258 df_quotient = df / m; 259 df_remainder = ((df % m) * 1000) / m; 260 261 if (freq > df_quotient) { 262 df_quotient = freq - df_quotient - 1; 263 df_remainder = 1000 - df_remainder; 264 } else { 265 df_quotient = df_quotient - freq; 266 } 267 268 if (df_quotient_min > df_quotient || 269 (df_quotient_min == df_quotient && 270 df_remainder_min > df_remainder)) { 271 /* found a closer freq, save parameters */ 272 clk->p[SEL_FRA] = 1; 273 clk->p[SDM_MOD] = sdm; 274 clk->p[PH_SEL] = ph; 275 clk->p[NFRA] = nfra; 276 clk->p[DIVR] = r; 277 clk->p[DIVM] = m; 278 279 fout = df / m; 280 df_quotient_min = df_quotient; 281 df_remainder_min = df_remainder; 282 } 283 } 284 } 285 } 286 287 if (!fout) { 288 pr_err("%s: %s freq:%lu not found a valid setting\n", 289 __func__, clk_hw_get_name(&clk->hw), freq); 290 return -EINVAL; 291 } 292 293 return fout; 294} 295 296static long plltv_div(struct sp_pll *clk, unsigned long freq) 297{ 298 if (freq % 100) 299 return plltv_fractional_div(clk, freq); 300 301 return plltv_integer_div(clk, freq); 302} 303 304static int plltv_set_rate(struct sp_pll *clk) 305{ 306 unsigned long flags; 307 u32 r0, r1, r2; 308 309 r0 = BIT(clk->bp_bit + 16); 310 r0 |= FIELD_PREP_WM16(MASK_SEL_FRA, clk->p[SEL_FRA]); 311 r0 |= FIELD_PREP_WM16(MASK_SDM_MOD, clk->p[SDM_MOD]); 312 r0 |= FIELD_PREP_WM16(MASK_PH_SEL, clk->p[PH_SEL]); 313 r0 |= FIELD_PREP_WM16(MASK_NFRA, clk->p[NFRA]); 314 315 r1 = FIELD_PREP_WM16(MASK_DIVR, clk->p[DIVR]); 316 317 r2 = FIELD_PREP_WM16(MASK_DIVN, clk->p[DIVN] - 1); 318 r2 |= FIELD_PREP_WM16(MASK_DIVM, clk->p[DIVM] - 1); 319 320 spin_lock_irqsave(&clk->lock, flags); 321 writel(r0, clk->reg); 322 writel(r1, clk->reg + 4); 323 writel(r2, clk->reg + 8); 324 spin_unlock_irqrestore(&clk->lock, flags); 325 326 return 0; 327} 328 329/*********************************** PLL_A ***********************************/ 330 331/* from Q628_PLLs_REG_setting.xlsx */ 332static const struct { 333 u32 rate; 334 u32 regs[5]; 335} pa[] = { 336 { 337 .rate = 135475200, 338 .regs = { 339 0x4801, 340 0x02df, 341 0x248f, 342 0x0211, 343 0x33e9 344 } 345 }, 346 { 347 .rate = 147456000, 348 .regs = { 349 0x4801, 350 0x1adf, 351 0x2490, 352 0x0349, 353 0x33e9 354 } 355 }, 356 { 357 .rate = 196608000, 358 .regs = { 359 0x4801, 360 0x42ef, 361 0x2495, 362 0x01c6, 363 0x33e9 364 } 365 }, 366}; 367 368static int plla_set_rate(struct sp_pll *clk) 369{ 370 const u32 *pp = pa[clk->p[0]].regs; 371 unsigned long flags; 372 int i; 373 374 spin_lock_irqsave(&clk->lock, flags); 375 for (i = 0; i < ARRAY_SIZE(pa->regs); i++) 376 writel(0xffff0000 | pp[i], clk->reg + (i * 4)); 377 spin_unlock_irqrestore(&clk->lock, flags); 378 379 return 0; 380} 381 382static long plla_round_rate(struct sp_pll *clk, unsigned long rate) 383{ 384 int i = ARRAY_SIZE(pa); 385 386 while (--i) { 387 if (rate >= pa[i].rate) 388 break; 389 } 390 clk->p[0] = i; 391 392 return pa[i].rate; 393} 394 395/********************************** SP_PLL ***********************************/ 396 397static long sp_pll_calc_div(struct sp_pll *clk, unsigned long rate) 398{ 399 u32 fbdiv; 400 u32 max = 1 << clk->div_width; 401 402 fbdiv = DIV_ROUND_CLOSEST(rate, clk->brate); 403 if (fbdiv > max) 404 fbdiv = max; 405 406 return fbdiv; 407} 408 409static int sp_pll_determine_rate(struct clk_hw *hw, 410 struct clk_rate_request *req) 411{ 412 struct sp_pll *clk = to_sp_pll(hw); 413 long ret; 414 415 if (req->rate == req->best_parent_rate) { 416 ret = req->best_parent_rate; /* bypass */ 417 } else if (clk->div_width == DIV_A) { 418 ret = plla_round_rate(clk, req->rate); 419 } else if (clk->div_width == DIV_TV) { 420 ret = plltv_div(clk, req->rate); 421 if (ret < 0) 422 ret = req->best_parent_rate; 423 } else { 424 ret = sp_pll_calc_div(clk, req->rate) * clk->brate; 425 } 426 427 req->rate = ret; 428 429 return 0; 430} 431 432static unsigned long sp_pll_recalc_rate(struct clk_hw *hw, 433 unsigned long prate) 434{ 435 struct sp_pll *clk = to_sp_pll(hw); 436 u32 reg = readl(clk->reg); 437 unsigned long ret; 438 439 if (reg & BIT(clk->bp_bit)) { 440 ret = prate; /* bypass */ 441 } else if (clk->div_width == DIV_A) { 442 ret = pa[clk->p[0]].rate; 443 } else if (clk->div_width == DIV_TV) { 444 u32 m, r, reg2; 445 446 r = FIELD_GET(MASK_DIVR, readl(clk->reg + 4)); 447 reg2 = readl(clk->reg + 8); 448 m = FIELD_GET(MASK_DIVM, reg2) + 1; 449 450 if (reg & MASK_SEL_FRA) { 451 /* fractional divider */ 452 u32 sdm = FIELD_GET(MASK_SDM_MOD, reg); 453 u32 ph = FIELD_GET(MASK_PH_SEL, reg); 454 u32 nfra = FIELD_GET(MASK_NFRA, reg); 455 const u32 *pp = pt[ph]; 456 unsigned long r0, r1; 457 458 ret = prate >> r; 459 r0 = ret * (pp[1] + pp[2]) / pp[0]; 460 r1 = ret * (sdm_mod_vals[sdm] - nfra) / sdm_mod_vals[sdm] / pp[4]; 461 ret = (r0 - r1) / m; 462 } else { 463 /* integer divider */ 464 u32 n = FIELD_GET(MASK_DIVN, reg2) + 1; 465 466 ret = (prate / m * n) >> r; 467 } 468 } else { 469 u32 fbdiv = ((reg >> clk->div_shift) & ((1 << clk->div_width) - 1)) + 1; 470 471 ret = clk->brate * fbdiv; 472 } 473 474 return ret; 475} 476 477static int sp_pll_set_rate(struct clk_hw *hw, unsigned long rate, 478 unsigned long prate) 479{ 480 struct sp_pll *clk = to_sp_pll(hw); 481 unsigned long flags; 482 u32 reg; 483 484 reg = BIT(clk->bp_bit + 16); /* HIWORD_MASK */ 485 486 if (rate == prate) { 487 reg |= BIT(clk->bp_bit); /* bypass */ 488 } else if (clk->div_width == DIV_A) { 489 return plla_set_rate(clk); 490 } else if (clk->div_width == DIV_TV) { 491 return plltv_set_rate(clk); 492 } else if (clk->div_width) { 493 u32 fbdiv = sp_pll_calc_div(clk, rate); 494 u32 mask = GENMASK(clk->div_shift + clk->div_width - 1, clk->div_shift); 495 496 reg |= mask << 16; 497 reg |= ((fbdiv - 1) << clk->div_shift) & mask; 498 } 499 500 spin_lock_irqsave(&clk->lock, flags); 501 writel(reg, clk->reg); 502 spin_unlock_irqrestore(&clk->lock, flags); 503 504 return 0; 505} 506 507static int sp_pll_enable(struct clk_hw *hw) 508{ 509 struct sp_pll *clk = to_sp_pll(hw); 510 511 writel(BIT(clk->pd_bit + 16) | BIT(clk->pd_bit), clk->reg); 512 513 return 0; 514} 515 516static void sp_pll_disable(struct clk_hw *hw) 517{ 518 struct sp_pll *clk = to_sp_pll(hw); 519 520 writel(BIT(clk->pd_bit + 16), clk->reg); 521} 522 523static int sp_pll_is_enabled(struct clk_hw *hw) 524{ 525 struct sp_pll *clk = to_sp_pll(hw); 526 527 return readl(clk->reg) & BIT(clk->pd_bit); 528} 529 530static const struct clk_ops sp_pll_ops = { 531 .enable = sp_pll_enable, 532 .disable = sp_pll_disable, 533 .is_enabled = sp_pll_is_enabled, 534 .determine_rate = sp_pll_determine_rate, 535 .recalc_rate = sp_pll_recalc_rate, 536 .set_rate = sp_pll_set_rate 537}; 538 539static const struct clk_ops sp_pll_sub_ops = { 540 .enable = sp_pll_enable, 541 .disable = sp_pll_disable, 542 .is_enabled = sp_pll_is_enabled, 543 .recalc_rate = sp_pll_recalc_rate, 544}; 545 546static struct clk_hw *sp_pll_register(struct device *dev, const char *name, 547 const struct clk_parent_data *parent_data, 548 void __iomem *reg, int pd_bit, int bp_bit, 549 unsigned long brate, int shift, int width, 550 unsigned long flags) 551{ 552 struct sp_pll *pll; 553 struct clk_hw *hw; 554 struct clk_init_data initd = { 555 .name = name, 556 .parent_data = parent_data, 557 .ops = (bp_bit >= 0) ? &sp_pll_ops : &sp_pll_sub_ops, 558 .num_parents = 1, 559 .flags = flags, 560 }; 561 int ret; 562 563 pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); 564 if (!pll) 565 return ERR_PTR(-ENOMEM); 566 567 pll->hw.init = &initd; 568 pll->reg = reg; 569 pll->pd_bit = pd_bit; 570 pll->bp_bit = bp_bit; 571 pll->brate = brate; 572 pll->div_shift = shift; 573 pll->div_width = width; 574 spin_lock_init(&pll->lock); 575 576 hw = &pll->hw; 577 ret = devm_clk_hw_register(dev, hw); 578 if (ret) 579 return ERR_PTR(ret); 580 581 return hw; 582} 583 584#define PLLA_CTL (pll_base + 0x1c) 585#define PLLE_CTL (pll_base + 0x30) 586#define PLLF_CTL (pll_base + 0x34) 587#define PLLTV_CTL (pll_base + 0x38) 588 589static int sp7021_clk_probe(struct platform_device *pdev) 590{ 591 static const u32 sp_clken[] = { 592 0x67ef, 0x03ff, 0xff03, 0xfff0, 0x0004, /* G0.1~5 */ 593 0x0000, 0x8000, 0xffff, 0x0040, 0x0000, /* G0.6~10 */ 594 }; 595 static struct clk_parent_data pd_ext, pd_sys, pd_e; 596 struct device *dev = &pdev->dev; 597 void __iomem *clk_base, *pll_base, *sys_base; 598 struct clk_hw_onecell_data *clk_data; 599 struct clk_hw **hws; 600 int i; 601 602 clk_base = devm_platform_ioremap_resource(pdev, 0); 603 if (IS_ERR(clk_base)) 604 return PTR_ERR(clk_base); 605 pll_base = devm_platform_ioremap_resource(pdev, 1); 606 if (IS_ERR(pll_base)) 607 return PTR_ERR(pll_base); 608 sys_base = devm_platform_ioremap_resource(pdev, 2); 609 if (IS_ERR(sys_base)) 610 return PTR_ERR(sys_base); 611 612 /* enable default clks */ 613 for (i = 0; i < ARRAY_SIZE(sp_clken); i++) 614 writel((sp_clken[i] << 16) | sp_clken[i], clk_base + i * 4); 615 616 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, CLK_MAX), 617 GFP_KERNEL); 618 if (!clk_data) 619 return -ENOMEM; 620 clk_data->num = CLK_MAX; 621 622 hws = clk_data->hws; 623 pd_ext.index = 0; 624 625 /* PLLs */ 626 hws[PLL_A] = sp_pll_register(dev, "plla", &pd_ext, PLLA_CTL, 627 11, 12, 27000000, 0, DIV_A, 0); 628 if (IS_ERR(hws[PLL_A])) 629 return PTR_ERR(hws[PLL_A]); 630 631 hws[PLL_E] = sp_pll_register(dev, "plle", &pd_ext, PLLE_CTL, 632 6, 2, 50000000, 0, 0, 0); 633 if (IS_ERR(hws[PLL_E])) 634 return PTR_ERR(hws[PLL_E]); 635 pd_e.hw = hws[PLL_E]; 636 hws[PLL_E_2P5] = sp_pll_register(dev, "plle_2p5", &pd_e, PLLE_CTL, 637 13, -1, 2500000, 0, 0, 0); 638 if (IS_ERR(hws[PLL_E_2P5])) 639 return PTR_ERR(hws[PLL_E_2P5]); 640 hws[PLL_E_25] = sp_pll_register(dev, "plle_25", &pd_e, PLLE_CTL, 641 12, -1, 25000000, 0, 0, 0); 642 if (IS_ERR(hws[PLL_E_25])) 643 return PTR_ERR(hws[PLL_E_25]); 644 hws[PLL_E_112P5] = sp_pll_register(dev, "plle_112p5", &pd_e, PLLE_CTL, 645 11, -1, 112500000, 0, 0, 0); 646 if (IS_ERR(hws[PLL_E_112P5])) 647 return PTR_ERR(hws[PLL_E_112P5]); 648 649 hws[PLL_F] = sp_pll_register(dev, "pllf", &pd_ext, PLLF_CTL, 650 0, 10, 13500000, 1, 4, 0); 651 if (IS_ERR(hws[PLL_F])) 652 return PTR_ERR(hws[PLL_F]); 653 654 hws[PLL_TV] = sp_pll_register(dev, "plltv", &pd_ext, PLLTV_CTL, 655 0, 15, 27000000, 0, DIV_TV, 0); 656 if (IS_ERR(hws[PLL_TV])) 657 return PTR_ERR(hws[PLL_TV]); 658 hws[PLL_TV_A] = devm_clk_hw_register_divider(dev, "plltv_a", "plltv", 0, 659 PLLTV_CTL + 4, 5, 1, 660 CLK_DIVIDER_POWER_OF_TWO, 661 &to_sp_pll(hws[PLL_TV])->lock); 662 if (IS_ERR(hws[PLL_TV_A])) 663 return PTR_ERR(hws[PLL_TV_A]); 664 665 /* system clock, should not be disabled */ 666 hws[PLL_SYS] = sp_pll_register(dev, "pllsys", &pd_ext, sys_base, 667 10, 9, 13500000, 0, 4, CLK_IS_CRITICAL); 668 if (IS_ERR(hws[PLL_SYS])) 669 return PTR_ERR(hws[PLL_SYS]); 670 pd_sys.hw = hws[PLL_SYS]; 671 672 /* gates */ 673 for (i = 0; i < ARRAY_SIZE(sp_clk_gates); i++) { 674 char name[10]; 675 u32 j = sp_clk_gates[i].reg; 676 struct clk_parent_data *pd = sp_clk_gates[i].ext_parent ? &pd_ext : &pd_sys; 677 678 sprintf(name, "%02d_0x%02x", i, j); 679 hws[i] = devm_clk_hw_register_gate_parent_data(dev, name, pd, 0, 680 clk_base + (j >> 4) * 4, 681 j & 0x0f, 682 CLK_GATE_HIWORD_MASK, 683 NULL); 684 if (IS_ERR(hws[i])) 685 return PTR_ERR(hws[i]); 686 } 687 688 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); 689} 690 691static const struct of_device_id sp7021_clk_dt_ids[] = { 692 { .compatible = "sunplus,sp7021-clkc" }, 693 { } 694}; 695MODULE_DEVICE_TABLE(of, sp7021_clk_dt_ids); 696 697static struct platform_driver sp7021_clk_driver = { 698 .probe = sp7021_clk_probe, 699 .driver = { 700 .name = "sp7021-clk", 701 .of_match_table = sp7021_clk_dt_ids, 702 }, 703}; 704module_platform_driver(sp7021_clk_driver); 705 706MODULE_AUTHOR("Sunplus Technology"); 707MODULE_LICENSE("GPL"); 708MODULE_DESCRIPTION("Clock driver for Sunplus SP7021 SoC");
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