clk-si521xx.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Driver for Skyworks Si521xx PCIe clock generator driver
  4 *
  5 * The following series can be supported:
  6 *   - Si52144 - 4x DIFF
  7 *   - Si52146 - 6x DIFF
  8 *   - Si52147 - 9x DIFF
  9 * Currently tested:
 10 *   - Si52144
 11 *
 12 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
 13 */
 14
 15#include <linux/bitfield.h>
 16#include <linux/bitrev.h>
 17#include <linux/clk-provider.h>
 18#include <linux/i2c.h>
 19#include <linux/mod_devicetable.h>
 20#include <linux/module.h>
 21#include <linux/of.h>
 22#include <linux/regmap.h>
 23
 24/* OE1 and OE2 register */
 25#define SI521XX_REG_OE(n)			(((n) & 0x1) + 1)
 26#define SI521XX_REG_ID				0x3
 27#define SI521XX_REG_ID_PROG			GENMASK(7, 4)
 28#define SI521XX_REG_ID_VENDOR			GENMASK(3, 0)
 29#define SI521XX_REG_BC				0x4
 30#define SI521XX_REG_DA				0x5
 31#define SI521XX_REG_DA_AMP_SEL			BIT(7)
 32#define SI521XX_REG_DA_AMP_MASK			GENMASK(6, 4)
 33#define SI521XX_REG_DA_AMP_MIN			300000
 34#define SI521XX_REG_DA_AMP_DEFAULT		800000
 35#define SI521XX_REG_DA_AMP_MAX			1000000
 36#define SI521XX_REG_DA_AMP_STEP			100000
 37#define SI521XX_REG_DA_AMP(UV)			\
 38	FIELD_PREP(SI521XX_REG_DA_AMP_MASK,	\
 39		   ((UV) - SI521XX_REG_DA_AMP_MIN) / SI521XX_REG_DA_AMP_STEP)
 40#define SI521XX_REG_DA_UNKNOWN			BIT(3)	/* Always set */
 41
 42/* Count of populated OE bits in control register ref, 1 and 2 */
 43#define SI521XX_OE_MAP(cr1, cr2)	(((cr2) << 8) | (cr1))
 44#define SI521XX_OE_MAP_GET_OE(oe, map)	(((map) >> (((oe) - 1) * 8)) & 0xff)
 45
 46#define SI521XX_DIFF_MULT	4
 47#define SI521XX_DIFF_DIV	1
 48
 49/* Supported Skyworks Si521xx models. */
 50enum si521xx_model {
 51	SI52144 = 0x44,
 52	SI52146 = 0x46,
 53	SI52147 = 0x47,
 54};
 55
 56struct si521xx;
 57
 58struct si_clk {
 59	struct clk_hw		hw;
 60	struct si521xx		*si;
 61	u8			reg;
 62	u8			bit;
 63};
 64
 65struct si521xx {
 66	struct i2c_client	*client;
 67	struct regmap		*regmap;
 68	struct si_clk		clk_dif[9];
 69	u16			chip_info;
 70	u8			pll_amplitude;
 71};
 72
 73/*
 74 * Si521xx i2c regmap
 75 */
 76static const struct regmap_range si521xx_readable_ranges[] = {
 77	regmap_reg_range(SI521XX_REG_OE(0), SI521XX_REG_DA),
 78};
 79
 80static const struct regmap_access_table si521xx_readable_table = {
 81	.yes_ranges = si521xx_readable_ranges,
 82	.n_yes_ranges = ARRAY_SIZE(si521xx_readable_ranges),
 83};
 84
 85static const struct regmap_range si521xx_writeable_ranges[] = {
 86	regmap_reg_range(SI521XX_REG_OE(0), SI521XX_REG_OE(1)),
 87	regmap_reg_range(SI521XX_REG_BC, SI521XX_REG_DA),
 88};
 89
 90static const struct regmap_access_table si521xx_writeable_table = {
 91	.yes_ranges = si521xx_writeable_ranges,
 92	.n_yes_ranges = ARRAY_SIZE(si521xx_writeable_ranges),
 93};
 94
 95static int si521xx_regmap_i2c_write(void *context, unsigned int reg,
 96				    unsigned int val)
 97{
 98	struct i2c_client *i2c = context;
 99	const u8 data[2] = { reg, val };
100	const int count = ARRAY_SIZE(data);
101	int ret;
102
103	ret = i2c_master_send(i2c, data, count);
104	if (ret == count)
105		return 0;
106	else if (ret < 0)
107		return ret;
108	else
109		return -EIO;
110}
111
112static int si521xx_regmap_i2c_read(void *context, unsigned int reg,
113				   unsigned int *val)
114{
115	struct i2c_client *i2c = context;
116	struct i2c_msg xfer[2];
117	u8 txdata = reg;
118	u8 rxdata[2];
119	int ret;
120
121	xfer[0].addr = i2c->addr;
122	xfer[0].flags = 0;
123	xfer[0].len = 1;
124	xfer[0].buf = (void *)&txdata;
125
126	xfer[1].addr = i2c->addr;
127	xfer[1].flags = I2C_M_RD;
128	xfer[1].len = 2;
129	xfer[1].buf = (void *)rxdata;
130
131	ret = i2c_transfer(i2c->adapter, xfer, 2);
132	if (ret < 0)
133		return ret;
134	if (ret != 2)
135		return -EIO;
136
137	/*
138	 * Byte 0 is transfer length, which is always 1 due
139	 * to BCP register programming to 1 in si521xx_probe(),
140	 * ignore it and use data from Byte 1.
141	 */
142	*val = rxdata[1];
143	return 0;
144}
145
146static const struct regmap_config si521xx_regmap_config = {
147	.reg_bits = 8,
148	.val_bits = 8,
149	.cache_type = REGCACHE_FLAT,
150	.max_register = SI521XX_REG_DA,
151	.rd_table = &si521xx_readable_table,
152	.wr_table = &si521xx_writeable_table,
153	.reg_write = si521xx_regmap_i2c_write,
154	.reg_read = si521xx_regmap_i2c_read,
155};
156
157static unsigned long si521xx_diff_recalc_rate(struct clk_hw *hw,
158					      unsigned long parent_rate)
159{
160	unsigned long long rate;
161
162	rate = (unsigned long long)parent_rate * SI521XX_DIFF_MULT;
163	do_div(rate, SI521XX_DIFF_DIV);
164	return (unsigned long)rate;
165}
166
167static int si521xx_diff_determine_rate(struct clk_hw *hw,
168				       struct clk_rate_request *req)
169{
170	unsigned long best_parent;
171
172	best_parent = (req->rate / SI521XX_DIFF_MULT) * SI521XX_DIFF_DIV;
173	req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
174
175	req->rate = (req->best_parent_rate / SI521XX_DIFF_DIV) * SI521XX_DIFF_MULT;
176
177	return 0;
178}
179
180static int si521xx_diff_set_rate(struct clk_hw *hw, unsigned long rate,
181				 unsigned long parent_rate)
182{
183	/*
184	 * We must report success but we can do so unconditionally because
185	 * si521xx_diff_round_rate returns values that ensure this call is a
186	 * nop.
187	 */
188
189	return 0;
190}
191
192#define to_si521xx_clk(_hw) container_of(_hw, struct si_clk, hw)
193
194static int si521xx_diff_prepare(struct clk_hw *hw)
195{
196	struct si_clk *si_clk = to_si521xx_clk(hw);
197	struct si521xx *si = si_clk->si;
198
199	regmap_set_bits(si->regmap, SI521XX_REG_OE(si_clk->reg), si_clk->bit);
200
201	return 0;
202}
203
204static void si521xx_diff_unprepare(struct clk_hw *hw)
205{
206	struct si_clk *si_clk = to_si521xx_clk(hw);
207	struct si521xx *si = si_clk->si;
208
209	regmap_clear_bits(si->regmap, SI521XX_REG_OE(si_clk->reg), si_clk->bit);
210}
211
212static const struct clk_ops si521xx_diff_clk_ops = {
213	.determine_rate = si521xx_diff_determine_rate,
214	.set_rate	= si521xx_diff_set_rate,
215	.recalc_rate	= si521xx_diff_recalc_rate,
216	.prepare	= si521xx_diff_prepare,
217	.unprepare	= si521xx_diff_unprepare,
218};
219
220static int si521xx_get_common_config(struct si521xx *si)
221{
222	struct i2c_client *client = si->client;
223	struct device_node *np = client->dev.of_node;
224	unsigned int amp;
225	int ret;
226
227	/* Set defaults */
228	si->pll_amplitude = SI521XX_REG_DA_AMP(SI521XX_REG_DA_AMP_DEFAULT);
229
230	/* Output clock amplitude */
231	ret = of_property_read_u32(np, "skyworks,out-amplitude-microvolt",
232				   &amp);
233	if (!ret) {
234		if (amp < SI521XX_REG_DA_AMP_MIN || amp > SI521XX_REG_DA_AMP_MAX ||
235		    amp % SI521XX_REG_DA_AMP_STEP) {
236			return dev_err_probe(&client->dev, -EINVAL,
237					     "Invalid skyworks,out-amplitude-microvolt value\n");
238		}
239		si->pll_amplitude = SI521XX_REG_DA_AMP(amp);
240	}
241
242	return 0;
243}
244
245static void si521xx_update_config(struct si521xx *si)
246{
247	/* If amplitude is non-default, update it. */
248	if (si->pll_amplitude == SI521XX_REG_DA_AMP(SI521XX_REG_DA_AMP_DEFAULT))
249		return;
250
251	regmap_update_bits(si->regmap, SI521XX_REG_DA,
252			   SI521XX_REG_DA_AMP_MASK, si->pll_amplitude);
253}
254
255static void si521xx_diff_idx_to_reg_bit(const u16 chip_info, const int idx,
256					struct si_clk *clk)
257{
258	unsigned long mask;
259	int oe, b, ctr = 0;
260
261	for (oe = 1; oe <= 2; oe++) {
262		mask = bitrev8(SI521XX_OE_MAP_GET_OE(oe, chip_info));
263		for_each_set_bit(b, &mask, 8) {
264			if (ctr++ != idx)
265				continue;
266			clk->reg = SI521XX_REG_OE(oe);
267			clk->bit = 7 - b;
268			return;
269		}
270	}
271}
272
273static struct clk_hw *
274si521xx_of_clk_get(struct of_phandle_args *clkspec, void *data)
275{
276	struct si521xx *si = data;
277	unsigned int idx = clkspec->args[0];
278
279	return &si->clk_dif[idx].hw;
280}
281
282static int si521xx_probe(struct i2c_client *client)
283{
284	const u16 chip_info = (u16)(uintptr_t)i2c_get_match_data(client);
285	const struct clk_parent_data clk_parent_data = { .index = 0 };
286	const u8 data[3] = { SI521XX_REG_BC, 1, 1 };
287	unsigned char name[16] = "DIFF0";
288	struct clk_init_data init = {};
289	struct si521xx *si;
290	int i, ret;
291
292	if (!chip_info)
293		return -EINVAL;
294
295	si = devm_kzalloc(&client->dev, sizeof(*si), GFP_KERNEL);
296	if (!si)
297		return -ENOMEM;
298
299	i2c_set_clientdata(client, si);
300	si->client = client;
301
302	/* Fetch common configuration from DT (if specified) */
303	ret = si521xx_get_common_config(si);
304	if (ret)
305		return ret;
306
307	si->regmap = devm_regmap_init(&client->dev, NULL, client,
308				      &si521xx_regmap_config);
309	if (IS_ERR(si->regmap))
310		return dev_err_probe(&client->dev, PTR_ERR(si->regmap),
311				     "Failed to allocate register map\n");
312
313	/* Always read back 1 Byte via I2C */
314	ret = i2c_master_send(client, data, ARRAY_SIZE(data));
315	if (ret < 0)
316		return ret;
317
318	/* Register clock */
319	for (i = 0; i < hweight16(chip_info); i++) {
320		memset(&init, 0, sizeof(init));
321		snprintf(name, sizeof(name), "DIFF%d", i);
322		init.name = name;
323		init.ops = &si521xx_diff_clk_ops;
324		init.parent_data = &clk_parent_data;
325		init.num_parents = 1;
326		init.flags = CLK_SET_RATE_PARENT;
327
328		si->clk_dif[i].hw.init = &init;
329		si->clk_dif[i].si = si;
330
331		si521xx_diff_idx_to_reg_bit(chip_info, i, &si->clk_dif[i]);
332
333		ret = devm_clk_hw_register(&client->dev, &si->clk_dif[i].hw);
334		if (ret)
335			return ret;
336	}
337
338	ret = devm_of_clk_add_hw_provider(&client->dev, si521xx_of_clk_get, si);
339	if (!ret)
340		si521xx_update_config(si);
341
342	return ret;
343}
344
345static int __maybe_unused si521xx_suspend(struct device *dev)
346{
347	struct si521xx *si = dev_get_drvdata(dev);
348
349	regcache_cache_only(si->regmap, true);
350	regcache_mark_dirty(si->regmap);
351
352	return 0;
353}
354
355static int __maybe_unused si521xx_resume(struct device *dev)
356{
357	struct si521xx *si = dev_get_drvdata(dev);
358	int ret;
359
360	regcache_cache_only(si->regmap, false);
361	ret = regcache_sync(si->regmap);
362	if (ret)
363		dev_err(dev, "Failed to restore register map: %d\n", ret);
364	return ret;
365}
366
367static const struct i2c_device_id si521xx_id[] = {
368	{ "si52144", .driver_data = SI521XX_OE_MAP(0x5, 0xc0) },
369	{ "si52146", .driver_data = SI521XX_OE_MAP(0x15, 0xe0) },
370	{ "si52147", .driver_data = SI521XX_OE_MAP(0x17, 0xf8) },
371	{ }
372};
373MODULE_DEVICE_TABLE(i2c, si521xx_id);
374
375static const struct of_device_id clk_si521xx_of_match[] = {
376	{ .compatible = "skyworks,si52144", .data = (void *)SI521XX_OE_MAP(0x5, 0xc0) },
377	{ .compatible = "skyworks,si52146", .data = (void *)SI521XX_OE_MAP(0x15, 0xe0) },
378	{ .compatible = "skyworks,si52147", .data = (void *)SI521XX_OE_MAP(0x15, 0xf8) },
379	{ }
380};
381MODULE_DEVICE_TABLE(of, clk_si521xx_of_match);
382
383static SIMPLE_DEV_PM_OPS(si521xx_pm_ops, si521xx_suspend, si521xx_resume);
384
385static struct i2c_driver si521xx_driver = {
386	.driver = {
387		.name = "clk-si521xx",
388		.pm	= &si521xx_pm_ops,
389		.of_match_table = clk_si521xx_of_match,
390	},
391	.probe		= si521xx_probe,
392	.id_table	= si521xx_id,
393};
394module_i2c_driver(si521xx_driver);
395
396MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
397MODULE_DESCRIPTION("Skyworks Si521xx PCIe clock generator driver");
398MODULE_LICENSE("GPL");