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clk-rp1.c
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linux-6.19.14/drivers/clk/clk-rp1.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2023 Raspberry Pi Ltd. 4 * 5 * Clock driver for RP1 PCIe multifunction chip. 6 */ 7 8#include <linux/bitfield.h> 9#include <linux/clk-provider.h> 10#include <linux/regmap.h> 11#include <linux/math64.h> 12#include <linux/module.h> 13#include <linux/platform_device.h> 14#include <linux/units.h> 15 16#include <dt-bindings/clock/raspberrypi,rp1-clocks.h> 17 18#define PLL_SYS_OFFSET 0x08000 19#define PLL_SYS_CS (PLL_SYS_OFFSET + 0x00) 20#define PLL_SYS_PWR (PLL_SYS_OFFSET + 0x04) 21#define PLL_SYS_FBDIV_INT (PLL_SYS_OFFSET + 0x08) 22#define PLL_SYS_FBDIV_FRAC (PLL_SYS_OFFSET + 0x0c) 23#define PLL_SYS_PRIM (PLL_SYS_OFFSET + 0x10) 24#define PLL_SYS_SEC (PLL_SYS_OFFSET + 0x14) 25 26#define PLL_AUDIO_OFFSET 0x0c000 27#define PLL_AUDIO_CS (PLL_AUDIO_OFFSET + 0x00) 28#define PLL_AUDIO_PWR (PLL_AUDIO_OFFSET + 0x04) 29#define PLL_AUDIO_FBDIV_INT (PLL_AUDIO_OFFSET + 0x08) 30#define PLL_AUDIO_FBDIV_FRAC (PLL_AUDIO_OFFSET + 0x0c) 31#define PLL_AUDIO_PRIM (PLL_AUDIO_OFFSET + 0x10) 32#define PLL_AUDIO_SEC (PLL_AUDIO_OFFSET + 0x14) 33#define PLL_AUDIO_TERN (PLL_AUDIO_OFFSET + 0x18) 34 35#define PLL_VIDEO_OFFSET 0x10000 36#define PLL_VIDEO_CS (PLL_VIDEO_OFFSET + 0x00) 37#define PLL_VIDEO_PWR (PLL_VIDEO_OFFSET + 0x04) 38#define PLL_VIDEO_FBDIV_INT (PLL_VIDEO_OFFSET + 0x08) 39#define PLL_VIDEO_FBDIV_FRAC (PLL_VIDEO_OFFSET + 0x0c) 40#define PLL_VIDEO_PRIM (PLL_VIDEO_OFFSET + 0x10) 41#define PLL_VIDEO_SEC (PLL_VIDEO_OFFSET + 0x14) 42 43#define GPCLK_OE_CTRL 0x00000 44 45#define CLK_SYS_OFFSET 0x00014 46#define CLK_SYS_CTRL (CLK_SYS_OFFSET + 0x00) 47#define CLK_SYS_DIV_INT (CLK_SYS_OFFSET + 0x04) 48#define CLK_SYS_SEL (CLK_SYS_OFFSET + 0x0c) 49 50#define CLK_SLOW_OFFSET 0x00024 51#define CLK_SLOW_SYS_CTRL (CLK_SLOW_OFFSET + 0x00) 52#define CLK_SLOW_SYS_DIV_INT (CLK_SLOW_OFFSET + 0x04) 53#define CLK_SLOW_SYS_SEL (CLK_SLOW_OFFSET + 0x0c) 54 55#define CLK_DMA_OFFSET 0x00044 56#define CLK_DMA_CTRL (CLK_DMA_OFFSET + 0x00) 57#define CLK_DMA_DIV_INT (CLK_DMA_OFFSET + 0x04) 58#define CLK_DMA_SEL (CLK_DMA_OFFSET + 0x0c) 59 60#define CLK_UART_OFFSET 0x00054 61#define CLK_UART_CTRL (CLK_UART_OFFSET + 0x00) 62#define CLK_UART_DIV_INT (CLK_UART_OFFSET + 0x04) 63#define CLK_UART_SEL (CLK_UART_OFFSET + 0x0c) 64 65#define CLK_ETH_OFFSET 0x00064 66#define CLK_ETH_CTRL (CLK_ETH_OFFSET + 0x00) 67#define CLK_ETH_DIV_INT (CLK_ETH_OFFSET + 0x04) 68#define CLK_ETH_SEL (CLK_ETH_OFFSET + 0x0c) 69 70#define CLK_PWM0_OFFSET 0x00074 71#define CLK_PWM0_CTRL (CLK_PWM0_OFFSET + 0x00) 72#define CLK_PWM0_DIV_INT (CLK_PWM0_OFFSET + 0x04) 73#define CLK_PWM0_DIV_FRAC (CLK_PWM0_OFFSET + 0x08) 74#define CLK_PWM0_SEL (CLK_PWM0_OFFSET + 0x0c) 75 76#define CLK_PWM1_OFFSET 0x00084 77#define CLK_PWM1_CTRL (CLK_PWM1_OFFSET + 0x00) 78#define CLK_PWM1_DIV_INT (CLK_PWM1_OFFSET + 0x04) 79#define CLK_PWM1_DIV_FRAC (CLK_PWM1_OFFSET + 0x08) 80#define CLK_PWM1_SEL (CLK_PWM1_OFFSET + 0x0c) 81 82#define CLK_AUDIO_IN_OFFSET 0x00094 83#define CLK_AUDIO_IN_CTRL (CLK_AUDIO_IN_OFFSET + 0x00) 84#define CLK_AUDIO_IN_DIV_INT (CLK_AUDIO_IN_OFFSET + 0x04) 85#define CLK_AUDIO_IN_SEL (CLK_AUDIO_IN_OFFSET + 0x0c) 86 87#define CLK_AUDIO_OUT_OFFSET 0x000a4 88#define CLK_AUDIO_OUT_CTRL (CLK_AUDIO_OUT_OFFSET + 0x00) 89#define CLK_AUDIO_OUT_DIV_INT (CLK_AUDIO_OUT_OFFSET + 0x04) 90#define CLK_AUDIO_OUT_SEL (CLK_AUDIO_OUT_OFFSET + 0x0c) 91 92#define CLK_I2S_OFFSET 0x000b4 93#define CLK_I2S_CTRL (CLK_I2S_OFFSET + 0x00) 94#define CLK_I2S_DIV_INT (CLK_I2S_OFFSET + 0x04) 95#define CLK_I2S_SEL (CLK_I2S_OFFSET + 0x0c) 96 97#define CLK_MIPI0_CFG_OFFSET 0x000c4 98#define CLK_MIPI0_CFG_CTRL (CLK_MIPI0_CFG_OFFSET + 0x00) 99#define CLK_MIPI0_CFG_DIV_INT (CLK_MIPI0_CFG_OFFSET + 0x04) 100#define CLK_MIPI0_CFG_SEL (CLK_MIPI0_CFG_OFFSET + 0x0c) 101 102#define CLK_MIPI1_CFG_OFFSET 0x000d4 103#define CLK_MIPI1_CFG_CTRL (CLK_MIPI1_CFG_OFFSET + 0x00) 104#define CLK_MIPI1_CFG_DIV_INT (CLK_MIPI1_CFG_OFFSET + 0x04) 105#define CLK_MIPI1_CFG_SEL (CLK_MIPI1_CFG_OFFSET + 0x0c) 106 107#define CLK_PCIE_AUX_OFFSET 0x000e4 108#define CLK_PCIE_AUX_CTRL (CLK_PCIE_AUX_OFFSET + 0x00) 109#define CLK_PCIE_AUX_DIV_INT (CLK_PCIE_AUX_OFFSET + 0x04) 110#define CLK_PCIE_AUX_SEL (CLK_PCIE_AUX_OFFSET + 0x0c) 111 112#define CLK_USBH0_MICROFRAME_OFFSET 0x000f4 113#define CLK_USBH0_MICROFRAME_CTRL (CLK_USBH0_MICROFRAME_OFFSET + 0x00) 114#define CLK_USBH0_MICROFRAME_DIV_INT (CLK_USBH0_MICROFRAME_OFFSET + 0x04) 115#define CLK_USBH0_MICROFRAME_SEL (CLK_USBH0_MICROFRAME_OFFSET + 0x0c) 116 117#define CLK_USBH1_MICROFRAME_OFFSET 0x00104 118#define CLK_USBH1_MICROFRAME_CTRL (CLK_USBH1_MICROFRAME_OFFSET + 0x00) 119#define CLK_USBH1_MICROFRAME_DIV_INT (CLK_USBH1_MICROFRAME_OFFSET + 0x04) 120#define CLK_USBH1_MICROFRAME_SEL (CLK_USBH1_MICROFRAME_OFFSET + 0x0c) 121 122#define CLK_USBH0_SUSPEND_OFFSET 0x00114 123#define CLK_USBH0_SUSPEND_CTRL (CLK_USBH0_SUSPEND_OFFSET + 0x00) 124#define CLK_USBH0_SUSPEND_DIV_INT (CLK_USBH0_SUSPEND_OFFSET + 0x04) 125#define CLK_USBH0_SUSPEND_SEL (CLK_USBH0_SUSPEND_OFFSET + 0x0c) 126 127#define CLK_USBH1_SUSPEND_OFFSET 0x00124 128#define CLK_USBH1_SUSPEND_CTRL (CLK_USBH1_SUSPEND_OFFSET + 0x00) 129#define CLK_USBH1_SUSPEND_DIV_INT (CLK_USBH1_SUSPEND_OFFSET + 0x04) 130#define CLK_USBH1_SUSPEND_SEL (CLK_USBH1_SUSPEND_OFFSET + 0x0c) 131 132#define CLK_ETH_TSU_OFFSET 0x00134 133#define CLK_ETH_TSU_CTRL (CLK_ETH_TSU_OFFSET + 0x00) 134#define CLK_ETH_TSU_DIV_INT (CLK_ETH_TSU_OFFSET + 0x04) 135#define CLK_ETH_TSU_SEL (CLK_ETH_TSU_OFFSET + 0x0c) 136 137#define CLK_ADC_OFFSET 0x00144 138#define CLK_ADC_CTRL (CLK_ADC_OFFSET + 0x00) 139#define CLK_ADC_DIV_INT (CLK_ADC_OFFSET + 0x04) 140#define CLK_ADC_SEL (CLK_ADC_OFFSET + 0x0c) 141 142#define CLK_SDIO_TIMER_OFFSET 0x00154 143#define CLK_SDIO_TIMER_CTRL (CLK_SDIO_TIMER_OFFSET + 0x00) 144#define CLK_SDIO_TIMER_DIV_INT (CLK_SDIO_TIMER_OFFSET + 0x04) 145#define CLK_SDIO_TIMER_SEL (CLK_SDIO_TIMER_OFFSET + 0x0c) 146 147#define CLK_SDIO_ALT_SRC_OFFSET 0x00164 148#define CLK_SDIO_ALT_SRC_CTRL (CLK_SDIO_ALT_SRC_OFFSET + 0x00) 149#define CLK_SDIO_ALT_SRC_DIV_INT (CLK_SDIO_ALT_SRC_OFFSET + 0x04) 150#define CLK_SDIO_ALT_SRC_SEL (CLK_SDIO_ALT_SRC_OFFSET + 0x0c) 151 152#define CLK_GP0_OFFSET 0x00174 153#define CLK_GP0_CTRL (CLK_GP0_OFFSET + 0x00) 154#define CLK_GP0_DIV_INT (CLK_GP0_OFFSET + 0x04) 155#define CLK_GP0_DIV_FRAC (CLK_GP0_OFFSET + 0x08) 156#define CLK_GP0_SEL (CLK_GP0_OFFSET + 0x0c) 157 158#define CLK_GP1_OFFSET 0x00184 159#define CLK_GP1_CTRL (CLK_GP1_OFFSET + 0x00) 160#define CLK_GP1_DIV_INT (CLK_GP1_OFFSET + 0x04) 161#define CLK_GP1_DIV_FRAC (CLK_GP1_OFFSET + 0x08) 162#define CLK_GP1_SEL (CLK_GP1_OFFSET + 0x0c) 163 164#define CLK_GP2_OFFSET 0x00194 165#define CLK_GP2_CTRL (CLK_GP2_OFFSET + 0x00) 166#define CLK_GP2_DIV_INT (CLK_GP2_OFFSET + 0x04) 167#define CLK_GP2_DIV_FRAC (CLK_GP2_OFFSET + 0x08) 168#define CLK_GP2_SEL (CLK_GP2_OFFSET + 0x0c) 169 170#define CLK_GP3_OFFSET 0x001a4 171#define CLK_GP3_CTRL (CLK_GP3_OFFSET + 0x00) 172#define CLK_GP3_DIV_INT (CLK_GP3_OFFSET + 0x04) 173#define CLK_GP3_DIV_FRAC (CLK_GP3_OFFSET + 0x08) 174#define CLK_GP3_SEL (CLK_GP3_OFFSET + 0x0c) 175 176#define CLK_GP4_OFFSET 0x001b4 177#define CLK_GP4_CTRL (CLK_GP4_OFFSET + 0x00) 178#define CLK_GP4_DIV_INT (CLK_GP4_OFFSET + 0x04) 179#define CLK_GP4_DIV_FRAC (CLK_GP4_OFFSET + 0x08) 180#define CLK_GP4_SEL (CLK_GP4_OFFSET + 0x0c) 181 182#define CLK_GP5_OFFSET 0x001c4 183#define CLK_GP5_CTRL (CLK_GP5_OFFSET + 0x00) 184#define CLK_GP5_DIV_INT (CLK_GP5_OFFSET + 0x04) 185#define CLK_GP5_DIV_FRAC (CLK_GP5_OFFSET + 0x08) 186#define CLK_GP5_SEL (CLK_GP5_OFFSET + 0x0c) 187 188#define CLK_SYS_RESUS_CTRL 0x0020c 189 190#define CLK_SLOW_SYS_RESUS_CTRL 0x00214 191 192#define FC0_OFFSET 0x0021c 193#define FC0_REF_KHZ (FC0_OFFSET + 0x00) 194#define FC0_MIN_KHZ (FC0_OFFSET + 0x04) 195#define FC0_MAX_KHZ (FC0_OFFSET + 0x08) 196#define FC0_DELAY (FC0_OFFSET + 0x0c) 197#define FC0_INTERVAL (FC0_OFFSET + 0x10) 198#define FC0_SRC (FC0_OFFSET + 0x14) 199#define FC0_STATUS (FC0_OFFSET + 0x18) 200#define FC0_RESULT (FC0_OFFSET + 0x1c) 201#define FC_SIZE 0x20 202#define FC_COUNT 8 203#define FC_NUM(idx, off) ((idx) * 32 + (off)) 204 205#define AUX_SEL 1 206 207#define VIDEO_CLOCKS_OFFSET 0x4000 208#define VIDEO_CLK_VEC_CTRL (VIDEO_CLOCKS_OFFSET + 0x0000) 209#define VIDEO_CLK_VEC_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0004) 210#define VIDEO_CLK_VEC_SEL (VIDEO_CLOCKS_OFFSET + 0x000c) 211#define VIDEO_CLK_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0010) 212#define VIDEO_CLK_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0014) 213#define VIDEO_CLK_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x001c) 214#define VIDEO_CLK_MIPI0_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0020) 215#define VIDEO_CLK_MIPI0_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0024) 216#define VIDEO_CLK_MIPI0_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0028) 217#define VIDEO_CLK_MIPI0_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x002c) 218#define VIDEO_CLK_MIPI1_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0030) 219#define VIDEO_CLK_MIPI1_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0034) 220#define VIDEO_CLK_MIPI1_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0038) 221#define VIDEO_CLK_MIPI1_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x003c) 222 223#define DIV_INT_8BIT_MAX GENMASK(7, 0) /* max divide for most clocks */ 224#define DIV_INT_16BIT_MAX GENMASK(15, 0) /* max divide for GPx, PWM */ 225#define DIV_INT_24BIT_MAX GENMASK(23, 0) /* max divide for CLK_SYS */ 226 227#define FC0_STATUS_DONE BIT(4) 228#define FC0_STATUS_RUNNING BIT(8) 229#define FC0_RESULT_FRAC_SHIFT 5 230 231#define PLL_PRIM_DIV1_MASK GENMASK(18, 16) 232#define PLL_PRIM_DIV2_MASK GENMASK(14, 12) 233 234#define PLL_SEC_DIV_MASK GENMASK(12, 8) 235 236#define PLL_CS_LOCK BIT(31) 237#define PLL_CS_REFDIV_MASK BIT(1) 238 239#define PLL_PWR_PD BIT(0) 240#define PLL_PWR_DACPD BIT(1) 241#define PLL_PWR_DSMPD BIT(2) 242#define PLL_PWR_POSTDIVPD BIT(3) 243#define PLL_PWR_4PHASEPD BIT(4) 244#define PLL_PWR_VCOPD BIT(5) 245#define PLL_PWR_MASK GENMASK(5, 0) 246 247#define PLL_SEC_RST BIT(16) 248#define PLL_SEC_IMPL BIT(31) 249 250/* PLL phase output for both PRI and SEC */ 251#define PLL_PH_EN BIT(4) 252#define PLL_PH_PHASE_SHIFT 0 253 254#define RP1_PLL_PHASE_0 0 255#define RP1_PLL_PHASE_90 1 256#define RP1_PLL_PHASE_180 2 257#define RP1_PLL_PHASE_270 3 258 259/* Clock fields for all clocks */ 260#define CLK_CTRL_ENABLE BIT(11) 261#define CLK_CTRL_AUXSRC_MASK GENMASK(9, 5) 262#define CLK_CTRL_SRC_SHIFT 0 263#define CLK_DIV_FRAC_BITS 16 264 265#define LOCK_TIMEOUT_US 100000 266#define LOCK_POLL_DELAY_US 5 267 268#define MAX_CLK_PARENTS 16 269 270#define PLL_DIV_INVALID 19 271/* 272 * Secondary PLL channel output divider table. 273 * Divider values range from 8 to 19, where 274 * 19 means invalid. 275 */ 276static const struct clk_div_table pll_sec_div_table[] = { 277 { 0x00, PLL_DIV_INVALID }, 278 { 0x01, PLL_DIV_INVALID }, 279 { 0x02, PLL_DIV_INVALID }, 280 { 0x03, PLL_DIV_INVALID }, 281 { 0x04, PLL_DIV_INVALID }, 282 { 0x05, PLL_DIV_INVALID }, 283 { 0x06, PLL_DIV_INVALID }, 284 { 0x07, PLL_DIV_INVALID }, 285 { 0x08, 8 }, 286 { 0x09, 9 }, 287 { 0x0a, 10 }, 288 { 0x0b, 11 }, 289 { 0x0c, 12 }, 290 { 0x0d, 13 }, 291 { 0x0e, 14 }, 292 { 0x0f, 15 }, 293 { 0x10, 16 }, 294 { 0x11, 17 }, 295 { 0x12, 18 }, 296 { 0x13, PLL_DIV_INVALID }, 297 { 0x14, PLL_DIV_INVALID }, 298 { 0x15, PLL_DIV_INVALID }, 299 { 0x16, PLL_DIV_INVALID }, 300 { 0x17, PLL_DIV_INVALID }, 301 { 0x18, PLL_DIV_INVALID }, 302 { 0x19, PLL_DIV_INVALID }, 303 { 0x1a, PLL_DIV_INVALID }, 304 { 0x1b, PLL_DIV_INVALID }, 305 { 0x1c, PLL_DIV_INVALID }, 306 { 0x1d, PLL_DIV_INVALID }, 307 { 0x1e, PLL_DIV_INVALID }, 308 { 0x1f, PLL_DIV_INVALID }, 309 { 0 } 310}; 311 312struct rp1_clockman { 313 struct device *dev; 314 void __iomem *regs; 315 struct regmap *regmap; 316 spinlock_t regs_lock; /* spinlock for all clocks */ 317 318 /* Must be last */ 319 struct clk_hw_onecell_data onecell; 320}; 321 322struct rp1_pll_core_data { 323 u32 cs_reg; 324 u32 pwr_reg; 325 u32 fbdiv_int_reg; 326 u32 fbdiv_frac_reg; 327 u32 fc0_src; 328}; 329 330struct rp1_pll_data { 331 u32 ctrl_reg; 332 u32 fc0_src; 333}; 334 335struct rp1_pll_ph_data { 336 unsigned int phase; 337 unsigned int fixed_divider; 338 u32 ph_reg; 339 u32 fc0_src; 340}; 341 342struct rp1_pll_divider_data { 343 u32 sec_reg; 344 u32 fc0_src; 345}; 346 347struct rp1_clock_data { 348 int num_std_parents; 349 int num_aux_parents; 350 u32 oe_mask; 351 u32 clk_src_mask; 352 u32 ctrl_reg; 353 u32 div_int_reg; 354 u32 div_frac_reg; 355 u32 sel_reg; 356 u32 div_int_max; 357 unsigned long max_freq; 358 u32 fc0_src; 359}; 360 361struct rp1_clk_desc { 362 struct clk_hw *(*clk_register)(struct rp1_clockman *clockman, 363 struct rp1_clk_desc *desc); 364 const void *data; 365 struct clk_hw hw; 366 struct rp1_clockman *clockman; 367 unsigned long cached_rate; 368 struct clk_divider div; 369}; 370 371static struct rp1_clk_desc *clk_audio_core; 372static struct rp1_clk_desc *clk_audio; 373static struct rp1_clk_desc *clk_i2s; 374static struct clk_hw *clk_xosc; 375 376static inline 377void clockman_write(struct rp1_clockman *clockman, u32 reg, u32 val) 378{ 379 regmap_write(clockman->regmap, reg, val); 380} 381 382static inline u32 clockman_read(struct rp1_clockman *clockman, u32 reg) 383{ 384 u32 val; 385 386 regmap_read(clockman->regmap, reg, &val); 387 388 return val; 389} 390 391static int rp1_pll_core_is_on(struct clk_hw *hw) 392{ 393 struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); 394 struct rp1_clockman *clockman = pll_core->clockman; 395 const struct rp1_pll_core_data *data = pll_core->data; 396 u32 pwr = clockman_read(clockman, data->pwr_reg); 397 398 return (pwr & PLL_PWR_PD) || (pwr & PLL_PWR_POSTDIVPD); 399} 400 401static int rp1_pll_core_on(struct clk_hw *hw) 402{ 403 struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); 404 struct rp1_clockman *clockman = pll_core->clockman; 405 const struct rp1_pll_core_data *data = pll_core->data; 406 u32 fbdiv_frac, val; 407 int ret; 408 409 spin_lock(&clockman->regs_lock); 410 411 if (!(clockman_read(clockman, data->cs_reg) & PLL_CS_LOCK)) { 412 /* Reset to a known state. */ 413 clockman_write(clockman, data->pwr_reg, PLL_PWR_MASK); 414 clockman_write(clockman, data->fbdiv_int_reg, 20); 415 clockman_write(clockman, data->fbdiv_frac_reg, 0); 416 clockman_write(clockman, data->cs_reg, PLL_CS_REFDIV_MASK); 417 } 418 419 /* Come out of reset. */ 420 fbdiv_frac = clockman_read(clockman, data->fbdiv_frac_reg); 421 clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD); 422 spin_unlock(&clockman->regs_lock); 423 424 /* Wait for the PLL to lock. */ 425 ret = regmap_read_poll_timeout(clockman->regmap, data->cs_reg, val, 426 val & PLL_CS_LOCK, 427 LOCK_POLL_DELAY_US, LOCK_TIMEOUT_US); 428 if (ret) 429 dev_err(clockman->dev, "%s: can't lock PLL\n", 430 clk_hw_get_name(hw)); 431 432 return ret; 433} 434 435static void rp1_pll_core_off(struct clk_hw *hw) 436{ 437 struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); 438 struct rp1_clockman *clockman = pll_core->clockman; 439 const struct rp1_pll_core_data *data = pll_core->data; 440 441 spin_lock(&clockman->regs_lock); 442 clockman_write(clockman, data->pwr_reg, 0); 443 spin_unlock(&clockman->regs_lock); 444} 445 446static inline unsigned long get_pll_core_divider(struct clk_hw *hw, 447 unsigned long rate, 448 unsigned long parent_rate, 449 u32 *div_int, u32 *div_frac) 450{ 451 u32 fbdiv_int, fbdiv_frac; 452 unsigned long calc_rate; 453 u64 shifted_fbdiv_int; 454 u64 div_fp64; /* 32.32 fixed point fraction. */ 455 456 /* Factor of reference clock to VCO frequency. */ 457 div_fp64 = (u64)(rate) << 32; 458 div_fp64 = DIV_ROUND_CLOSEST_ULL(div_fp64, parent_rate); 459 460 /* Round the fractional component at 24 bits. */ 461 div_fp64 += 1 << (32 - 24 - 1); 462 463 fbdiv_int = div_fp64 >> 32; 464 fbdiv_frac = (div_fp64 >> (32 - 24)) & 0xffffff; 465 466 shifted_fbdiv_int = (u64)fbdiv_int << 24; 467 calc_rate = (u64)parent_rate * (shifted_fbdiv_int + fbdiv_frac); 468 calc_rate += BIT(23); 469 calc_rate >>= 24; 470 471 *div_int = fbdiv_int; 472 *div_frac = fbdiv_frac; 473 474 return calc_rate; 475} 476 477static int rp1_pll_core_set_rate(struct clk_hw *hw, 478 unsigned long rate, unsigned long parent_rate) 479{ 480 struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); 481 struct rp1_clockman *clockman = pll_core->clockman; 482 const struct rp1_pll_core_data *data = pll_core->data; 483 u32 fbdiv_int, fbdiv_frac; 484 485 /* Disable dividers to start with. */ 486 spin_lock(&clockman->regs_lock); 487 clockman_write(clockman, data->fbdiv_int_reg, 0); 488 clockman_write(clockman, data->fbdiv_frac_reg, 0); 489 spin_unlock(&clockman->regs_lock); 490 491 get_pll_core_divider(hw, rate, parent_rate, 492 &fbdiv_int, &fbdiv_frac); 493 494 spin_lock(&clockman->regs_lock); 495 clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD); 496 clockman_write(clockman, data->fbdiv_int_reg, fbdiv_int); 497 clockman_write(clockman, data->fbdiv_frac_reg, fbdiv_frac); 498 spin_unlock(&clockman->regs_lock); 499 500 /* Check that reference frequency is no greater than VCO / 16. */ 501 if (WARN_ON_ONCE(parent_rate > (rate / 16))) 502 return -ERANGE; 503 504 spin_lock(&clockman->regs_lock); 505 /* Don't need to divide ref unless parent_rate > (output freq / 16) */ 506 clockman_write(clockman, data->cs_reg, 507 clockman_read(clockman, data->cs_reg) | 508 PLL_CS_REFDIV_MASK); 509 spin_unlock(&clockman->regs_lock); 510 511 return 0; 512} 513 514static unsigned long rp1_pll_core_recalc_rate(struct clk_hw *hw, 515 unsigned long parent_rate) 516{ 517 struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); 518 struct rp1_clockman *clockman = pll_core->clockman; 519 const struct rp1_pll_core_data *data = pll_core->data; 520 u32 fbdiv_int, fbdiv_frac; 521 unsigned long calc_rate; 522 u64 shifted_fbdiv_int; 523 524 fbdiv_int = clockman_read(clockman, data->fbdiv_int_reg); 525 fbdiv_frac = clockman_read(clockman, data->fbdiv_frac_reg); 526 527 shifted_fbdiv_int = (u64)fbdiv_int << 24; 528 calc_rate = (u64)parent_rate * (shifted_fbdiv_int + fbdiv_frac); 529 calc_rate += BIT(23); 530 calc_rate >>= 24; 531 532 return calc_rate; 533} 534 535static int rp1_pll_core_determine_rate(struct clk_hw *hw, 536 struct clk_rate_request *req) 537{ 538 u32 fbdiv_int, fbdiv_frac; 539 540 req->rate = get_pll_core_divider(hw, req->rate, req->best_parent_rate, 541 &fbdiv_int, 542 &fbdiv_frac); 543 544 return 0; 545} 546 547static void get_pll_prim_dividers(unsigned long rate, unsigned long parent_rate, 548 u32 *divider1, u32 *divider2) 549{ 550 unsigned int div1, div2; 551 unsigned int best_div1 = 7, best_div2 = 7; 552 unsigned long best_rate_diff = 553 abs_diff(DIV_ROUND_CLOSEST(parent_rate, best_div1 * best_div2), rate); 554 unsigned long rate_diff, calc_rate; 555 556 for (div1 = 1; div1 <= 7; div1++) { 557 for (div2 = 1; div2 <= div1; div2++) { 558 calc_rate = DIV_ROUND_CLOSEST(parent_rate, div1 * div2); 559 rate_diff = abs_diff(calc_rate, rate); 560 561 if (calc_rate == rate) { 562 best_div1 = div1; 563 best_div2 = div2; 564 goto done; 565 } else if (rate_diff < best_rate_diff) { 566 best_div1 = div1; 567 best_div2 = div2; 568 best_rate_diff = rate_diff; 569 } 570 } 571 } 572 573done: 574 *divider1 = best_div1; 575 *divider2 = best_div2; 576} 577 578static int rp1_pll_set_rate(struct clk_hw *hw, 579 unsigned long rate, unsigned long parent_rate) 580{ 581 struct rp1_clk_desc *pll = container_of(hw, struct rp1_clk_desc, hw); 582 struct rp1_clockman *clockman = pll->clockman; 583 const struct rp1_pll_data *data = pll->data; 584 585 u32 prim, prim_div1, prim_div2; 586 587 get_pll_prim_dividers(rate, parent_rate, &prim_div1, &prim_div2); 588 589 spin_lock(&clockman->regs_lock); 590 prim = clockman_read(clockman, data->ctrl_reg); 591 prim &= ~PLL_PRIM_DIV1_MASK; 592 prim |= FIELD_PREP(PLL_PRIM_DIV1_MASK, prim_div1); 593 prim &= ~PLL_PRIM_DIV2_MASK; 594 prim |= FIELD_PREP(PLL_PRIM_DIV2_MASK, prim_div2); 595 clockman_write(clockman, data->ctrl_reg, prim); 596 spin_unlock(&clockman->regs_lock); 597 598 return 0; 599} 600 601static unsigned long rp1_pll_recalc_rate(struct clk_hw *hw, 602 unsigned long parent_rate) 603{ 604 struct rp1_clk_desc *pll = container_of(hw, struct rp1_clk_desc, hw); 605 struct rp1_clockman *clockman = pll->clockman; 606 const struct rp1_pll_data *data = pll->data; 607 u32 prim, prim_div1, prim_div2; 608 609 prim = clockman_read(clockman, data->ctrl_reg); 610 prim_div1 = FIELD_GET(PLL_PRIM_DIV1_MASK, prim); 611 prim_div2 = FIELD_GET(PLL_PRIM_DIV2_MASK, prim); 612 613 if (!prim_div1 || !prim_div2) { 614 dev_err(clockman->dev, "%s: (%s) zero divider value\n", 615 __func__, clk_hw_get_name(hw)); 616 return 0; 617 } 618 619 return DIV_ROUND_CLOSEST(parent_rate, prim_div1 * prim_div2); 620} 621 622static int rp1_pll_determine_rate(struct clk_hw *hw, 623 struct clk_rate_request *req) 624{ 625 struct clk_hw *clk_audio_hw = &clk_audio->hw; 626 u32 div1, div2; 627 628 if (hw == clk_audio_hw && clk_audio->cached_rate == req->rate) 629 req->best_parent_rate = clk_audio_core->cached_rate; 630 631 get_pll_prim_dividers(req->rate, req->best_parent_rate, &div1, &div2); 632 633 req->rate = DIV_ROUND_CLOSEST(req->best_parent_rate, div1 * div2); 634 635 return 0; 636} 637 638static int rp1_pll_ph_is_on(struct clk_hw *hw) 639{ 640 struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw); 641 struct rp1_clockman *clockman = pll_ph->clockman; 642 const struct rp1_pll_ph_data *data = pll_ph->data; 643 644 return !!(clockman_read(clockman, data->ph_reg) & PLL_PH_EN); 645} 646 647static int rp1_pll_ph_on(struct clk_hw *hw) 648{ 649 struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw); 650 struct rp1_clockman *clockman = pll_ph->clockman; 651 const struct rp1_pll_ph_data *data = pll_ph->data; 652 u32 ph_reg; 653 654 spin_lock(&clockman->regs_lock); 655 ph_reg = clockman_read(clockman, data->ph_reg); 656 ph_reg |= data->phase << PLL_PH_PHASE_SHIFT; 657 ph_reg |= PLL_PH_EN; 658 clockman_write(clockman, data->ph_reg, ph_reg); 659 spin_unlock(&clockman->regs_lock); 660 661 return 0; 662} 663 664static void rp1_pll_ph_off(struct clk_hw *hw) 665{ 666 struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw); 667 struct rp1_clockman *clockman = pll_ph->clockman; 668 const struct rp1_pll_ph_data *data = pll_ph->data; 669 670 spin_lock(&clockman->regs_lock); 671 clockman_write(clockman, data->ph_reg, 672 clockman_read(clockman, data->ph_reg) & ~PLL_PH_EN); 673 spin_unlock(&clockman->regs_lock); 674} 675 676static unsigned long rp1_pll_ph_recalc_rate(struct clk_hw *hw, 677 unsigned long parent_rate) 678{ 679 struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw); 680 const struct rp1_pll_ph_data *data = pll_ph->data; 681 682 return parent_rate / data->fixed_divider; 683} 684 685static int rp1_pll_ph_determine_rate(struct clk_hw *hw, 686 struct clk_rate_request *req) 687{ 688 struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw); 689 const struct rp1_pll_ph_data *data = pll_ph->data; 690 691 req->rate = req->best_parent_rate / data->fixed_divider; 692 693 return 0; 694} 695 696static int rp1_pll_divider_is_on(struct clk_hw *hw) 697{ 698 struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); 699 struct rp1_clockman *clockman = divider->clockman; 700 const struct rp1_pll_data *data = divider->data; 701 702 return !(clockman_read(clockman, data->ctrl_reg) & PLL_SEC_RST); 703} 704 705static int rp1_pll_divider_on(struct clk_hw *hw) 706{ 707 struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); 708 struct rp1_clockman *clockman = divider->clockman; 709 const struct rp1_pll_data *data = divider->data; 710 711 spin_lock(&clockman->regs_lock); 712 /* Check the implementation bit is set! */ 713 WARN_ON(!(clockman_read(clockman, data->ctrl_reg) & PLL_SEC_IMPL)); 714 clockman_write(clockman, data->ctrl_reg, 715 clockman_read(clockman, data->ctrl_reg) & ~PLL_SEC_RST); 716 spin_unlock(&clockman->regs_lock); 717 718 return 0; 719} 720 721static void rp1_pll_divider_off(struct clk_hw *hw) 722{ 723 struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); 724 struct rp1_clockman *clockman = divider->clockman; 725 const struct rp1_pll_data *data = divider->data; 726 727 spin_lock(&clockman->regs_lock); 728 clockman_write(clockman, data->ctrl_reg, 729 clockman_read(clockman, data->ctrl_reg) | PLL_SEC_RST); 730 spin_unlock(&clockman->regs_lock); 731} 732 733static int rp1_pll_divider_set_rate(struct clk_hw *hw, 734 unsigned long rate, 735 unsigned long parent_rate) 736{ 737 struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); 738 struct rp1_clockman *clockman = divider->clockman; 739 const struct rp1_pll_data *data = divider->data; 740 u32 div, sec; 741 742 div = DIV_ROUND_UP_ULL(parent_rate, rate); 743 div = clamp(div, 8u, 19u); 744 745 spin_lock(&clockman->regs_lock); 746 sec = clockman_read(clockman, data->ctrl_reg); 747 sec &= ~PLL_SEC_DIV_MASK; 748 sec |= FIELD_PREP(PLL_SEC_DIV_MASK, div); 749 750 /* Must keep the divider in reset to change the value. */ 751 sec |= PLL_SEC_RST; 752 clockman_write(clockman, data->ctrl_reg, sec); 753 754 /* must sleep 10 pll vco cycles */ 755 ndelay(div64_ul(10ULL * div * NSEC_PER_SEC, parent_rate)); 756 757 sec &= ~PLL_SEC_RST; 758 clockman_write(clockman, data->ctrl_reg, sec); 759 spin_unlock(&clockman->regs_lock); 760 761 return 0; 762} 763 764static unsigned long rp1_pll_divider_recalc_rate(struct clk_hw *hw, 765 unsigned long parent_rate) 766{ 767 return clk_divider_ops.recalc_rate(hw, parent_rate); 768} 769 770static int rp1_pll_divider_determine_rate(struct clk_hw *hw, 771 struct clk_rate_request *req) 772{ 773 req->rate = clk_divider_ops.determine_rate(hw, req); 774 775 return 0; 776} 777 778static int rp1_clock_is_on(struct clk_hw *hw) 779{ 780 struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); 781 struct rp1_clockman *clockman = clock->clockman; 782 const struct rp1_clock_data *data = clock->data; 783 784 return !!(clockman_read(clockman, data->ctrl_reg) & CLK_CTRL_ENABLE); 785} 786 787static unsigned long rp1_clock_recalc_rate(struct clk_hw *hw, 788 unsigned long parent_rate) 789{ 790 struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); 791 struct rp1_clockman *clockman = clock->clockman; 792 const struct rp1_clock_data *data = clock->data; 793 u64 calc_rate; 794 u64 div; 795 u32 frac; 796 797 div = clockman_read(clockman, data->div_int_reg); 798 frac = (data->div_frac_reg != 0) ? 799 clockman_read(clockman, data->div_frac_reg) : 0; 800 801 /* If the integer portion of the divider is 0, treat it as 2^16 */ 802 if (!div) 803 div = 1 << 16; 804 805 div = (div << CLK_DIV_FRAC_BITS) | (frac >> (32 - CLK_DIV_FRAC_BITS)); 806 807 calc_rate = (u64)parent_rate << CLK_DIV_FRAC_BITS; 808 calc_rate = div64_u64(calc_rate, div); 809 810 return calc_rate; 811} 812 813static int rp1_clock_on(struct clk_hw *hw) 814{ 815 struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); 816 struct rp1_clockman *clockman = clock->clockman; 817 const struct rp1_clock_data *data = clock->data; 818 819 spin_lock(&clockman->regs_lock); 820 clockman_write(clockman, data->ctrl_reg, 821 clockman_read(clockman, data->ctrl_reg) | CLK_CTRL_ENABLE); 822 /* If this is a GPCLK, turn on the output-enable */ 823 if (data->oe_mask) 824 clockman_write(clockman, GPCLK_OE_CTRL, 825 clockman_read(clockman, GPCLK_OE_CTRL) | data->oe_mask); 826 spin_unlock(&clockman->regs_lock); 827 828 return 0; 829} 830 831static void rp1_clock_off(struct clk_hw *hw) 832{ 833 struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); 834 struct rp1_clockman *clockman = clock->clockman; 835 const struct rp1_clock_data *data = clock->data; 836 837 spin_lock(&clockman->regs_lock); 838 clockman_write(clockman, data->ctrl_reg, 839 clockman_read(clockman, data->ctrl_reg) & ~CLK_CTRL_ENABLE); 840 /* If this is a GPCLK, turn off the output-enable */ 841 if (data->oe_mask) 842 clockman_write(clockman, GPCLK_OE_CTRL, 843 clockman_read(clockman, GPCLK_OE_CTRL) & ~data->oe_mask); 844 spin_unlock(&clockman->regs_lock); 845} 846 847static u32 rp1_clock_choose_div(unsigned long rate, unsigned long parent_rate, 848 const struct rp1_clock_data *data) 849{ 850 u64 div; 851 852 /* 853 * Due to earlier rounding, calculated parent_rate may differ from 854 * expected value. Don't fail on a small discrepancy near unity divide. 855 */ 856 if (!rate || rate > parent_rate + (parent_rate >> CLK_DIV_FRAC_BITS)) 857 return 0; 858 859 /* 860 * Always express div in fixed-point format for fractional division; 861 * If no fractional divider is present, the fraction part will be zero. 862 */ 863 if (data->div_frac_reg) { 864 div = (u64)parent_rate << CLK_DIV_FRAC_BITS; 865 div = DIV_ROUND_CLOSEST_ULL(div, rate); 866 } else { 867 div = DIV_ROUND_CLOSEST_ULL(parent_rate, rate); 868 div <<= CLK_DIV_FRAC_BITS; 869 } 870 871 div = clamp(div, 872 1ull << CLK_DIV_FRAC_BITS, 873 (u64)data->div_int_max << CLK_DIV_FRAC_BITS); 874 875 return div; 876} 877 878static u8 rp1_clock_get_parent(struct clk_hw *hw) 879{ 880 struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); 881 struct rp1_clockman *clockman = clock->clockman; 882 const struct rp1_clock_data *data = clock->data; 883 u32 sel, ctrl; 884 u8 parent; 885 886 /* Sel is one-hot, so find the first bit set */ 887 sel = clockman_read(clockman, data->sel_reg); 888 parent = ffs(sel) - 1; 889 890 /* sel == 0 implies the parent clock is not enabled yet. */ 891 if (!sel) { 892 /* Read the clock src from the CTRL register instead */ 893 ctrl = clockman_read(clockman, data->ctrl_reg); 894 parent = (ctrl & data->clk_src_mask) >> CLK_CTRL_SRC_SHIFT; 895 } 896 897 if (parent >= data->num_std_parents) 898 parent = AUX_SEL; 899 900 if (parent == AUX_SEL) { 901 /* 902 * Clock parent is an auxiliary source, so get the parent from 903 * the AUXSRC register field. 904 */ 905 ctrl = clockman_read(clockman, data->ctrl_reg); 906 parent = FIELD_GET(CLK_CTRL_AUXSRC_MASK, ctrl); 907 parent += data->num_std_parents; 908 } 909 910 return parent; 911} 912 913static int rp1_clock_set_parent(struct clk_hw *hw, u8 index) 914{ 915 struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); 916 struct rp1_clockman *clockman = clock->clockman; 917 const struct rp1_clock_data *data = clock->data; 918 u32 ctrl, sel; 919 920 spin_lock(&clockman->regs_lock); 921 ctrl = clockman_read(clockman, data->ctrl_reg); 922 923 if (index >= data->num_std_parents) { 924 /* This is an aux source request */ 925 if (index >= data->num_std_parents + data->num_aux_parents) { 926 spin_unlock(&clockman->regs_lock); 927 return -EINVAL; 928 } 929 930 /* Select parent from aux list */ 931 ctrl &= ~CLK_CTRL_AUXSRC_MASK; 932 ctrl |= FIELD_PREP(CLK_CTRL_AUXSRC_MASK, index - data->num_std_parents); 933 /* Set src to aux list */ 934 ctrl &= ~data->clk_src_mask; 935 ctrl |= (AUX_SEL << CLK_CTRL_SRC_SHIFT) & data->clk_src_mask; 936 } else { 937 ctrl &= ~data->clk_src_mask; 938 ctrl |= (index << CLK_CTRL_SRC_SHIFT) & data->clk_src_mask; 939 } 940 941 clockman_write(clockman, data->ctrl_reg, ctrl); 942 spin_unlock(&clockman->regs_lock); 943 944 sel = rp1_clock_get_parent(hw); 945 if (sel != index) 946 return -EINVAL; 947 948 return 0; 949} 950 951static int rp1_clock_set_rate_and_parent(struct clk_hw *hw, 952 unsigned long rate, 953 unsigned long parent_rate, 954 u8 parent) 955{ 956 struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); 957 struct rp1_clockman *clockman = clock->clockman; 958 const struct rp1_clock_data *data = clock->data; 959 u32 div = rp1_clock_choose_div(rate, parent_rate, data); 960 961 spin_lock(&clockman->regs_lock); 962 963 clockman_write(clockman, data->div_int_reg, div >> CLK_DIV_FRAC_BITS); 964 if (data->div_frac_reg) 965 clockman_write(clockman, data->div_frac_reg, div << (32 - CLK_DIV_FRAC_BITS)); 966 967 spin_unlock(&clockman->regs_lock); 968 969 if (parent != 0xff) 970 return rp1_clock_set_parent(hw, parent); 971 972 return 0; 973} 974 975static int rp1_clock_set_rate(struct clk_hw *hw, unsigned long rate, 976 unsigned long parent_rate) 977{ 978 return rp1_clock_set_rate_and_parent(hw, rate, parent_rate, 0xff); 979} 980 981static unsigned long calc_core_pll_rate(struct clk_hw *pll_hw, 982 unsigned long target_rate, 983 int *pdiv_prim, int *pdiv_clk) 984{ 985 static const int prim_divs[] = { 986 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 15, 16, 987 18, 20, 21, 24, 25, 28, 30, 35, 36, 42, 49, 988 }; 989 const unsigned long xosc_rate = clk_hw_get_rate(clk_xosc); 990 const unsigned long core_min = xosc_rate * 16; 991 const unsigned long core_max = 2400000000; 992 int best_div_prim = 1, best_div_clk = 1; 993 unsigned long best_rate = core_max + 1; 994 unsigned long core_rate = 0; 995 int div_int, div_frac; 996 u64 div; 997 int i; 998 999 /* Given the target rate, choose a set of divisors/multipliers */ 1000 for (i = 0; i < ARRAY_SIZE(prim_divs); i++) { 1001 int div_prim = prim_divs[i]; 1002 int div_clk; 1003 1004 for (div_clk = 1; div_clk <= 256; div_clk++) { 1005 core_rate = target_rate * div_clk * div_prim; 1006 if (core_rate >= core_min) { 1007 if (core_rate < best_rate) { 1008 best_rate = core_rate; 1009 best_div_prim = div_prim; 1010 best_div_clk = div_clk; 1011 } 1012 break; 1013 } 1014 } 1015 } 1016 1017 if (best_rate < core_max) { 1018 div = ((best_rate << 24) + xosc_rate / 2) / xosc_rate; 1019 div_int = div >> 24; 1020 div_frac = div % (1 << 24); 1021 core_rate = (xosc_rate * ((div_int << 24) + div_frac) + (1 << 23)) >> 24; 1022 } else { 1023 core_rate = 0; 1024 } 1025 1026 if (pdiv_prim) 1027 *pdiv_prim = best_div_prim; 1028 if (pdiv_clk) 1029 *pdiv_clk = best_div_clk; 1030 1031 return core_rate; 1032} 1033 1034static void rp1_clock_choose_div_and_prate(struct clk_hw *hw, 1035 int parent_idx, 1036 unsigned long rate, 1037 unsigned long *prate, 1038 unsigned long *calc_rate) 1039{ 1040 struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); 1041 const struct rp1_clock_data *data = clock->data; 1042 struct clk_hw *clk_audio_hw = &clk_audio->hw; 1043 struct clk_hw *clk_i2s_hw = &clk_i2s->hw; 1044 struct clk_hw *parent; 1045 u32 div; 1046 u64 tmp; 1047 1048 parent = clk_hw_get_parent_by_index(hw, parent_idx); 1049 1050 if (hw == clk_i2s_hw && clk_i2s->cached_rate == rate && parent == clk_audio_hw) { 1051 *prate = clk_audio->cached_rate; 1052 *calc_rate = rate; 1053 return; 1054 } 1055 1056 if (hw == clk_i2s_hw && parent == clk_audio_hw) { 1057 unsigned long core_rate, audio_rate, i2s_rate; 1058 int div_prim, div_clk; 1059 1060 core_rate = calc_core_pll_rate(parent, rate, &div_prim, &div_clk); 1061 audio_rate = DIV_ROUND_CLOSEST(core_rate, div_prim); 1062 i2s_rate = DIV_ROUND_CLOSEST(audio_rate, div_clk); 1063 clk_audio_core->cached_rate = core_rate; 1064 clk_audio->cached_rate = audio_rate; 1065 clk_i2s->cached_rate = i2s_rate; 1066 *prate = audio_rate; 1067 *calc_rate = i2s_rate; 1068 return; 1069 } 1070 1071 *prate = clk_hw_get_rate(parent); 1072 div = rp1_clock_choose_div(rate, *prate, data); 1073 1074 if (!div) { 1075 *calc_rate = 0; 1076 return; 1077 } 1078 1079 /* Recalculate to account for rounding errors */ 1080 tmp = (u64)*prate << CLK_DIV_FRAC_BITS; 1081 tmp = div_u64(tmp, div); 1082 1083 /* 1084 * Prevent overclocks - if all parent choices result in 1085 * a downstream clock in excess of the maximum, then the 1086 * call to set the clock will fail. 1087 */ 1088 if (tmp > data->max_freq) 1089 *calc_rate = 0; 1090 else 1091 *calc_rate = tmp; 1092} 1093 1094static int rp1_clock_determine_rate(struct clk_hw *hw, 1095 struct clk_rate_request *req) 1096{ 1097 struct clk_hw *parent, *best_parent = NULL; 1098 unsigned long best_rate = 0; 1099 unsigned long best_prate = 0; 1100 unsigned long best_rate_diff = ULONG_MAX; 1101 unsigned long prate, calc_rate; 1102 size_t i; 1103 1104 /* 1105 * If the NO_REPARENT flag is set, try to use existing parent. 1106 */ 1107 if ((clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT)) { 1108 i = rp1_clock_get_parent(hw); 1109 parent = clk_hw_get_parent_by_index(hw, i); 1110 if (parent) { 1111 rp1_clock_choose_div_and_prate(hw, i, req->rate, &prate, 1112 &calc_rate); 1113 if (calc_rate > 0) { 1114 req->best_parent_hw = parent; 1115 req->best_parent_rate = prate; 1116 req->rate = calc_rate; 1117 return 0; 1118 } 1119 } 1120 } 1121 1122 /* 1123 * Select parent clock that results in the closest rate (lower or 1124 * higher) 1125 */ 1126 for (i = 0; i < clk_hw_get_num_parents(hw); i++) { 1127 parent = clk_hw_get_parent_by_index(hw, i); 1128 if (!parent) 1129 continue; 1130 1131 rp1_clock_choose_div_and_prate(hw, i, req->rate, &prate, 1132 &calc_rate); 1133 1134 if (abs_diff(calc_rate, req->rate) < best_rate_diff) { 1135 best_parent = parent; 1136 best_prate = prate; 1137 best_rate = calc_rate; 1138 best_rate_diff = abs_diff(calc_rate, req->rate); 1139 1140 if (best_rate_diff == 0) 1141 break; 1142 } 1143 } 1144 1145 if (best_rate == 0) 1146 return -EINVAL; 1147 1148 req->best_parent_hw = best_parent; 1149 req->best_parent_rate = best_prate; 1150 req->rate = best_rate; 1151 1152 return 0; 1153} 1154 1155static int rp1_varsrc_set_rate(struct clk_hw *hw, 1156 unsigned long rate, unsigned long parent_rate) 1157{ 1158 struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); 1159 1160 /* 1161 * "varsrc" exists purely to let clock dividers know the frequency 1162 * of an externally-managed clock source (such as MIPI DSI byte-clock) 1163 * which may change at run-time as a side-effect of some other driver. 1164 */ 1165 clock->cached_rate = rate; 1166 return 0; 1167} 1168 1169static unsigned long rp1_varsrc_recalc_rate(struct clk_hw *hw, 1170 unsigned long parent_rate) 1171{ 1172 struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); 1173 1174 return clock->cached_rate; 1175} 1176 1177static int rp1_varsrc_determine_rate(struct clk_hw *hw, 1178 struct clk_rate_request *req) 1179{ 1180 return 0; 1181} 1182 1183static const struct clk_ops rp1_pll_core_ops = { 1184 .is_prepared = rp1_pll_core_is_on, 1185 .prepare = rp1_pll_core_on, 1186 .unprepare = rp1_pll_core_off, 1187 .set_rate = rp1_pll_core_set_rate, 1188 .recalc_rate = rp1_pll_core_recalc_rate, 1189 .determine_rate = rp1_pll_core_determine_rate, 1190}; 1191 1192static const struct clk_ops rp1_pll_ops = { 1193 .set_rate = rp1_pll_set_rate, 1194 .recalc_rate = rp1_pll_recalc_rate, 1195 .determine_rate = rp1_pll_determine_rate, 1196}; 1197 1198static const struct clk_ops rp1_pll_ph_ops = { 1199 .is_prepared = rp1_pll_ph_is_on, 1200 .prepare = rp1_pll_ph_on, 1201 .unprepare = rp1_pll_ph_off, 1202 .recalc_rate = rp1_pll_ph_recalc_rate, 1203 .determine_rate = rp1_pll_ph_determine_rate, 1204}; 1205 1206static const struct clk_ops rp1_pll_divider_ops = { 1207 .is_prepared = rp1_pll_divider_is_on, 1208 .prepare = rp1_pll_divider_on, 1209 .unprepare = rp1_pll_divider_off, 1210 .set_rate = rp1_pll_divider_set_rate, 1211 .recalc_rate = rp1_pll_divider_recalc_rate, 1212 .determine_rate = rp1_pll_divider_determine_rate, 1213}; 1214 1215static const struct clk_ops rp1_clk_ops = { 1216 .is_prepared = rp1_clock_is_on, 1217 .prepare = rp1_clock_on, 1218 .unprepare = rp1_clock_off, 1219 .recalc_rate = rp1_clock_recalc_rate, 1220 .get_parent = rp1_clock_get_parent, 1221 .set_parent = rp1_clock_set_parent, 1222 .set_rate_and_parent = rp1_clock_set_rate_and_parent, 1223 .set_rate = rp1_clock_set_rate, 1224 .determine_rate = rp1_clock_determine_rate, 1225}; 1226 1227static const struct clk_ops rp1_varsrc_ops = { 1228 .set_rate = rp1_varsrc_set_rate, 1229 .recalc_rate = rp1_varsrc_recalc_rate, 1230 .determine_rate = rp1_varsrc_determine_rate, 1231}; 1232 1233static struct clk_hw *rp1_register_pll(struct rp1_clockman *clockman, 1234 struct rp1_clk_desc *desc) 1235{ 1236 int ret; 1237 1238 desc->clockman = clockman; 1239 1240 ret = devm_clk_hw_register(clockman->dev, &desc->hw); 1241 if (ret) 1242 return ERR_PTR(ret); 1243 1244 return &desc->hw; 1245} 1246 1247static struct clk_hw *rp1_register_pll_divider(struct rp1_clockman *clockman, 1248 struct rp1_clk_desc *desc) 1249{ 1250 const struct rp1_pll_data *divider_data = desc->data; 1251 int ret; 1252 1253 desc->div.reg = clockman->regs + divider_data->ctrl_reg; 1254 desc->div.shift = __ffs(PLL_SEC_DIV_MASK); 1255 desc->div.width = __ffs(~(PLL_SEC_DIV_MASK >> desc->div.shift)); 1256 desc->div.flags = CLK_DIVIDER_ROUND_CLOSEST; 1257 desc->div.lock = &clockman->regs_lock; 1258 desc->div.hw.init = desc->hw.init; 1259 desc->div.table = pll_sec_div_table; 1260 1261 desc->clockman = clockman; 1262 1263 ret = devm_clk_hw_register(clockman->dev, &desc->div.hw); 1264 if (ret) 1265 return ERR_PTR(ret); 1266 1267 return &desc->div.hw; 1268} 1269 1270static struct clk_hw *rp1_register_clock(struct rp1_clockman *clockman, 1271 struct rp1_clk_desc *desc) 1272{ 1273 const struct rp1_clock_data *clock_data = desc->data; 1274 int ret; 1275 1276 if (WARN_ON_ONCE(MAX_CLK_PARENTS < 1277 clock_data->num_std_parents + clock_data->num_aux_parents)) 1278 return ERR_PTR(-EINVAL); 1279 1280 /* There must be a gap for the AUX selector */ 1281 if (WARN_ON_ONCE(clock_data->num_std_parents > AUX_SEL && 1282 desc->hw.init->parent_data[AUX_SEL].index != -1)) 1283 return ERR_PTR(-EINVAL); 1284 1285 desc->clockman = clockman; 1286 1287 ret = devm_clk_hw_register(clockman->dev, &desc->hw); 1288 if (ret) 1289 return ERR_PTR(ret); 1290 1291 return &desc->hw; 1292} 1293 1294/* Assignment helper macros for different clock types. */ 1295#define _REGISTER(f, ...) { .clk_register = f, __VA_ARGS__ } 1296 1297#define CLK_DATA(type, ...) .data = &(struct type) { __VA_ARGS__ } 1298 1299#define REGISTER_PLL(...) _REGISTER(&rp1_register_pll, \ 1300 __VA_ARGS__) 1301 1302#define REGISTER_PLL_DIV(...) _REGISTER(&rp1_register_pll_divider, \ 1303 __VA_ARGS__) 1304 1305#define REGISTER_CLK(...) _REGISTER(&rp1_register_clock, \ 1306 __VA_ARGS__) 1307 1308static struct rp1_clk_desc pll_sys_core_desc = REGISTER_PLL( 1309 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1310 "pll_sys_core", 1311 (const struct clk_parent_data[]) { { .index = 0 } }, 1312 &rp1_pll_core_ops, 1313 CLK_IS_CRITICAL 1314 ), 1315 CLK_DATA(rp1_pll_core_data, 1316 .cs_reg = PLL_SYS_CS, 1317 .pwr_reg = PLL_SYS_PWR, 1318 .fbdiv_int_reg = PLL_SYS_FBDIV_INT, 1319 .fbdiv_frac_reg = PLL_SYS_FBDIV_FRAC, 1320 ) 1321); 1322 1323static struct rp1_clk_desc pll_audio_core_desc = REGISTER_PLL( 1324 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1325 "pll_audio_core", 1326 (const struct clk_parent_data[]) { { .index = 0 } }, 1327 &rp1_pll_core_ops, 1328 CLK_IS_CRITICAL 1329 ), 1330 CLK_DATA(rp1_pll_core_data, 1331 .cs_reg = PLL_AUDIO_CS, 1332 .pwr_reg = PLL_AUDIO_PWR, 1333 .fbdiv_int_reg = PLL_AUDIO_FBDIV_INT, 1334 .fbdiv_frac_reg = PLL_AUDIO_FBDIV_FRAC, 1335 ) 1336); 1337 1338static struct rp1_clk_desc pll_video_core_desc = REGISTER_PLL( 1339 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1340 "pll_video_core", 1341 (const struct clk_parent_data[]) { { .index = 0 } }, 1342 &rp1_pll_core_ops, 1343 CLK_IS_CRITICAL 1344 ), 1345 CLK_DATA(rp1_pll_core_data, 1346 .cs_reg = PLL_VIDEO_CS, 1347 .pwr_reg = PLL_VIDEO_PWR, 1348 .fbdiv_int_reg = PLL_VIDEO_FBDIV_INT, 1349 .fbdiv_frac_reg = PLL_VIDEO_FBDIV_FRAC, 1350 ) 1351); 1352 1353static struct rp1_clk_desc pll_sys_desc = REGISTER_PLL( 1354 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1355 "pll_sys", 1356 (const struct clk_parent_data[]) { 1357 { .hw = &pll_sys_core_desc.hw } 1358 }, 1359 &rp1_pll_ops, 1360 0 1361 ), 1362 CLK_DATA(rp1_pll_data, 1363 .ctrl_reg = PLL_SYS_PRIM, 1364 .fc0_src = FC_NUM(0, 2), 1365 ) 1366); 1367 1368static struct rp1_clk_desc pll_audio_desc = REGISTER_PLL( 1369 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1370 "pll_audio", 1371 (const struct clk_parent_data[]) { 1372 { .hw = &pll_audio_core_desc.hw } 1373 }, 1374 &rp1_pll_ops, 1375 CLK_SET_RATE_PARENT 1376 ), 1377 CLK_DATA(rp1_pll_data, 1378 .ctrl_reg = PLL_AUDIO_PRIM, 1379 .fc0_src = FC_NUM(4, 2), 1380 ) 1381); 1382 1383static struct rp1_clk_desc pll_video_desc = REGISTER_PLL( 1384 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1385 "pll_video", 1386 (const struct clk_parent_data[]) { 1387 { .hw = &pll_video_core_desc.hw } 1388 }, 1389 &rp1_pll_ops, 1390 0 1391 ), 1392 CLK_DATA(rp1_pll_data, 1393 .ctrl_reg = PLL_VIDEO_PRIM, 1394 .fc0_src = FC_NUM(3, 2), 1395 ) 1396); 1397 1398static struct rp1_clk_desc pll_sys_sec_desc = REGISTER_PLL_DIV( 1399 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1400 "pll_sys_sec", 1401 (const struct clk_parent_data[]) { 1402 { .hw = &pll_sys_core_desc.hw } 1403 }, 1404 &rp1_pll_divider_ops, 1405 0 1406 ), 1407 CLK_DATA(rp1_pll_data, 1408 .ctrl_reg = PLL_SYS_SEC, 1409 .fc0_src = FC_NUM(2, 2), 1410 ) 1411); 1412 1413static struct rp1_clk_desc pll_video_sec_desc = REGISTER_PLL_DIV( 1414 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1415 "pll_video_sec", 1416 (const struct clk_parent_data[]) { 1417 { .hw = &pll_video_core_desc.hw } 1418 }, 1419 &rp1_pll_divider_ops, 1420 0 1421 ), 1422 CLK_DATA(rp1_pll_data, 1423 .ctrl_reg = PLL_VIDEO_SEC, 1424 .fc0_src = FC_NUM(5, 3), 1425 ) 1426); 1427 1428static const struct clk_parent_data clk_eth_tsu_parents[] = { 1429 { .index = 0 }, 1430 { .hw = &pll_video_sec_desc.hw }, 1431 { .index = -1 }, 1432 { .index = -1 }, 1433 { .index = -1 }, 1434 { .index = -1 }, 1435 { .index = -1 }, 1436 { .index = -1 }, 1437}; 1438 1439static struct rp1_clk_desc clk_eth_tsu_desc = REGISTER_CLK( 1440 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1441 "clk_eth_tsu", 1442 clk_eth_tsu_parents, 1443 &rp1_clk_ops, 1444 0 1445 ), 1446 CLK_DATA(rp1_clock_data, 1447 .num_std_parents = 0, 1448 .num_aux_parents = 8, 1449 .ctrl_reg = CLK_ETH_TSU_CTRL, 1450 .div_int_reg = CLK_ETH_TSU_DIV_INT, 1451 .sel_reg = CLK_ETH_TSU_SEL, 1452 .div_int_max = DIV_INT_8BIT_MAX, 1453 .max_freq = 50 * HZ_PER_MHZ, 1454 .fc0_src = FC_NUM(5, 7), 1455 ) 1456); 1457 1458static const struct clk_parent_data clk_eth_parents[] = { 1459 { .hw = &pll_sys_sec_desc.div.hw }, 1460 { .hw = &pll_sys_desc.hw }, 1461 { .hw = &pll_video_sec_desc.hw }, 1462}; 1463 1464static struct rp1_clk_desc clk_eth_desc = REGISTER_CLK( 1465 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1466 "clk_eth", 1467 clk_eth_parents, 1468 &rp1_clk_ops, 1469 0 1470 ), 1471 CLK_DATA(rp1_clock_data, 1472 .num_std_parents = 0, 1473 .num_aux_parents = 3, 1474 .ctrl_reg = CLK_ETH_CTRL, 1475 .div_int_reg = CLK_ETH_DIV_INT, 1476 .sel_reg = CLK_ETH_SEL, 1477 .div_int_max = DIV_INT_8BIT_MAX, 1478 .max_freq = 125 * HZ_PER_MHZ, 1479 .fc0_src = FC_NUM(4, 6), 1480 ) 1481); 1482 1483static const struct clk_parent_data clk_sys_parents[] = { 1484 { .index = 0 }, 1485 { .index = -1 }, 1486 { .hw = &pll_sys_desc.hw }, 1487}; 1488 1489static struct rp1_clk_desc clk_sys_desc = REGISTER_CLK( 1490 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1491 "clk_sys", 1492 clk_sys_parents, 1493 &rp1_clk_ops, 1494 CLK_IS_CRITICAL 1495 ), 1496 CLK_DATA(rp1_clock_data, 1497 .num_std_parents = 3, 1498 .num_aux_parents = 0, 1499 .ctrl_reg = CLK_SYS_CTRL, 1500 .div_int_reg = CLK_SYS_DIV_INT, 1501 .sel_reg = CLK_SYS_SEL, 1502 .div_int_max = DIV_INT_24BIT_MAX, 1503 .max_freq = 200 * HZ_PER_MHZ, 1504 .fc0_src = FC_NUM(0, 4), 1505 .clk_src_mask = 0x3, 1506 ) 1507); 1508 1509static struct rp1_clk_desc pll_sys_pri_ph_desc = REGISTER_PLL( 1510 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1511 "pll_sys_pri_ph", 1512 (const struct clk_parent_data[]) { 1513 { .hw = &pll_sys_desc.hw } 1514 }, 1515 &rp1_pll_ph_ops, 1516 0 1517 ), 1518 CLK_DATA(rp1_pll_ph_data, 1519 .ph_reg = PLL_SYS_PRIM, 1520 .fixed_divider = 2, 1521 .phase = RP1_PLL_PHASE_0, 1522 .fc0_src = FC_NUM(1, 2), 1523 ) 1524); 1525 1526static struct rp1_clk_desc pll_audio_pri_ph_desc = REGISTER_PLL( 1527 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1528 "pll_audio_pri_ph", 1529 (const struct clk_parent_data[]) { 1530 { .hw = &pll_audio_desc.hw } 1531 }, 1532 &rp1_pll_ph_ops, 1533 0 1534 ), 1535 CLK_DATA(rp1_pll_ph_data, 1536 .ph_reg = PLL_AUDIO_PRIM, 1537 .fixed_divider = 2, 1538 .phase = RP1_PLL_PHASE_0, 1539 .fc0_src = FC_NUM(5, 1), 1540 ) 1541); 1542 1543static struct rp1_clk_desc pll_video_pri_ph_desc = REGISTER_PLL( 1544 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1545 "pll_video_pri_ph", 1546 (const struct clk_parent_data[]) { 1547 { .hw = &pll_video_desc.hw } 1548 }, 1549 &rp1_pll_ph_ops, 1550 0 1551 ), 1552 CLK_DATA(rp1_pll_ph_data, 1553 .ph_reg = PLL_VIDEO_PRIM, 1554 .fixed_divider = 2, 1555 .phase = RP1_PLL_PHASE_0, 1556 .fc0_src = FC_NUM(4, 3), 1557 ) 1558); 1559 1560static struct rp1_clk_desc pll_audio_sec_desc = REGISTER_PLL_DIV( 1561 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1562 "pll_audio_sec", 1563 (const struct clk_parent_data[]) { 1564 { .hw = &pll_audio_core_desc.hw } 1565 }, 1566 &rp1_pll_divider_ops, 1567 0 1568 ), 1569 CLK_DATA(rp1_pll_data, 1570 .ctrl_reg = PLL_AUDIO_SEC, 1571 .fc0_src = FC_NUM(6, 2), 1572 ) 1573); 1574 1575static struct rp1_clk_desc pll_audio_tern_desc = REGISTER_PLL_DIV( 1576 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1577 "pll_audio_tern", 1578 (const struct clk_parent_data[]) { 1579 { .hw = &pll_audio_core_desc.hw } 1580 }, 1581 &rp1_pll_divider_ops, 1582 0 1583 ), 1584 CLK_DATA(rp1_pll_data, 1585 .ctrl_reg = PLL_AUDIO_TERN, 1586 .fc0_src = FC_NUM(6, 2), 1587 ) 1588); 1589 1590static struct rp1_clk_desc clk_slow_sys_desc = REGISTER_CLK( 1591 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1592 "clk_slow_sys", 1593 (const struct clk_parent_data[]) { { .index = 0 } }, 1594 &rp1_clk_ops, 1595 CLK_IS_CRITICAL 1596 ), 1597 CLK_DATA(rp1_clock_data, 1598 .num_std_parents = 1, 1599 .num_aux_parents = 0, 1600 .ctrl_reg = CLK_SLOW_SYS_CTRL, 1601 .div_int_reg = CLK_SLOW_SYS_DIV_INT, 1602 .sel_reg = CLK_SLOW_SYS_SEL, 1603 .div_int_max = DIV_INT_8BIT_MAX, 1604 .max_freq = 50 * HZ_PER_MHZ, 1605 .fc0_src = FC_NUM(1, 4), 1606 .clk_src_mask = 0x1, 1607 ) 1608); 1609 1610static const struct clk_parent_data clk_dma_parents[] = { 1611 { .hw = &pll_sys_pri_ph_desc.hw }, 1612 { .hw = &pll_video_desc.hw }, 1613 { .index = 0 }, 1614}; 1615 1616static struct rp1_clk_desc clk_dma_desc = REGISTER_CLK( 1617 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1618 "clk_dma", 1619 clk_dma_parents, 1620 &rp1_clk_ops, 1621 0 1622 ), 1623 CLK_DATA(rp1_clock_data, 1624 .num_std_parents = 0, 1625 .num_aux_parents = 3, 1626 .ctrl_reg = CLK_DMA_CTRL, 1627 .div_int_reg = CLK_DMA_DIV_INT, 1628 .sel_reg = CLK_DMA_SEL, 1629 .div_int_max = DIV_INT_8BIT_MAX, 1630 .max_freq = 100 * HZ_PER_MHZ, 1631 .fc0_src = FC_NUM(2, 2), 1632 ) 1633); 1634 1635static const struct clk_parent_data clk_uart_parents[] = { 1636 { .hw = &pll_sys_pri_ph_desc.hw }, 1637 { .hw = &pll_video_desc.hw }, 1638 { .index = 0 }, 1639}; 1640 1641static struct rp1_clk_desc clk_uart_desc = REGISTER_CLK( 1642 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1643 "clk_uart", 1644 clk_uart_parents, 1645 &rp1_clk_ops, 1646 0 1647 ), 1648 CLK_DATA(rp1_clock_data, 1649 .num_std_parents = 0, 1650 .num_aux_parents = 3, 1651 .ctrl_reg = CLK_UART_CTRL, 1652 .div_int_reg = CLK_UART_DIV_INT, 1653 .sel_reg = CLK_UART_SEL, 1654 .div_int_max = DIV_INT_8BIT_MAX, 1655 .max_freq = 100 * HZ_PER_MHZ, 1656 .fc0_src = FC_NUM(6, 7), 1657 ) 1658); 1659 1660static const struct clk_parent_data clk_pwm0_parents[] = { 1661 { .index = -1 }, 1662 { .hw = &pll_video_sec_desc.hw }, 1663 { .index = 0 }, 1664}; 1665 1666static struct rp1_clk_desc clk_pwm0_desc = REGISTER_CLK( 1667 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1668 "clk_pwm0", 1669 clk_pwm0_parents, 1670 &rp1_clk_ops, 1671 0 1672 ), 1673 CLK_DATA(rp1_clock_data, 1674 .num_std_parents = 0, 1675 .num_aux_parents = 3, 1676 .ctrl_reg = CLK_PWM0_CTRL, 1677 .div_int_reg = CLK_PWM0_DIV_INT, 1678 .div_frac_reg = CLK_PWM0_DIV_FRAC, 1679 .sel_reg = CLK_PWM0_SEL, 1680 .div_int_max = DIV_INT_16BIT_MAX, 1681 .max_freq = 76800 * HZ_PER_KHZ, 1682 .fc0_src = FC_NUM(0, 5), 1683 ) 1684); 1685 1686static const struct clk_parent_data clk_pwm1_parents[] = { 1687 { .index = -1 }, 1688 { .hw = &pll_video_sec_desc.hw }, 1689 { .index = 0 }, 1690}; 1691 1692static struct rp1_clk_desc clk_pwm1_desc = REGISTER_CLK( 1693 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1694 "clk_pwm1", 1695 clk_pwm1_parents, 1696 &rp1_clk_ops, 1697 0 1698 ), 1699 CLK_DATA(rp1_clock_data, 1700 .num_std_parents = 0, 1701 .num_aux_parents = 3, 1702 .ctrl_reg = CLK_PWM1_CTRL, 1703 .div_int_reg = CLK_PWM1_DIV_INT, 1704 .div_frac_reg = CLK_PWM1_DIV_FRAC, 1705 .sel_reg = CLK_PWM1_SEL, 1706 .div_int_max = DIV_INT_16BIT_MAX, 1707 .max_freq = 76800 * HZ_PER_KHZ, 1708 .fc0_src = FC_NUM(1, 5), 1709 ) 1710); 1711 1712static const struct clk_parent_data clk_audio_in_parents[] = { 1713 { .index = -1 }, 1714 { .index = -1 }, 1715 { .index = -1 }, 1716 { .hw = &pll_video_sec_desc.hw }, 1717 { .index = 0 }, 1718}; 1719 1720static struct rp1_clk_desc clk_audio_in_desc = REGISTER_CLK( 1721 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1722 "clk_audio_in", 1723 clk_audio_in_parents, 1724 &rp1_clk_ops, 1725 0 1726 ), 1727 CLK_DATA(rp1_clock_data, 1728 .num_std_parents = 0, 1729 .num_aux_parents = 5, 1730 .ctrl_reg = CLK_AUDIO_IN_CTRL, 1731 .div_int_reg = CLK_AUDIO_IN_DIV_INT, 1732 .sel_reg = CLK_AUDIO_IN_SEL, 1733 .div_int_max = DIV_INT_8BIT_MAX, 1734 .max_freq = 76800 * HZ_PER_KHZ, 1735 .fc0_src = FC_NUM(2, 5), 1736 ) 1737); 1738 1739static const struct clk_parent_data clk_audio_out_parents[] = { 1740 { .index = -1 }, 1741 { .index = -1 }, 1742 { .hw = &pll_video_sec_desc.hw }, 1743 { .index = 0 }, 1744}; 1745 1746static struct rp1_clk_desc clk_audio_out_desc = REGISTER_CLK( 1747 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1748 "clk_audio_out", 1749 clk_audio_out_parents, 1750 &rp1_clk_ops, 1751 0 1752 ), 1753 CLK_DATA(rp1_clock_data, 1754 .num_std_parents = 0, 1755 .num_aux_parents = 4, 1756 .ctrl_reg = CLK_AUDIO_OUT_CTRL, 1757 .div_int_reg = CLK_AUDIO_OUT_DIV_INT, 1758 .sel_reg = CLK_AUDIO_OUT_SEL, 1759 .div_int_max = DIV_INT_8BIT_MAX, 1760 .max_freq = 153600 * HZ_PER_KHZ, 1761 .fc0_src = FC_NUM(3, 5), 1762 ) 1763); 1764 1765static const struct clk_parent_data clk_i2s_parents[] = { 1766 { .index = 0 }, 1767 { .hw = &pll_audio_desc.hw }, 1768 { .hw = &pll_audio_sec_desc.hw }, 1769}; 1770 1771static struct rp1_clk_desc clk_i2s_desc = REGISTER_CLK( 1772 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1773 "clk_i2s", 1774 clk_i2s_parents, 1775 &rp1_clk_ops, 1776 CLK_SET_RATE_PARENT 1777 ), 1778 CLK_DATA(rp1_clock_data, 1779 .num_std_parents = 0, 1780 .num_aux_parents = 3, 1781 .ctrl_reg = CLK_I2S_CTRL, 1782 .div_int_reg = CLK_I2S_DIV_INT, 1783 .sel_reg = CLK_I2S_SEL, 1784 .div_int_max = DIV_INT_8BIT_MAX, 1785 .max_freq = 50 * HZ_PER_MHZ, 1786 .fc0_src = FC_NUM(4, 4), 1787 ) 1788); 1789 1790static struct rp1_clk_desc clk_mipi0_cfg_desc = REGISTER_CLK( 1791 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1792 "clk_mipi0_cfg", 1793 (const struct clk_parent_data[]) { { .index = 0 } }, 1794 &rp1_clk_ops, 1795 0 1796 ), 1797 CLK_DATA(rp1_clock_data, 1798 .num_std_parents = 0, 1799 .num_aux_parents = 1, 1800 .ctrl_reg = CLK_MIPI0_CFG_CTRL, 1801 .div_int_reg = CLK_MIPI0_CFG_DIV_INT, 1802 .sel_reg = CLK_MIPI0_CFG_SEL, 1803 .div_int_max = DIV_INT_8BIT_MAX, 1804 .max_freq = 50 * HZ_PER_MHZ, 1805 .fc0_src = FC_NUM(4, 5), 1806 ) 1807); 1808 1809static struct rp1_clk_desc clk_mipi1_cfg_desc = REGISTER_CLK( 1810 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1811 "clk_mipi1_cfg", 1812 (const struct clk_parent_data[]) { { .index = 0 } }, 1813 &rp1_clk_ops, 1814 0 1815 ), 1816 CLK_DATA(rp1_clock_data, 1817 .num_std_parents = 0, 1818 .num_aux_parents = 1, 1819 .ctrl_reg = CLK_MIPI1_CFG_CTRL, 1820 .div_int_reg = CLK_MIPI1_CFG_DIV_INT, 1821 .sel_reg = CLK_MIPI1_CFG_SEL, 1822 .div_int_max = DIV_INT_8BIT_MAX, 1823 .max_freq = 50 * HZ_PER_MHZ, 1824 .fc0_src = FC_NUM(5, 6), 1825 .clk_src_mask = 0x1, 1826 ) 1827); 1828 1829static struct rp1_clk_desc clk_adc_desc = REGISTER_CLK( 1830 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1831 "clk_adc", 1832 (const struct clk_parent_data[]) { { .index = 0 } }, 1833 &rp1_clk_ops, 1834 0 1835 ), 1836 CLK_DATA(rp1_clock_data, 1837 .num_std_parents = 0, 1838 .num_aux_parents = 1, 1839 .ctrl_reg = CLK_ADC_CTRL, 1840 .div_int_reg = CLK_ADC_DIV_INT, 1841 .sel_reg = CLK_ADC_SEL, 1842 .div_int_max = DIV_INT_8BIT_MAX, 1843 .max_freq = 50 * HZ_PER_MHZ, 1844 .fc0_src = FC_NUM(5, 5), 1845 ) 1846); 1847 1848static struct rp1_clk_desc clk_sdio_timer_desc = REGISTER_CLK( 1849 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1850 "clk_sdio_timer", 1851 (const struct clk_parent_data[]) { { .index = 0 } }, 1852 &rp1_clk_ops, 1853 0 1854 ), 1855 CLK_DATA(rp1_clock_data, 1856 .num_std_parents = 0, 1857 .num_aux_parents = 1, 1858 .ctrl_reg = CLK_SDIO_TIMER_CTRL, 1859 .div_int_reg = CLK_SDIO_TIMER_DIV_INT, 1860 .sel_reg = CLK_SDIO_TIMER_SEL, 1861 .div_int_max = DIV_INT_8BIT_MAX, 1862 .max_freq = 50 * HZ_PER_MHZ, 1863 .fc0_src = FC_NUM(3, 4), 1864 ) 1865); 1866 1867static struct rp1_clk_desc clk_sdio_alt_src_desc = REGISTER_CLK( 1868 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1869 "clk_sdio_alt_src", 1870 (const struct clk_parent_data[]) { 1871 { .hw = &pll_sys_desc.hw } 1872 }, 1873 &rp1_clk_ops, 1874 0 1875 ), 1876 CLK_DATA(rp1_clock_data, 1877 .num_std_parents = 0, 1878 .num_aux_parents = 1, 1879 .ctrl_reg = CLK_SDIO_ALT_SRC_CTRL, 1880 .div_int_reg = CLK_SDIO_ALT_SRC_DIV_INT, 1881 .sel_reg = CLK_SDIO_ALT_SRC_SEL, 1882 .div_int_max = DIV_INT_8BIT_MAX, 1883 .max_freq = 200 * HZ_PER_MHZ, 1884 .fc0_src = FC_NUM(5, 4), 1885 ) 1886); 1887 1888static const struct clk_parent_data clk_dpi_parents[] = { 1889 { .hw = &pll_sys_desc.hw }, 1890 { .hw = &pll_video_sec_desc.hw }, 1891 { .hw = &pll_video_desc.hw }, 1892 { .index = -1 }, 1893 { .index = -1 }, 1894 { .index = -1 }, 1895 { .index = -1 }, 1896 { .index = -1 }, 1897}; 1898 1899static struct rp1_clk_desc clk_dpi_desc = REGISTER_CLK( 1900 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1901 "clk_dpi", 1902 clk_dpi_parents, 1903 &rp1_clk_ops, 1904 CLK_SET_RATE_NO_REPARENT /* Let DPI driver set parent */ 1905 ), 1906 CLK_DATA(rp1_clock_data, 1907 .num_std_parents = 0, 1908 .num_aux_parents = 8, 1909 .ctrl_reg = VIDEO_CLK_DPI_CTRL, 1910 .div_int_reg = VIDEO_CLK_DPI_DIV_INT, 1911 .sel_reg = VIDEO_CLK_DPI_SEL, 1912 .div_int_max = DIV_INT_8BIT_MAX, 1913 .max_freq = 200 * HZ_PER_MHZ, 1914 .fc0_src = FC_NUM(1, 6), 1915 ) 1916); 1917 1918static const struct clk_parent_data clk_gp0_parents[] = { 1919 { .index = 0 }, 1920 { .index = -1 }, 1921 { .index = -1 }, 1922 { .index = -1 }, 1923 { .index = -1 }, 1924 { .index = -1 }, 1925 { .hw = &pll_sys_desc.hw }, 1926 { .index = -1 }, 1927 { .index = -1 }, 1928 { .index = -1 }, 1929 { .hw = &clk_i2s_desc.hw }, 1930 { .hw = &clk_adc_desc.hw }, 1931 { .index = -1 }, 1932 { .index = -1 }, 1933 { .index = -1 }, 1934 { .hw = &clk_sys_desc.hw }, 1935}; 1936 1937static struct rp1_clk_desc clk_gp0_desc = REGISTER_CLK( 1938 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1939 "clk_gp0", 1940 clk_gp0_parents, 1941 &rp1_clk_ops, 1942 0 1943 ), 1944 CLK_DATA(rp1_clock_data, 1945 .num_std_parents = 0, 1946 .num_aux_parents = 16, 1947 .oe_mask = BIT(0), 1948 .ctrl_reg = CLK_GP0_CTRL, 1949 .div_int_reg = CLK_GP0_DIV_INT, 1950 .div_frac_reg = CLK_GP0_DIV_FRAC, 1951 .sel_reg = CLK_GP0_SEL, 1952 .div_int_max = DIV_INT_16BIT_MAX, 1953 .max_freq = 100 * HZ_PER_MHZ, 1954 .fc0_src = FC_NUM(0, 1), 1955 ) 1956); 1957 1958static const struct clk_parent_data clk_gp1_parents[] = { 1959 { .hw = &clk_sdio_timer_desc.hw }, 1960 { .index = -1 }, 1961 { .index = -1 }, 1962 { .index = -1 }, 1963 { .index = -1 }, 1964 { .index = -1 }, 1965 { .hw = &pll_sys_pri_ph_desc.hw }, 1966 { .index = -1 }, 1967 { .index = -1 }, 1968 { .index = -1 }, 1969 { .hw = &clk_adc_desc.hw }, 1970 { .hw = &clk_dpi_desc.hw }, 1971 { .hw = &clk_pwm0_desc.hw }, 1972 { .index = -1 }, 1973 { .index = -1 }, 1974 { .index = -1 }, 1975}; 1976 1977static struct rp1_clk_desc clk_gp1_desc = REGISTER_CLK( 1978 .hw.init = CLK_HW_INIT_PARENTS_DATA( 1979 "clk_gp1", 1980 clk_gp1_parents, 1981 &rp1_clk_ops, 1982 0 1983 ), 1984 CLK_DATA(rp1_clock_data, 1985 .num_std_parents = 0, 1986 .num_aux_parents = 16, 1987 .oe_mask = BIT(1), 1988 .ctrl_reg = CLK_GP1_CTRL, 1989 .div_int_reg = CLK_GP1_DIV_INT, 1990 .div_frac_reg = CLK_GP1_DIV_FRAC, 1991 .sel_reg = CLK_GP1_SEL, 1992 .div_int_max = DIV_INT_16BIT_MAX, 1993 .max_freq = 100 * HZ_PER_MHZ, 1994 .fc0_src = FC_NUM(1, 1), 1995 ) 1996); 1997 1998static struct rp1_clk_desc clksrc_mipi0_dsi_byteclk_desc = REGISTER_CLK( 1999 .hw.init = CLK_HW_INIT_PARENTS_DATA( 2000 "clksrc_mipi0_dsi_byteclk", 2001 (const struct clk_parent_data[]) { { .index = 0 } }, 2002 &rp1_varsrc_ops, 2003 0 2004 ), 2005 CLK_DATA(rp1_clock_data, 2006 .num_std_parents = 1, 2007 .num_aux_parents = 0, 2008 ) 2009); 2010 2011static struct rp1_clk_desc clksrc_mipi1_dsi_byteclk_desc = REGISTER_CLK( 2012 .hw.init = CLK_HW_INIT_PARENTS_DATA( 2013 "clksrc_mipi1_dsi_byteclk", 2014 (const struct clk_parent_data[]) { { .index = 0 } }, 2015 &rp1_varsrc_ops, 2016 0 2017 ), 2018 CLK_DATA(rp1_clock_data, 2019 .num_std_parents = 1, 2020 .num_aux_parents = 0, 2021 ) 2022); 2023 2024static const struct clk_parent_data clk_mipi0_dpi_parents[] = { 2025 { .hw = &pll_sys_desc.hw }, 2026 { .hw = &pll_video_sec_desc.hw }, 2027 { .hw = &pll_video_desc.hw }, 2028 { .hw = &clksrc_mipi0_dsi_byteclk_desc.hw }, 2029 { .index = -1 }, 2030 { .index = -1 }, 2031 { .index = -1 }, 2032 { .index = -1 }, 2033}; 2034 2035static struct rp1_clk_desc clk_mipi0_dpi_desc = REGISTER_CLK( 2036 .hw.init = CLK_HW_INIT_PARENTS_DATA( 2037 "clk_mipi0_dpi", 2038 clk_mipi0_dpi_parents, 2039 &rp1_clk_ops, 2040 CLK_SET_RATE_NO_REPARENT /* Let DSI driver set parent */ 2041 ), 2042 CLK_DATA(rp1_clock_data, 2043 .num_std_parents = 0, 2044 .num_aux_parents = 8, 2045 .ctrl_reg = VIDEO_CLK_MIPI0_DPI_CTRL, 2046 .div_int_reg = VIDEO_CLK_MIPI0_DPI_DIV_INT, 2047 .div_frac_reg = VIDEO_CLK_MIPI0_DPI_DIV_FRAC, 2048 .sel_reg = VIDEO_CLK_MIPI0_DPI_SEL, 2049 .div_int_max = DIV_INT_8BIT_MAX, 2050 .max_freq = 200 * HZ_PER_MHZ, 2051 .fc0_src = FC_NUM(2, 6), 2052 ) 2053); 2054 2055static const struct clk_parent_data clk_mipi1_dpi_parents[] = { 2056 { .hw = &pll_sys_desc.hw }, 2057 { .hw = &pll_video_sec_desc.hw }, 2058 { .hw = &pll_video_desc.hw }, 2059 { .hw = &clksrc_mipi1_dsi_byteclk_desc.hw }, 2060 { .index = -1 }, 2061 { .index = -1 }, 2062 { .index = -1 }, 2063 { .index = -1 }, 2064}; 2065 2066static struct rp1_clk_desc clk_mipi1_dpi_desc = REGISTER_CLK( 2067 .hw.init = CLK_HW_INIT_PARENTS_DATA( 2068 "clk_mipi1_dpi", 2069 clk_mipi1_dpi_parents, 2070 &rp1_clk_ops, 2071 CLK_SET_RATE_NO_REPARENT /* Let DSI driver set parent */ 2072 ), 2073 CLK_DATA(rp1_clock_data, 2074 .num_std_parents = 0, 2075 .num_aux_parents = 8, 2076 .ctrl_reg = VIDEO_CLK_MIPI1_DPI_CTRL, 2077 .div_int_reg = VIDEO_CLK_MIPI1_DPI_DIV_INT, 2078 .div_frac_reg = VIDEO_CLK_MIPI1_DPI_DIV_FRAC, 2079 .sel_reg = VIDEO_CLK_MIPI1_DPI_SEL, 2080 .div_int_max = DIV_INT_8BIT_MAX, 2081 .max_freq = 200 * HZ_PER_MHZ, 2082 .fc0_src = FC_NUM(3, 6), 2083 ) 2084); 2085 2086static const struct clk_parent_data clk_gp2_parents[] = { 2087 { .hw = &clk_sdio_alt_src_desc.hw }, 2088 { .index = -1 }, 2089 { .index = -1 }, 2090 { .index = -1 }, 2091 { .index = -1 }, 2092 { .index = -1 }, 2093 { .hw = &pll_sys_sec_desc.hw }, 2094 { .index = -1 }, 2095 { .hw = &pll_video_desc.hw }, 2096 { .hw = &clk_audio_in_desc.hw }, 2097 { .hw = &clk_dpi_desc.hw }, 2098 { .hw = &clk_pwm0_desc.hw }, 2099 { .hw = &clk_pwm1_desc.hw }, 2100 { .hw = &clk_mipi0_dpi_desc.hw }, 2101 { .hw = &clk_mipi1_cfg_desc.hw }, 2102 { .hw = &clk_sys_desc.hw }, 2103}; 2104 2105static struct rp1_clk_desc clk_gp2_desc = REGISTER_CLK( 2106 .hw.init = CLK_HW_INIT_PARENTS_DATA( 2107 "clk_gp2", 2108 clk_gp2_parents, 2109 &rp1_clk_ops, 2110 0 2111 ), 2112 CLK_DATA(rp1_clock_data, 2113 .num_std_parents = 0, 2114 .num_aux_parents = 16, 2115 .oe_mask = BIT(2), 2116 .ctrl_reg = CLK_GP2_CTRL, 2117 .div_int_reg = CLK_GP2_DIV_INT, 2118 .div_frac_reg = CLK_GP2_DIV_FRAC, 2119 .sel_reg = CLK_GP2_SEL, 2120 .div_int_max = DIV_INT_16BIT_MAX, 2121 .max_freq = 100 * HZ_PER_MHZ, 2122 .fc0_src = FC_NUM(2, 1), 2123 ) 2124); 2125 2126static const struct clk_parent_data clk_gp3_parents[] = { 2127 { .index = 0 }, 2128 { .index = -1 }, 2129 { .index = -1 }, 2130 { .index = -1 }, 2131 { .index = -1 }, 2132 { .index = -1 }, 2133 { .index = -1 }, 2134 { .index = -1 }, 2135 { .hw = &pll_video_pri_ph_desc.hw }, 2136 { .hw = &clk_audio_out_desc.hw }, 2137 { .index = -1 }, 2138 { .index = -1 }, 2139 { .hw = &clk_mipi1_dpi_desc.hw }, 2140 { .index = -1 }, 2141 { .index = -1 }, 2142 { .index = -1 }, 2143}; 2144 2145static struct rp1_clk_desc clk_gp3_desc = REGISTER_CLK( 2146 .hw.init = CLK_HW_INIT_PARENTS_DATA( 2147 "clk_gp3", 2148 clk_gp3_parents, 2149 &rp1_clk_ops, 2150 0 2151 ), 2152 CLK_DATA(rp1_clock_data, 2153 .num_std_parents = 0, 2154 .num_aux_parents = 16, 2155 .oe_mask = BIT(3), 2156 .ctrl_reg = CLK_GP3_CTRL, 2157 .div_int_reg = CLK_GP3_DIV_INT, 2158 .div_frac_reg = CLK_GP3_DIV_FRAC, 2159 .sel_reg = CLK_GP3_SEL, 2160 .div_int_max = DIV_INT_16BIT_MAX, 2161 .max_freq = 100 * HZ_PER_MHZ, 2162 .fc0_src = FC_NUM(3, 1), 2163 ) 2164); 2165 2166static const struct clk_parent_data clk_gp4_parents[] = { 2167 { .index = 0 }, 2168 { .index = -1 }, 2169 { .index = -1 }, 2170 { .index = -1 }, 2171 { .index = -1 }, 2172 { .index = -1 }, 2173 { .index = -1 }, 2174 { .hw = &pll_video_sec_desc.hw }, 2175 { .index = -1 }, 2176 { .index = -1 }, 2177 { .index = -1 }, 2178 { .hw = &clk_mipi0_cfg_desc.hw }, 2179 { .hw = &clk_uart_desc.hw }, 2180 { .index = -1 }, 2181 { .index = -1 }, 2182 { .hw = &clk_sys_desc.hw }, 2183}; 2184 2185static struct rp1_clk_desc clk_gp4_desc = REGISTER_CLK( 2186 .hw.init = CLK_HW_INIT_PARENTS_DATA( 2187 "clk_gp4", 2188 clk_gp4_parents, 2189 &rp1_clk_ops, 2190 0 2191 ), 2192 CLK_DATA(rp1_clock_data, 2193 .num_std_parents = 0, 2194 .num_aux_parents = 16, 2195 .oe_mask = BIT(4), 2196 .ctrl_reg = CLK_GP4_CTRL, 2197 .div_int_reg = CLK_GP4_DIV_INT, 2198 .div_frac_reg = CLK_GP4_DIV_FRAC, 2199 .sel_reg = CLK_GP4_SEL, 2200 .div_int_max = DIV_INT_16BIT_MAX, 2201 .max_freq = 100 * HZ_PER_MHZ, 2202 .fc0_src = FC_NUM(4, 1), 2203 ) 2204); 2205 2206static const struct clk_parent_data clk_vec_parents[] = { 2207 { .hw = &pll_sys_pri_ph_desc.hw }, 2208 { .hw = &pll_video_sec_desc.hw }, 2209 { .hw = &pll_video_desc.hw }, 2210 { .index = -1 }, 2211 { .index = -1 }, 2212 { .index = -1 }, 2213 { .index = -1 }, 2214 { .index = -1 }, 2215}; 2216 2217static struct rp1_clk_desc clk_vec_desc = REGISTER_CLK( 2218 .hw.init = CLK_HW_INIT_PARENTS_DATA( 2219 "clk_vec", 2220 clk_vec_parents, 2221 &rp1_clk_ops, 2222 CLK_SET_RATE_NO_REPARENT /* Let VEC driver set parent */ 2223 ), 2224 CLK_DATA(rp1_clock_data, 2225 .num_std_parents = 0, 2226 .num_aux_parents = 8, 2227 .ctrl_reg = VIDEO_CLK_VEC_CTRL, 2228 .div_int_reg = VIDEO_CLK_VEC_DIV_INT, 2229 .sel_reg = VIDEO_CLK_VEC_SEL, 2230 .div_int_max = DIV_INT_8BIT_MAX, 2231 .max_freq = 108 * HZ_PER_MHZ, 2232 .fc0_src = FC_NUM(0, 6), 2233 ) 2234); 2235 2236static const struct clk_parent_data clk_gp5_parents[] = { 2237 { .index = 0 }, 2238 { .index = -1 }, 2239 { .index = -1 }, 2240 { .index = -1 }, 2241 { .index = -1 }, 2242 { .index = -1 }, 2243 { .index = -1 }, 2244 { .hw = &pll_video_sec_desc.hw }, 2245 { .hw = &clk_eth_tsu_desc.hw }, 2246 { .index = -1 }, 2247 { .hw = &clk_vec_desc.hw }, 2248 { .index = -1 }, 2249 { .index = -1 }, 2250 { .index = -1 }, 2251 { .index = -1 }, 2252 { .index = -1 }, 2253}; 2254 2255static struct rp1_clk_desc clk_gp5_desc = REGISTER_CLK( 2256 .hw.init = CLK_HW_INIT_PARENTS_DATA( 2257 "clk_gp5", 2258 clk_gp5_parents, 2259 &rp1_clk_ops, 2260 0 2261 ), 2262 CLK_DATA(rp1_clock_data, 2263 .num_std_parents = 0, 2264 .num_aux_parents = 16, 2265 .oe_mask = BIT(5), 2266 .ctrl_reg = CLK_GP5_CTRL, 2267 .div_int_reg = CLK_GP5_DIV_INT, 2268 .div_frac_reg = CLK_GP5_DIV_FRAC, 2269 .sel_reg = CLK_GP5_SEL, 2270 .div_int_max = DIV_INT_16BIT_MAX, 2271 .max_freq = 100 * HZ_PER_MHZ, 2272 .fc0_src = FC_NUM(5, 1), 2273 ) 2274); 2275 2276static struct rp1_clk_desc *const clk_desc_array[] = { 2277 [RP1_PLL_SYS_CORE] = &pll_sys_core_desc, 2278 [RP1_PLL_AUDIO_CORE] = &pll_audio_core_desc, 2279 [RP1_PLL_VIDEO_CORE] = &pll_video_core_desc, 2280 [RP1_PLL_SYS] = &pll_sys_desc, 2281 [RP1_CLK_ETH_TSU] = &clk_eth_tsu_desc, 2282 [RP1_CLK_ETH] = &clk_eth_desc, 2283 [RP1_CLK_SYS] = &clk_sys_desc, 2284 [RP1_PLL_SYS_PRI_PH] = &pll_sys_pri_ph_desc, 2285 [RP1_PLL_SYS_SEC] = &pll_sys_sec_desc, 2286 [RP1_PLL_AUDIO] = &pll_audio_desc, 2287 [RP1_PLL_VIDEO] = &pll_video_desc, 2288 [RP1_PLL_AUDIO_PRI_PH] = &pll_audio_pri_ph_desc, 2289 [RP1_PLL_VIDEO_PRI_PH] = &pll_video_pri_ph_desc, 2290 [RP1_PLL_AUDIO_SEC] = &pll_audio_sec_desc, 2291 [RP1_PLL_VIDEO_SEC] = &pll_video_sec_desc, 2292 [RP1_PLL_AUDIO_TERN] = &pll_audio_tern_desc, 2293 [RP1_CLK_SLOW_SYS] = &clk_slow_sys_desc, 2294 [RP1_CLK_DMA] = &clk_dma_desc, 2295 [RP1_CLK_UART] = &clk_uart_desc, 2296 [RP1_CLK_PWM0] = &clk_pwm0_desc, 2297 [RP1_CLK_PWM1] = &clk_pwm1_desc, 2298 [RP1_CLK_AUDIO_IN] = &clk_audio_in_desc, 2299 [RP1_CLK_AUDIO_OUT] = &clk_audio_out_desc, 2300 [RP1_CLK_I2S] = &clk_i2s_desc, 2301 [RP1_CLK_MIPI0_CFG] = &clk_mipi0_cfg_desc, 2302 [RP1_CLK_MIPI1_CFG] = &clk_mipi1_cfg_desc, 2303 [RP1_CLK_ADC] = &clk_adc_desc, 2304 [RP1_CLK_SDIO_TIMER] = &clk_sdio_timer_desc, 2305 [RP1_CLK_SDIO_ALT_SRC] = &clk_sdio_alt_src_desc, 2306 [RP1_CLK_GP0] = &clk_gp0_desc, 2307 [RP1_CLK_GP1] = &clk_gp1_desc, 2308 [RP1_CLK_GP2] = &clk_gp2_desc, 2309 [RP1_CLK_GP3] = &clk_gp3_desc, 2310 [RP1_CLK_GP4] = &clk_gp4_desc, 2311 [RP1_CLK_GP5] = &clk_gp5_desc, 2312 [RP1_CLK_VEC] = &clk_vec_desc, 2313 [RP1_CLK_DPI] = &clk_dpi_desc, 2314 [RP1_CLK_MIPI0_DPI] = &clk_mipi0_dpi_desc, 2315 [RP1_CLK_MIPI1_DPI] = &clk_mipi1_dpi_desc, 2316 [RP1_CLK_MIPI0_DSI_BYTECLOCK] = &clksrc_mipi0_dsi_byteclk_desc, 2317 [RP1_CLK_MIPI1_DSI_BYTECLOCK] = &clksrc_mipi1_dsi_byteclk_desc, 2318}; 2319 2320static const struct regmap_range rp1_reg_ranges[] = { 2321 regmap_reg_range(PLL_SYS_CS, PLL_SYS_SEC), 2322 regmap_reg_range(PLL_AUDIO_CS, PLL_AUDIO_TERN), 2323 regmap_reg_range(PLL_VIDEO_CS, PLL_VIDEO_SEC), 2324 regmap_reg_range(GPCLK_OE_CTRL, GPCLK_OE_CTRL), 2325 regmap_reg_range(CLK_SYS_CTRL, CLK_SYS_DIV_INT), 2326 regmap_reg_range(CLK_SYS_SEL, CLK_SYS_SEL), 2327 regmap_reg_range(CLK_SLOW_SYS_CTRL, CLK_SLOW_SYS_DIV_INT), 2328 regmap_reg_range(CLK_SLOW_SYS_SEL, CLK_SLOW_SYS_SEL), 2329 regmap_reg_range(CLK_DMA_CTRL, CLK_DMA_DIV_INT), 2330 regmap_reg_range(CLK_DMA_SEL, CLK_DMA_SEL), 2331 regmap_reg_range(CLK_UART_CTRL, CLK_UART_DIV_INT), 2332 regmap_reg_range(CLK_UART_SEL, CLK_UART_SEL), 2333 regmap_reg_range(CLK_ETH_CTRL, CLK_ETH_DIV_INT), 2334 regmap_reg_range(CLK_ETH_SEL, CLK_ETH_SEL), 2335 regmap_reg_range(CLK_PWM0_CTRL, CLK_PWM0_SEL), 2336 regmap_reg_range(CLK_PWM1_CTRL, CLK_PWM1_SEL), 2337 regmap_reg_range(CLK_AUDIO_IN_CTRL, CLK_AUDIO_IN_DIV_INT), 2338 regmap_reg_range(CLK_AUDIO_IN_SEL, CLK_AUDIO_IN_SEL), 2339 regmap_reg_range(CLK_AUDIO_OUT_CTRL, CLK_AUDIO_OUT_DIV_INT), 2340 regmap_reg_range(CLK_AUDIO_OUT_SEL, CLK_AUDIO_OUT_SEL), 2341 regmap_reg_range(CLK_I2S_CTRL, CLK_I2S_DIV_INT), 2342 regmap_reg_range(CLK_I2S_SEL, CLK_I2S_SEL), 2343 regmap_reg_range(CLK_MIPI0_CFG_CTRL, CLK_MIPI0_CFG_DIV_INT), 2344 regmap_reg_range(CLK_MIPI0_CFG_SEL, CLK_MIPI0_CFG_SEL), 2345 regmap_reg_range(CLK_MIPI1_CFG_CTRL, CLK_MIPI1_CFG_DIV_INT), 2346 regmap_reg_range(CLK_MIPI1_CFG_SEL, CLK_MIPI1_CFG_SEL), 2347 regmap_reg_range(CLK_PCIE_AUX_CTRL, CLK_PCIE_AUX_DIV_INT), 2348 regmap_reg_range(CLK_PCIE_AUX_SEL, CLK_PCIE_AUX_SEL), 2349 regmap_reg_range(CLK_USBH0_MICROFRAME_CTRL, CLK_USBH0_MICROFRAME_DIV_INT), 2350 regmap_reg_range(CLK_USBH0_MICROFRAME_SEL, CLK_USBH0_MICROFRAME_SEL), 2351 regmap_reg_range(CLK_USBH1_MICROFRAME_CTRL, CLK_USBH1_MICROFRAME_DIV_INT), 2352 regmap_reg_range(CLK_USBH1_MICROFRAME_SEL, CLK_USBH1_MICROFRAME_SEL), 2353 regmap_reg_range(CLK_USBH0_SUSPEND_CTRL, CLK_USBH0_SUSPEND_DIV_INT), 2354 regmap_reg_range(CLK_USBH0_SUSPEND_SEL, CLK_USBH0_SUSPEND_SEL), 2355 regmap_reg_range(CLK_USBH1_SUSPEND_CTRL, CLK_USBH1_SUSPEND_DIV_INT), 2356 regmap_reg_range(CLK_USBH1_SUSPEND_SEL, CLK_USBH1_SUSPEND_SEL), 2357 regmap_reg_range(CLK_ETH_TSU_CTRL, CLK_ETH_TSU_DIV_INT), 2358 regmap_reg_range(CLK_ETH_TSU_SEL, CLK_ETH_TSU_SEL), 2359 regmap_reg_range(CLK_ADC_CTRL, CLK_ADC_DIV_INT), 2360 regmap_reg_range(CLK_ADC_SEL, CLK_ADC_SEL), 2361 regmap_reg_range(CLK_SDIO_TIMER_CTRL, CLK_SDIO_TIMER_DIV_INT), 2362 regmap_reg_range(CLK_SDIO_TIMER_SEL, CLK_SDIO_TIMER_SEL), 2363 regmap_reg_range(CLK_SDIO_ALT_SRC_CTRL, CLK_SDIO_ALT_SRC_DIV_INT), 2364 regmap_reg_range(CLK_SDIO_ALT_SRC_SEL, CLK_SDIO_ALT_SRC_SEL), 2365 regmap_reg_range(CLK_GP0_CTRL, CLK_GP0_SEL), 2366 regmap_reg_range(CLK_GP1_CTRL, CLK_GP1_SEL), 2367 regmap_reg_range(CLK_GP2_CTRL, CLK_GP2_SEL), 2368 regmap_reg_range(CLK_GP3_CTRL, CLK_GP3_SEL), 2369 regmap_reg_range(CLK_GP4_CTRL, CLK_GP4_SEL), 2370 regmap_reg_range(CLK_GP5_CTRL, CLK_GP5_SEL), 2371 regmap_reg_range(CLK_SYS_RESUS_CTRL, CLK_SYS_RESUS_CTRL), 2372 regmap_reg_range(CLK_SLOW_SYS_RESUS_CTRL, CLK_SLOW_SYS_RESUS_CTRL), 2373 regmap_reg_range(FC0_REF_KHZ, FC0_RESULT), 2374 regmap_reg_range(VIDEO_CLK_VEC_CTRL, VIDEO_CLK_VEC_DIV_INT), 2375 regmap_reg_range(VIDEO_CLK_VEC_SEL, VIDEO_CLK_DPI_DIV_INT), 2376 regmap_reg_range(VIDEO_CLK_DPI_SEL, VIDEO_CLK_MIPI1_DPI_SEL), 2377}; 2378 2379static const struct regmap_access_table rp1_reg_table = { 2380 .yes_ranges = rp1_reg_ranges, 2381 .n_yes_ranges = ARRAY_SIZE(rp1_reg_ranges), 2382}; 2383 2384static const struct regmap_config rp1_clk_regmap_cfg = { 2385 .reg_bits = 32, 2386 .val_bits = 32, 2387 .reg_stride = 4, 2388 .max_register = PLL_VIDEO_SEC, 2389 .name = "rp1-clk", 2390 .rd_table = &rp1_reg_table, 2391 .disable_locking = true, 2392}; 2393 2394static int rp1_clk_probe(struct platform_device *pdev) 2395{ 2396 const size_t asize = ARRAY_SIZE(clk_desc_array); 2397 struct rp1_clk_desc *desc; 2398 struct device *dev = &pdev->dev; 2399 struct rp1_clockman *clockman; 2400 struct clk_hw **hws; 2401 unsigned int i; 2402 2403 clockman = devm_kzalloc(dev, struct_size(clockman, onecell.hws, asize), 2404 GFP_KERNEL); 2405 if (!clockman) 2406 return -ENOMEM; 2407 2408 spin_lock_init(&clockman->regs_lock); 2409 clockman->dev = dev; 2410 2411 clockman->regs = devm_platform_ioremap_resource(pdev, 0); 2412 if (IS_ERR(clockman->regs)) 2413 return PTR_ERR(clockman->regs); 2414 2415 clockman->regmap = devm_regmap_init_mmio(dev, clockman->regs, 2416 &rp1_clk_regmap_cfg); 2417 if (IS_ERR(clockman->regmap)) { 2418 dev_err_probe(dev, PTR_ERR(clockman->regmap), 2419 "could not init clock regmap\n"); 2420 return PTR_ERR(clockman->regmap); 2421 } 2422 2423 clockman->onecell.num = asize; 2424 hws = clockman->onecell.hws; 2425 2426 for (i = 0; i < asize; i++) { 2427 desc = clk_desc_array[i]; 2428 if (desc && desc->clk_register && desc->data) 2429 hws[i] = desc->clk_register(clockman, desc); 2430 } 2431 2432 clk_audio_core = &pll_audio_core_desc; 2433 clk_audio = &pll_audio_desc; 2434 clk_i2s = &clk_i2s_desc; 2435 clk_xosc = clk_hw_get_parent_by_index(&clk_i2s->hw, 0); 2436 2437 platform_set_drvdata(pdev, clockman); 2438 2439 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 2440 &clockman->onecell); 2441} 2442 2443static const struct of_device_id rp1_clk_of_match[] = { 2444 { .compatible = "raspberrypi,rp1-clocks" }, 2445 {} 2446}; 2447MODULE_DEVICE_TABLE(of, rp1_clk_of_match); 2448 2449static struct platform_driver rp1_clk_driver = { 2450 .driver = { 2451 .name = "rp1-clk", 2452 .of_match_table = rp1_clk_of_match, 2453 }, 2454 .probe = rp1_clk_probe, 2455}; 2456 2457module_platform_driver(rp1_clk_driver); 2458 2459MODULE_AUTHOR("Naushir Patuck <naush@raspberrypi.com>"); 2460MODULE_AUTHOR("Andrea della Porta <andrea.porta@suse.com>"); 2461MODULE_DESCRIPTION("RP1 clock driver"); 2462MODULE_LICENSE("GPL");
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