clk-lmk04832.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
   4 * Pin compatible with the LMK0482x family
   5 *
   6 * Datasheet: https://www.ti.com/lit/ds/symlink/lmk04832.pdf
   7 *
   8 * Copyright (c) 2020, Xiphos Systems Corp.
   9 *
  10 */
  11
  12#include <linux/bitfield.h>
  13#include <linux/clk.h>
  14#include <linux/clk-provider.h>
  15#include <linux/device.h>
  16#include <linux/gcd.h>
  17#include <linux/gpio/consumer.h>
  18#include <linux/module.h>
  19#include <linux/regmap.h>
  20#include <linux/spi/spi.h>
  21
  22/* 0x000 - 0x00d System Functions */
  23#define LMK04832_REG_RST3W		0x000
  24#define LMK04832_BIT_RESET			BIT(7)
  25#define LMK04832_BIT_SPI_3WIRE_DIS		BIT(4)
  26#define LMK04832_REG_POWERDOWN		0x002
  27#define LMK04832_REG_ID_DEV_TYPE	0x003
  28#define LMK04832_REG_ID_PROD_MSB	0x004
  29#define LMK04832_REG_ID_PROD_LSB	0x005
  30#define LMK04832_REG_ID_MASKREV		0x006
  31#define LMK04832_REG_ID_VNDR_MSB	0x00c
  32#define LMK04832_REG_ID_VNDR_LSB	0x00d
  33
  34/* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
  35#define LMK04832_REG_CLKOUT_CTRL0(ch)	(0x100 + (ch >> 1) * 8)
  36#define LMK04832_BIT_DCLK_DIV_LSB		GENMASK(7, 0)
  37#define LMK04832_REG_CLKOUT_CTRL1(ch)	(0x101 + (ch >> 1) * 8)
  38#define LMK04832_BIT_DCLKX_Y_DDLY_LSB		GENMASK(7, 0)
  39#define LMK04832_REG_CLKOUT_CTRL2(ch)	(0x102 + (ch >> 1) * 8)
  40#define LMK04832_BIT_CLKOUTX_Y_PD		BIT(7)
  41#define LMK04832_BIT_DCLKX_Y_DDLY_PD		BIT(4)
  42#define LMK04832_BIT_DCLKX_Y_DDLY_MSB		GENMASK(3, 2)
  43#define LMK04832_BIT_DCLK_DIV_MSB		GENMASK(1, 0)
  44#define LMK04832_REG_CLKOUT_SRC_MUX(ch)	(0x103 + (ch % 2) + (ch >> 1) * 8)
  45#define LMK04832_BIT_CLKOUT_SRC_MUX		BIT(5)
  46#define LMK04832_REG_CLKOUT_CTRL3(ch)	(0x103 + (ch >> 1) * 8)
  47#define LMK04832_BIT_DCLKX_Y_PD			BIT(4)
  48#define LMK04832_BIT_DCLKX_Y_DCC		BIT(2)
  49#define LMK04832_BIT_DCLKX_Y_HS			BIT(0)
  50#define LMK04832_REG_CLKOUT_CTRL4(ch)	(0x104 + (ch >> 1) * 8)
  51#define LMK04832_BIT_SCLK_PD			BIT(4)
  52#define LMK04832_BIT_SCLKX_Y_DIS_MODE		GENMASK(3, 2)
  53#define LMK04832_REG_SCLKX_Y_ADLY(ch)	(0x105 + (ch >> 1) * 8)
  54#define LMK04832_REG_SCLKX_Y_DDLY(ch)	(0x106 + (ch >> 1) * 8)
  55#define LMK04832_BIT_SCLKX_Y_DDLY		GENMASK(3, 0)
  56#define LMK04832_REG_CLKOUT_FMT(ch)	(0x107 + (ch >> 1) * 8)
  57#define LMK04832_BIT_CLKOUT_FMT(ch)		(ch % 2 ? 0xf0 : 0x0f)
  58#define LMK04832_VAL_CLKOUT_FMT_POWERDOWN		0x00
  59#define LMK04832_VAL_CLKOUT_FMT_LVDS			0x01
  60#define LMK04832_VAL_CLKOUT_FMT_HSDS6			0x02
  61#define LMK04832_VAL_CLKOUT_FMT_HSDS8			0x03
  62#define LMK04832_VAL_CLKOUT_FMT_LVPECL1600		0x04
  63#define LMK04832_VAL_CLKOUT_FMT_LVPECL2000		0x05
  64#define LMK04832_VAL_CLKOUT_FMT_LCPECL			0x06
  65#define LMK04832_VAL_CLKOUT_FMT_CML16			0x07
  66#define LMK04832_VAL_CLKOUT_FMT_CML24			0x08
  67#define LMK04832_VAL_CLKOUT_FMT_CML32			0x09
  68#define LMK04832_VAL_CLKOUT_FMT_CMOS_OFF_INV		0x0a
  69#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_OFF		0x0b
  70#define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_INV		0x0c
  71#define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_NOR		0x0d
  72#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_INV		0x0e
  73#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_NOR		0x0f
  74
  75/* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
  76#define LMK04832_REG_VCO_OSCOUT		0x138
  77#define LMK04832_BIT_VCO_MUX			GENMASK(6, 5)
  78#define LMK04832_VAL_VCO_MUX_VCO0			0x00
  79#define LMK04832_VAL_VCO_MUX_VCO1			0x01
  80#define LMK04832_VAL_VCO_MUX_EXT			0x02
  81#define LMK04832_REG_SYSREF_OUT		0x139
  82#define LMK04832_BIT_SYSREF_REQ_EN		BIT(6)
  83#define LMK04832_BIT_SYSREF_MUX			GENMASK(1, 0)
  84#define LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC		0x00
  85#define LMK04832_VAL_SYSREF_MUX_RECLK			0x01
  86#define LMK04832_VAL_SYSREF_MUX_PULSER			0x02
  87#define LMK04832_VAL_SYSREF_MUX_CONTINUOUS		0x03
  88#define LMK04832_REG_SYSREF_DIV_MSB	0x13a
  89#define LMK04832_BIT_SYSREF_DIV_MSB		GENMASK(4, 0)
  90#define LMK04832_REG_SYSREF_DIV_LSB	0x13b
  91#define LMK04832_REG_SYSREF_DDLY_MSB	0x13c
  92#define LMK04832_BIT_SYSREF_DDLY_MSB		GENMASK(4, 0)
  93#define LMK04832_REG_SYSREF_DDLY_LSB	0x13d
  94#define LMK04832_REG_SYSREF_PULSE_CNT	0x13e
  95#define LMK04832_REG_FB_CTRL		0x13f
  96#define LMK04832_BIT_PLL2_RCLK_MUX		BIT(7)
  97#define LMK04832_VAL_PLL2_RCLK_MUX_OSCIN		0x00
  98#define LMK04832_VAL_PLL2_RCLK_MUX_CLKIN		0x01
  99#define LMK04832_BIT_PLL2_NCLK_MUX		BIT(5)
 100#define LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P		0x00
 101#define LMK04832_VAL_PLL2_NCLK_MUX_FB_MUX		0x01
 102#define LMK04832_BIT_FB_MUX_EN			BIT(0)
 103#define LMK04832_REG_MAIN_PD		0x140
 104#define LMK04832_BIT_PLL1_PD			BIT(7)
 105#define LMK04832_BIT_VCO_LDO_PD			BIT(6)
 106#define LMK04832_BIT_VCO_PD			BIT(5)
 107#define LMK04832_BIT_OSCIN_PD			BIT(4)
 108#define LMK04832_BIT_SYSREF_GBL_PD		BIT(3)
 109#define LMK04832_BIT_SYSREF_PD			BIT(2)
 110#define LMK04832_BIT_SYSREF_DDLY_PD		BIT(1)
 111#define LMK04832_BIT_SYSREF_PLSR_PD		BIT(0)
 112#define LMK04832_REG_SYNC		0x143
 113#define LMK04832_BIT_SYNC_CLR			BIT(7)
 114#define LMK04832_BIT_SYNC_1SHOT_EN		BIT(6)
 115#define LMK04832_BIT_SYNC_POL			BIT(5)
 116#define LMK04832_BIT_SYNC_EN			BIT(4)
 117#define LMK04832_BIT_SYNC_MODE			GENMASK(1, 0)
 118#define LMK04832_VAL_SYNC_MODE_OFF			0x00
 119#define LMK04832_VAL_SYNC_MODE_ON			0x01
 120#define LMK04832_VAL_SYNC_MODE_PULSER_PIN		0x02
 121#define LMK04832_VAL_SYNC_MODE_PULSER_SPI		0x03
 122#define LMK04832_REG_SYNC_DIS		0x144
 123
 124/* 0x146 - 0x14a CLKin Control */
 125#define LMK04832_REG_CLKIN_SEL0		0x148
 126#define LMK04832_REG_CLKIN_SEL1		0x149
 127#define LMK04832_REG_CLKIN_RST		0x14a
 128#define LMK04832_BIT_SDIO_RDBK_TYPE		BIT(6)
 129#define LMK04832_BIT_CLKIN_SEL_MUX		GENMASK(5, 3)
 130#define LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK		0x06
 131#define LMK04832_BIT_CLKIN_SEL_TYPE		GENMASK(2, 0)
 132#define LMK04832_VAL_CLKIN_SEL_TYPE_OUT			0x03
 133
 134/* 0x14b - 0x152 Holdover */
 135
 136/* 0x153 - 0x15f PLL1 Configuration */
 137#define LMK04832_REG_PLL1_LD		0x15f
 138#define LMK04832_BIT_PLL1_LD_MUX		GENMASK(7, 3)
 139#define LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK		0x07
 140#define LMK04832_BIT_PLL1_LD_TYPE		GENMASK(2, 0)
 141#define LMK04832_VAL_PLL1_LD_TYPE_OUT_PP		0x03
 142
 143/* 0x160 - 0x16e PLL2 Configuration */
 144#define LMK04832_REG_PLL2_R_MSB		0x160
 145#define LMK04832_BIT_PLL2_R_MSB			GENMASK(3, 0)
 146#define LMK04832_REG_PLL2_R_LSB		0x161
 147#define LMK04832_REG_PLL2_MISC		0x162
 148#define LMK04832_BIT_PLL2_MISC_P		GENMASK(7, 5)
 149#define LMK04832_BIT_PLL2_MISC_REF_2X_EN	BIT(0)
 150#define LMK04832_REG_PLL2_N_CAL_0	0x163
 151#define LMK04832_BIT_PLL2_N_CAL_0		GENMASK(1, 0)
 152#define LMK04832_REG_PLL2_N_CAL_1	0x164
 153#define LMK04832_REG_PLL2_N_CAL_2	0x165
 154#define LMK04832_REG_PLL2_N_0		0x166
 155#define LMK04832_BIT_PLL2_N_0			GENMASK(1, 0)
 156#define LMK04832_REG_PLL2_N_1		0x167
 157#define LMK04832_REG_PLL2_N_2		0x168
 158#define LMK04832_REG_PLL2_DLD_CNT_MSB	0x16a
 159#define LMK04832_REG_PLL2_DLD_CNT_LSB	0x16b
 160#define LMK04832_REG_PLL2_LD		0x16e
 161#define LMK04832_BIT_PLL2_LD_MUX		GENMASK(7, 3)
 162#define LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD		0x02
 163#define LMK04832_BIT_PLL2_LD_TYPE		GENMASK(2, 0)
 164#define LMK04832_VAL_PLL2_LD_TYPE_OUT_PP		0x03
 165
 166/* 0x16F - 0x555 Misc Registers */
 167#define LMK04832_REG_PLL2_PD		0x173
 168#define LMK04832_BIT_PLL2_PRE_PD		BIT(6)
 169#define LMK04832_BIT_PLL2_PD			BIT(5)
 170#define LMK04832_REG_PLL1R_RST		0x177
 171#define LMK04832_REG_CLR_PLL_LOST	0x182
 172#define LMK04832_REG_RB_PLL_LD		0x183
 173#define LMK04832_REG_RB_CLK_DAC_VAL_MSB	0x184
 174#define LMK04832_REG_RB_DAC_VAL_LSB	0x185
 175#define LMK04832_REG_RB_HOLDOVER	0x188
 176#define LMK04832_REG_SPI_LOCK		0x555
 177
 178enum lmk04832_device_types {
 179	LMK04832,
 180};
 181
 182/**
 183 * struct lmk04832_device_info - Holds static device information that is
 184 *                               specific to the chip revision
 185 *
 186 * @pid:          Product Identifier
 187 * @maskrev:      IC version identifier
 188 * @num_channels: Number of available output channels (clkout count)
 189 * @vco0_range:   {min, max} of the VCO0 operating range (in MHz)
 190 * @vco1_range:   {min, max} of the VCO1 operating range (in MHz)
 191 */
 192struct lmk04832_device_info {
 193	u16 pid;
 194	u8 maskrev;
 195	size_t num_channels;
 196	unsigned int vco0_range[2];
 197	unsigned int vco1_range[2];
 198};
 199
 200static const struct lmk04832_device_info lmk04832_device_info[] = {
 201	[LMK04832] = {
 202		.pid = 0x63d1, /* WARNING PROD_ID is inverted in the datasheet */
 203		.maskrev = 0x70,
 204		.num_channels = 14,
 205		.vco0_range = { 2440, 2580 },
 206		.vco1_range = { 2945, 3255 },
 207	},
 208};
 209
 210enum lmk04832_rdbk_type {
 211	RDBK_CLKIN_SEL0,
 212	RDBK_CLKIN_SEL1,
 213	RDBK_RESET,
 214	RDBK_PLL1_LD,
 215};
 216
 217struct lmk_dclk {
 218	struct lmk04832 *lmk;
 219	struct clk_hw hw;
 220	u8 id;
 221};
 222
 223struct lmk_clkout {
 224	struct lmk04832 *lmk;
 225	struct clk_hw hw;
 226	bool sysref;
 227	u32 format;
 228	u8 id;
 229};
 230
 231/**
 232 * struct lmk04832 - The LMK04832 device structure
 233 *
 234 * @dev: reference to a struct device, linked to the spi_device
 235 * @regmap: struct regmap instance use to access the chip
 236 * @sync_mode: operational mode for SYNC signal
 237 * @sysref_mux: select SYSREF source
 238 * @sysref_pulse_cnt: number of SYSREF pulses generated while not in continuous
 239 *                    mode.
 240 * @sysref_ddly: SYSREF digital delay value
 241 * @oscin: PLL2 input clock
 242 * @vco: reference to the internal VCO clock
 243 * @sclk: reference to the internal sysref clock (SCLK)
 244 * @vco_rate: user provided VCO rate
 245 * @reset_gpio: reference to the reset GPIO
 246 * @dclk: list of internal device clock references.
 247 *        Each pair of clkout clocks share a single device clock (DCLKX_Y)
 248 * @clkout: list of output clock references
 249 * @clk_data: holds clkout related data like clk_hw* and number of clocks
 250 */
 251struct lmk04832 {
 252	struct device *dev;
 253	struct regmap *regmap;
 254
 255	unsigned int sync_mode;
 256	unsigned int sysref_mux;
 257	unsigned int sysref_pulse_cnt;
 258	unsigned int sysref_ddly;
 259
 260	struct clk *oscin;
 261	struct clk_hw vco;
 262	struct clk_hw sclk;
 263	unsigned int vco_rate;
 264
 265	struct gpio_desc *reset_gpio;
 266
 267	struct lmk_dclk *dclk;
 268	struct lmk_clkout *clkout;
 269	struct clk_hw_onecell_data *clk_data;
 270};
 271
 272static bool lmk04832_regmap_rd_regs(struct device *dev, unsigned int reg)
 273{
 274	switch (reg) {
 275	case LMK04832_REG_RST3W ... LMK04832_REG_ID_MASKREV:
 276	case LMK04832_REG_ID_VNDR_MSB:
 277	case LMK04832_REG_ID_VNDR_LSB:
 278	case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB:
 279	case LMK04832_REG_PLL2_LD:
 280	case LMK04832_REG_PLL2_PD:
 281	case LMK04832_REG_PLL1R_RST:
 282	case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB:
 283	case LMK04832_REG_RB_HOLDOVER:
 284	case LMK04832_REG_SPI_LOCK:
 285		return true;
 286	default:
 287		return false;
 288	};
 289}
 290
 291static bool lmk04832_regmap_wr_regs(struct device *dev, unsigned int reg)
 292{
 293	switch (reg) {
 294	case LMK04832_REG_RST3W:
 295	case LMK04832_REG_POWERDOWN:
 296		return true;
 297	case LMK04832_REG_ID_DEV_TYPE ... LMK04832_REG_ID_MASKREV:
 298	case LMK04832_REG_ID_VNDR_MSB:
 299	case LMK04832_REG_ID_VNDR_LSB:
 300		return false;
 301	case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB:
 302	case LMK04832_REG_PLL2_LD:
 303	case LMK04832_REG_PLL2_PD:
 304	case LMK04832_REG_PLL1R_RST:
 305	case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB:
 306	case LMK04832_REG_RB_HOLDOVER:
 307	case LMK04832_REG_SPI_LOCK:
 308		return true;
 309	default:
 310		return false;
 311	};
 312}
 313
 314static const struct regmap_config regmap_config = {
 315	.name = "lmk04832",
 316	.reg_bits = 16,
 317	.val_bits = 8,
 318	.use_single_read = 1,
 319	.use_single_write = 1,
 320	.read_flag_mask = 0x80,
 321	.write_flag_mask = 0x00,
 322	.readable_reg = lmk04832_regmap_rd_regs,
 323	.writeable_reg = lmk04832_regmap_wr_regs,
 324	.cache_type = REGCACHE_NONE,
 325	.max_register = LMK04832_REG_SPI_LOCK,
 326};
 327
 328static int lmk04832_vco_is_enabled(struct clk_hw *hw)
 329{
 330	struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
 331	unsigned int tmp;
 332	int ret;
 333
 334	ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp);
 335	if (ret)
 336		return ret;
 337
 338	return !(FIELD_GET(LMK04832_BIT_OSCIN_PD, tmp) |
 339		 FIELD_GET(LMK04832_BIT_VCO_PD, tmp) |
 340		 FIELD_GET(LMK04832_BIT_VCO_LDO_PD, tmp));
 341}
 342
 343static int lmk04832_vco_prepare(struct clk_hw *hw)
 344{
 345	struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
 346	int ret;
 347
 348	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD,
 349				 LMK04832_BIT_PLL2_PRE_PD |
 350				 LMK04832_BIT_PLL2_PD,
 351				 0x00);
 352	if (ret)
 353		return ret;
 354
 355	return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
 356				  LMK04832_BIT_VCO_LDO_PD |
 357				  LMK04832_BIT_VCO_PD |
 358				  LMK04832_BIT_OSCIN_PD, 0x00);
 359}
 360
 361static void lmk04832_vco_unprepare(struct clk_hw *hw)
 362{
 363	struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
 364
 365	regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD,
 366			   LMK04832_BIT_PLL2_PRE_PD | LMK04832_BIT_PLL2_PD,
 367			   0xff);
 368
 369	/* Don't set LMK04832_BIT_OSCIN_PD since other clocks depend on it */
 370	regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
 371			   LMK04832_BIT_VCO_LDO_PD | LMK04832_BIT_VCO_PD, 0xff);
 372}
 373
 374static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw,
 375					      unsigned long prate)
 376{
 377	struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
 378	static const unsigned int pll2_p[] = {8, 2, 2, 3, 4, 5, 6, 7};
 379	unsigned int pll2_n, p, pll2_r;
 380	unsigned int pll2_misc;
 381	unsigned long vco_rate;
 382	u8 tmp[3];
 383	int ret;
 384
 385	ret = regmap_read(lmk->regmap, LMK04832_REG_PLL2_MISC, &pll2_misc);
 386	if (ret)
 387		return ret;
 388
 389	p = FIELD_GET(LMK04832_BIT_PLL2_MISC_P, pll2_misc);
 390
 391	ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_N_0, &tmp, 3);
 392	if (ret)
 393		return ret;
 394
 395	pll2_n = FIELD_PREP(0x030000, tmp[0]) |
 396		 FIELD_PREP(0x00ff00, tmp[1]) |
 397		 FIELD_PREP(0x0000ff, tmp[2]);
 398
 399	ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_R_MSB, &tmp, 2);
 400	if (ret)
 401		return ret;
 402
 403	pll2_r = FIELD_PREP(0x0f00, tmp[0]) |
 404		 FIELD_PREP(0x00ff, tmp[1]);
 405
 406	vco_rate = (prate << FIELD_GET(LMK04832_BIT_PLL2_MISC_REF_2X_EN,
 407				       pll2_misc)) * pll2_n * pll2_p[p] / pll2_r;
 408
 409	return vco_rate;
 410}
 411
 412/**
 413 * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges
 414 *
 415 * @lmk:   Reference to the lmk device
 416 * @rate:  Desired output rate for the VCO
 417 *
 418 * The LMK04832 has 2 internal VCO, each with independent operating ranges.
 419 * Use the device_info structure to determine which VCO to use based on rate.
 420 *
 421 * Returns: VCO_MUX value or negative errno.
 422 */
 423static int lmk04832_check_vco_ranges(struct lmk04832 *lmk, unsigned long rate)
 424{
 425	struct spi_device *spi = to_spi_device(lmk->dev);
 426	const struct lmk04832_device_info *info;
 427	unsigned long mhz = rate / 1000000;
 428
 429	info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data];
 430
 431	if (mhz >= info->vco0_range[0] && mhz <= info->vco0_range[1])
 432		return LMK04832_VAL_VCO_MUX_VCO0;
 433
 434	if (mhz >= info->vco1_range[0] && mhz <= info->vco1_range[1])
 435		return LMK04832_VAL_VCO_MUX_VCO1;
 436
 437	dev_err(lmk->dev, "%lu Hz is out of VCO ranges\n", rate);
 438	return -ERANGE;
 439}
 440
 441/**
 442 * lmk04832_calc_pll2_params - Get PLL2 parameters used to set the VCO frequency
 443 *
 444 * @prate: parent rate to the PLL2, usually OSCin
 445 * @rate:  Desired output rate for the VCO
 446 * @n:     reference to PLL2_N
 447 * @p:     reference to PLL2_P
 448 * @r:     reference to PLL2_R
 449 *
 450 * This functions assumes LMK04832_BIT_PLL2_MISC_REF_2X_EN is set since it is
 451 * recommended in the datasheet because a higher phase detector frequencies
 452 * makes the design of wider loop bandwidth filters possible.
 453 *
 454 * the VCO rate can be calculated using the following expression:
 455 *
 456 *	VCO = OSCin * 2 * PLL2_N * PLL2_P / PLL2_R
 457 *
 458 * Returns: vco rate or negative errno.
 459 */
 460static long lmk04832_calc_pll2_params(unsigned long prate, unsigned long rate,
 461				      unsigned int *n, unsigned int *p,
 462				      unsigned int *r)
 463{
 464	unsigned int pll2_n, pll2_p, pll2_r;
 465	unsigned long num, div;
 466
 467	/* Set PLL2_P to a fixed value to simplify optimizations */
 468	pll2_p = 2;
 469
 470	div = gcd(rate, prate);
 471
 472	num = DIV_ROUND_CLOSEST(rate, div);
 473	pll2_r = DIV_ROUND_CLOSEST(prate, div);
 474
 475	if (num > 4) {
 476		pll2_n = num >> 2;
 477	} else {
 478		pll2_r = pll2_r << 2;
 479		pll2_n = num;
 480	}
 481
 482	if (pll2_n < 1 || pll2_n > 0x03ffff)
 483		return -EINVAL;
 484	if (pll2_r < 1 || pll2_r > 0xfff)
 485		return -EINVAL;
 486
 487	*n = pll2_n;
 488	*p = pll2_p;
 489	*r = pll2_r;
 490
 491	return DIV_ROUND_CLOSEST(prate * 2 * pll2_p * pll2_n, pll2_r);
 492}
 493
 494static int lmk04832_vco_determine_rate(struct clk_hw *hw,
 495				       struct clk_rate_request *req)
 496{
 497	struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
 498	unsigned int n, p, r;
 499	long vco_rate;
 500	int ret;
 501
 502	ret = lmk04832_check_vco_ranges(lmk, req->rate);
 503	if (ret < 0)
 504		return ret;
 505
 506	vco_rate = lmk04832_calc_pll2_params(req->best_parent_rate, req->rate,
 507					     &n, &p, &r);
 508	if (vco_rate < 0) {
 509		dev_err(lmk->dev, "PLL2 parameters out of range\n");
 510		req->rate = vco_rate;
 511
 512		return 0;
 513	}
 514
 515	if (req->rate != vco_rate)
 516		return -EINVAL;
 517
 518	req->rate = vco_rate;
 519
 520	return 0;
 521}
 522
 523static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
 524				 unsigned long prate)
 525{
 526	struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
 527	unsigned int n, p, r;
 528	long vco_rate;
 529	int vco_mux;
 530	int ret;
 531
 532	vco_mux = lmk04832_check_vco_ranges(lmk, rate);
 533	if (vco_mux < 0)
 534		return vco_mux;
 535
 536	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT,
 537				 LMK04832_BIT_VCO_MUX,
 538				 FIELD_PREP(LMK04832_BIT_VCO_MUX, vco_mux));
 539	if (ret)
 540		return ret;
 541
 542	vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r);
 543	if (vco_rate < 0) {
 544		dev_err(lmk->dev, "failed to determine PLL2 parameters\n");
 545		return vco_rate;
 546	}
 547
 548	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_R_MSB,
 549				 LMK04832_BIT_PLL2_R_MSB,
 550				 FIELD_GET(0x000700, r));
 551	if (ret)
 552		return ret;
 553
 554	ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_R_LSB,
 555			   FIELD_GET(0x0000ff, r));
 556	if (ret)
 557		return ret;
 558
 559	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC,
 560				 LMK04832_BIT_PLL2_MISC_P,
 561				 FIELD_PREP(LMK04832_BIT_PLL2_MISC_P, p));
 562	if (ret)
 563		return ret;
 564
 565	/*
 566	 * PLL2_N registers must be programmed after other PLL2 dividers are
 567	 * programmed to ensure proper VCO frequency calibration
 568	 */
 569	ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0,
 570			   FIELD_GET(0x030000, n));
 571	if (ret)
 572		return ret;
 573	ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_1,
 574			   FIELD_GET(0x00ff00, n));
 575	if (ret)
 576		return ret;
 577
 578	return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2,
 579			    FIELD_GET(0x0000ff, n));
 580}
 581
 582static const struct clk_ops lmk04832_vco_ops = {
 583	.is_enabled = lmk04832_vco_is_enabled,
 584	.prepare = lmk04832_vco_prepare,
 585	.unprepare = lmk04832_vco_unprepare,
 586	.recalc_rate = lmk04832_vco_recalc_rate,
 587	.determine_rate = lmk04832_vco_determine_rate,
 588	.set_rate = lmk04832_vco_set_rate,
 589};
 590
 591/*
 592 * lmk04832_register_vco - Initialize the internal VCO and clock distribution
 593 *                         path in PLL2 single loop mode.
 594 */
 595static int lmk04832_register_vco(struct lmk04832 *lmk)
 596{
 597	const char *parent_names[1];
 598	struct clk_init_data init;
 599	int ret;
 600
 601	init.name = "lmk-vco";
 602	parent_names[0] = __clk_get_name(lmk->oscin);
 603	init.parent_names = parent_names;
 604
 605	init.ops = &lmk04832_vco_ops;
 606	init.num_parents = 1;
 607
 608	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT,
 609				 LMK04832_BIT_VCO_MUX,
 610				 FIELD_PREP(LMK04832_BIT_VCO_MUX,
 611					    LMK04832_VAL_VCO_MUX_VCO1));
 612	if (ret)
 613		return ret;
 614
 615	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_FB_CTRL,
 616				 LMK04832_BIT_PLL2_RCLK_MUX |
 617				 LMK04832_BIT_PLL2_NCLK_MUX,
 618				 FIELD_PREP(LMK04832_BIT_PLL2_RCLK_MUX,
 619					    LMK04832_VAL_PLL2_RCLK_MUX_OSCIN)|
 620				 FIELD_PREP(LMK04832_BIT_PLL2_NCLK_MUX,
 621					    LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P));
 622	if (ret)
 623		return ret;
 624
 625	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC,
 626				 LMK04832_BIT_PLL2_MISC_REF_2X_EN,
 627				 LMK04832_BIT_PLL2_MISC_REF_2X_EN);
 628	if (ret)
 629		return ret;
 630
 631	ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_LD,
 632			   FIELD_PREP(LMK04832_BIT_PLL2_LD_MUX,
 633				      LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD) |
 634			   FIELD_PREP(LMK04832_BIT_PLL2_LD_TYPE,
 635				      LMK04832_VAL_PLL2_LD_TYPE_OUT_PP));
 636	if (ret)
 637		return ret;
 638
 639	lmk->vco.init = &init;
 640	return devm_clk_hw_register(lmk->dev, &lmk->vco);
 641}
 642
 643static int lmk04832_clkout_set_ddly(struct lmk04832 *lmk, int id)
 644{
 645	static const int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0};
 646	unsigned int sclkx_y_ddly = 10;
 647	unsigned int dclkx_y_ddly;
 648	unsigned int dclkx_y_div;
 649	unsigned int sysref_ddly;
 650	unsigned int dclkx_y_hs;
 651	unsigned int lsb, msb;
 652	int ret;
 653
 654	ret = regmap_update_bits(lmk->regmap,
 655				 LMK04832_REG_CLKOUT_CTRL2(id),
 656				 LMK04832_BIT_DCLKX_Y_DDLY_PD,
 657				 FIELD_PREP(LMK04832_BIT_DCLKX_Y_DDLY_PD, 0));
 658	if (ret)
 659		return ret;
 660
 661	ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, &lsb);
 662	if (ret)
 663		return ret;
 664
 665	ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, &msb);
 666	if (ret)
 667		return ret;
 668
 669	sysref_ddly = FIELD_GET(LMK04832_BIT_SYSREF_DDLY_MSB, msb) << 8 | lsb;
 670
 671	ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(id), &lsb);
 672	if (ret)
 673		return ret;
 674
 675	ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), &msb);
 676	if (ret)
 677		return ret;
 678
 679	dclkx_y_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
 680
 681	ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(id), &lsb);
 682	if (ret)
 683		return ret;
 684
 685	dclkx_y_hs = FIELD_GET(LMK04832_BIT_DCLKX_Y_HS, lsb);
 686
 687	dclkx_y_ddly = sysref_ddly + 1 -
 688		dclk_div_adj[dclkx_y_div < 6 ?  dclkx_y_div : 7] -
 689		dclkx_y_hs + sclkx_y_ddly;
 690
 691	if (dclkx_y_ddly < 7 || dclkx_y_ddly > 0x3fff) {
 692		dev_err(lmk->dev, "DCLKX_Y_DDLY out of range (%d)\n",
 693			dclkx_y_ddly);
 694		return -EINVAL;
 695	}
 696
 697	ret = regmap_write(lmk->regmap,
 698			   LMK04832_REG_SCLKX_Y_DDLY(id),
 699			   FIELD_GET(LMK04832_BIT_SCLKX_Y_DDLY, sclkx_y_ddly));
 700	if (ret)
 701		return ret;
 702
 703	ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL1(id),
 704				FIELD_GET(0x00ff, dclkx_y_ddly));
 705	if (ret)
 706		return ret;
 707
 708	dev_dbg(lmk->dev, "clkout%02u: sysref_ddly=%u, dclkx_y_ddly=%u, "
 709		"dclk_div_adj=%+d, dclkx_y_hs=%u, sclkx_y_ddly=%u\n",
 710		id, sysref_ddly, dclkx_y_ddly,
 711		dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7],
 712		dclkx_y_hs, sclkx_y_ddly);
 713
 714	return regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id),
 715				  LMK04832_BIT_DCLKX_Y_DDLY_MSB,
 716				  FIELD_GET(0x0300, dclkx_y_ddly));
 717}
 718
 719/** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk
 720 *                       and dclk
 721 *
 722 * @lmk: Reference to the lmk device
 723 *
 724 * The synchronization sequence:
 725 * - in the datasheet https://www.ti.com/lit/ds/symlink/lmk04832.pdf, p.31
 726 *   (8.3.3.1 How to enable SYSREF)
 727 * - Ti forum: https://e2e.ti.com/support/clock-and-timing/f/48/t/970972
 728 *
 729 * Returns 0 or negative errno.
 730 */
 731static int lmk04832_sclk_sync_sequence(struct lmk04832 *lmk)
 732{
 733	int ret;
 734	int i;
 735
 736	/* 1. (optional) mute all sysref_outputs during synchronization */
 737	/* 2. Enable and write device clock digital delay to applicable clocks */
 738	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
 739				 LMK04832_BIT_SYSREF_DDLY_PD,
 740				 FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0));
 741	if (ret)
 742		return ret;
 743
 744	for (i = 0; i < lmk->clk_data->num; i += 2) {
 745		ret = lmk04832_clkout_set_ddly(lmk, i);
 746		if (ret)
 747			return ret;
 748	}
 749
 750	/*
 751	 * 3. Configure SYNC_MODE to SYNC_PIN and SYSREF_MUX to Normal SYNC,
 752	 *    and clear SYSREF_REQ_EN (see 6.)
 753	 */
 754	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
 755				 LMK04832_BIT_SYSREF_REQ_EN |
 756				 LMK04832_BIT_SYSREF_MUX,
 757				 FIELD_PREP(LMK04832_BIT_SYSREF_REQ_EN, 0) |
 758				 FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
 759					    LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC));
 760	if (ret)
 761		return ret;
 762
 763	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
 764				 LMK04832_BIT_SYNC_MODE,
 765				 FIELD_PREP(LMK04832_BIT_SYNC_MODE,
 766					    LMK04832_VAL_SYNC_MODE_ON));
 767	if (ret)
 768		return ret;
 769
 770	/* 4. Clear SYNXC_DISx or applicable clocks and clear SYNC_DISSYSREF */
 771	ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00);
 772	if (ret)
 773		return ret;
 774
 775	/*
 776	 * 5. If SCLKX_Y_DDLY != 0, Set SYSREF_CLR=1 for at least 15 clock
 777	 *    distribution path cycles (VCO cycles), then back to 0. In
 778	 *    PLL2-only use case, this will be complete in less than one SPI
 779	 *    transaction. If SYSREF local digital delay is not used, this step
 780	 *    can be skipped.
 781	 */
 782	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
 783				 LMK04832_BIT_SYNC_CLR,
 784				 FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x01));
 785	if (ret)
 786		return ret;
 787
 788	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
 789				 LMK04832_BIT_SYNC_CLR,
 790				 FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x00));
 791	if (ret)
 792		return ret;
 793
 794	/*
 795	 * 6. Toggle SYNC_POL state between inverted and not inverted.
 796	 *    If you use an external signal on the SYNC pin instead of toggling
 797	 *    SYNC_POL, make sure that SYSREF_REQ_EN=0 so that the SYSREF_MUX
 798	 *    does not shift into continuous SYSREF mode.
 799	 */
 800	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
 801			   LMK04832_BIT_SYNC_POL,
 802			   FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x01));
 803	if (ret)
 804		return ret;
 805
 806	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
 807			   LMK04832_BIT_SYNC_POL,
 808			   FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x00));
 809	if (ret)
 810		return ret;
 811
 812	/* 7. Set all SYNC_DISx=1, including SYNC_DISSYSREF */
 813	ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
 814	if (ret)
 815		return ret;
 816
 817	/* 8. Restore state of SYNC_MODE and SYSREF_MUX to desired values */
 818	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
 819				 LMK04832_BIT_SYSREF_MUX,
 820				 FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
 821					    lmk->sysref_mux));
 822	if (ret)
 823		return ret;
 824
 825	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
 826				 LMK04832_BIT_SYNC_MODE,
 827				 FIELD_PREP(LMK04832_BIT_SYNC_MODE,
 828					    lmk->sync_mode));
 829	if (ret)
 830		return ret;
 831
 832	/*
 833	 * 9. (optional) if SCLKx_y_DIS_MODE was used to mute SYSREF outputs
 834	 *    during the SYNC event, restore SCLKx_y_DIS_MODE=0 for active state,
 835	 *    or set SYSREF_GBL_PD=0 if SCLKx_y_DIS_MODE is set to a conditional
 836	 *    option.
 837	 */
 838
 839	/*
 840	 * 10. (optional) To reduce power consumption, after the synchronization
 841	 *     event is complete, DCLKx_y_DDLY_PD=1 and SYSREF_DDLY_PD=1 disable the
 842	 *     digital delay counters (which are only used immediately after the
 843	 *     SYNC pulse to delay the output by some number of VCO counts).
 844	 */
 845
 846	return ret;
 847}
 848
 849static int lmk04832_sclk_is_enabled(struct clk_hw *hw)
 850{
 851	struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
 852	unsigned int tmp;
 853	int ret;
 854
 855	ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp);
 856	if (ret)
 857		return ret;
 858
 859	return FIELD_GET(LMK04832_BIT_SYSREF_PD, tmp);
 860}
 861
 862static int lmk04832_sclk_prepare(struct clk_hw *hw)
 863{
 864	struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
 865
 866	return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
 867				  LMK04832_BIT_SYSREF_PD, 0x00);
 868}
 869
 870static void lmk04832_sclk_unprepare(struct clk_hw *hw)
 871{
 872	struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
 873
 874	regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
 875			   LMK04832_BIT_SYSREF_PD, LMK04832_BIT_SYSREF_PD);
 876}
 877
 878static unsigned long lmk04832_sclk_recalc_rate(struct clk_hw *hw,
 879					       unsigned long prate)
 880{
 881	struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
 882	unsigned int sysref_div;
 883	u8 tmp[2];
 884	int ret;
 885
 886	ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, &tmp, 2);
 887	if (ret)
 888		return ret;
 889
 890	sysref_div = FIELD_GET(LMK04832_BIT_SYSREF_DIV_MSB, tmp[0]) << 8 |
 891		tmp[1];
 892
 893	return DIV_ROUND_CLOSEST(prate, sysref_div);
 894}
 895
 896static int lmk04832_sclk_determine_rate(struct clk_hw *hw,
 897					struct clk_rate_request *req)
 898{
 899	struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
 900	unsigned long sclk_rate;
 901	unsigned int sysref_div;
 902
 903	sysref_div = DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate);
 904	sclk_rate = DIV_ROUND_CLOSEST(req->best_parent_rate, sysref_div);
 905
 906	if (sysref_div < 0x07 || sysref_div > 0x1fff) {
 907		dev_err(lmk->dev, "SYSREF divider out of range\n");
 908		return -EINVAL;
 909	}
 910
 911	if (req->rate != sclk_rate)
 912		return -EINVAL;
 913
 914	req->rate = sclk_rate;
 915
 916	return 0;
 917}
 918
 919static int lmk04832_sclk_set_rate(struct clk_hw *hw, unsigned long rate,
 920				  unsigned long prate)
 921{
 922	struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
 923	unsigned int sysref_div;
 924	int ret;
 925
 926	sysref_div = DIV_ROUND_CLOSEST(prate, rate);
 927
 928	if (sysref_div < 0x07 || sysref_div > 0x1fff) {
 929		dev_err(lmk->dev, "SYSREF divider out of range\n");
 930		return -EINVAL;
 931	}
 932
 933	ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB,
 934			   FIELD_GET(0x1f00, sysref_div));
 935	if (ret)
 936		return ret;
 937
 938	ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB,
 939			    FIELD_GET(0x00ff, sysref_div));
 940	if (ret)
 941		return ret;
 942
 943	ret = lmk04832_sclk_sync_sequence(lmk);
 944	if (ret)
 945		dev_err(lmk->dev, "SYNC sequence failed\n");
 946
 947	return ret;
 948}
 949
 950static const struct clk_ops lmk04832_sclk_ops = {
 951	.is_enabled = lmk04832_sclk_is_enabled,
 952	.prepare = lmk04832_sclk_prepare,
 953	.unprepare = lmk04832_sclk_unprepare,
 954	.recalc_rate = lmk04832_sclk_recalc_rate,
 955	.determine_rate = lmk04832_sclk_determine_rate,
 956	.set_rate = lmk04832_sclk_set_rate,
 957};
 958
 959static int lmk04832_register_sclk(struct lmk04832 *lmk)
 960{
 961	const char *parent_names[1];
 962	struct clk_init_data init;
 963	int ret;
 964
 965	init.name = "lmk-sclk";
 966	parent_names[0] = clk_hw_get_name(&lmk->vco);
 967	init.parent_names = parent_names;
 968
 969	init.ops = &lmk04832_sclk_ops;
 970	init.flags = CLK_SET_RATE_PARENT;
 971	init.num_parents = 1;
 972
 973	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
 974				 LMK04832_BIT_SYSREF_MUX,
 975				 FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
 976					    lmk->sysref_mux));
 977	if (ret)
 978		return ret;
 979
 980	ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB,
 981			   FIELD_GET(0x00ff, lmk->sysref_ddly));
 982	if (ret)
 983		return ret;
 984
 985	ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB,
 986			   FIELD_GET(0x1f00, lmk->sysref_ddly));
 987	if (ret)
 988		return ret;
 989
 990	ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_PULSE_CNT,
 991			   ilog2(lmk->sysref_pulse_cnt));
 992	if (ret)
 993		return ret;
 994
 995	ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
 996				 LMK04832_BIT_SYSREF_DDLY_PD |
 997				 LMK04832_BIT_SYSREF_PLSR_PD,
 998				 FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0) |
 999				 FIELD_PREP(LMK04832_BIT_SYSREF_PLSR_PD, 0));
1000	if (ret)
1001		return ret;
1002
1003	ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC,
1004			   FIELD_PREP(LMK04832_BIT_SYNC_POL, 0) |
1005			   FIELD_PREP(LMK04832_BIT_SYNC_EN, 1) |
1006			   FIELD_PREP(LMK04832_BIT_SYNC_MODE, lmk->sync_mode));
1007	if (ret)
1008		return ret;
1009
1010	ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
1011	if (ret)
1012		return ret;
1013
1014	lmk->sclk.init = &init;
1015	return devm_clk_hw_register(lmk->dev, &lmk->sclk);
1016}
1017
1018static int lmk04832_dclk_is_enabled(struct clk_hw *hw)
1019{
1020	struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1021	struct lmk04832 *lmk = dclk->lmk;
1022	unsigned int tmp;
1023	int ret;
1024
1025	ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1026			  &tmp);
1027	if (ret)
1028		return ret;
1029
1030	return !FIELD_GET(LMK04832_BIT_DCLKX_Y_PD, tmp);
1031}
1032
1033static int lmk04832_dclk_prepare(struct clk_hw *hw)
1034{
1035	struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1036	struct lmk04832 *lmk = dclk->lmk;
1037
1038	return regmap_update_bits(lmk->regmap,
1039				  LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1040				  LMK04832_BIT_DCLKX_Y_PD, 0x00);
1041}
1042
1043static void lmk04832_dclk_unprepare(struct clk_hw *hw)
1044{
1045	struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1046	struct lmk04832 *lmk = dclk->lmk;
1047
1048	regmap_update_bits(lmk->regmap,
1049			   LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1050			   LMK04832_BIT_DCLKX_Y_PD, 0xff);
1051}
1052
1053static unsigned long lmk04832_dclk_recalc_rate(struct clk_hw *hw,
1054					       unsigned long prate)
1055{
1056	struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1057	struct lmk04832 *lmk = dclk->lmk;
1058	unsigned int dclk_div;
1059	unsigned int lsb, msb;
1060	unsigned long rate;
1061	int ret;
1062
1063	ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
1064			  &lsb);
1065	if (ret)
1066		return ret;
1067
1068	ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1069			  &msb);
1070	if (ret)
1071		return ret;
1072
1073	dclk_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
1074	rate = DIV_ROUND_CLOSEST(prate, dclk_div);
1075
1076	return rate;
1077}
1078
1079static int lmk04832_dclk_determine_rate(struct clk_hw *hw,
1080					struct clk_rate_request *req)
1081{
1082	struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1083	struct lmk04832 *lmk = dclk->lmk;
1084	unsigned long dclk_rate;
1085	unsigned int dclk_div;
1086
1087	dclk_div = DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate);
1088	dclk_rate = DIV_ROUND_CLOSEST(req->best_parent_rate, dclk_div);
1089
1090	if (dclk_div < 1 || dclk_div > 0x3ff) {
1091		dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw));
1092		return -EINVAL;
1093	}
1094
1095	if (req->rate != dclk_rate)
1096		return -EINVAL;
1097
1098	req->rate = dclk_rate;
1099
1100	return 0;
1101}
1102
1103static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
1104				  unsigned long prate)
1105{
1106	struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1107	struct lmk04832 *lmk = dclk->lmk;
1108	unsigned int dclk_div;
1109	int ret;
1110
1111	dclk_div = DIV_ROUND_CLOSEST(prate, rate);
1112
1113	if (dclk_div > 0x3ff) {
1114		dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw));
1115		return -EINVAL;
1116	}
1117
1118	/* Enable Duty Cycle Correction */
1119	if (dclk_div == 1) {
1120		ret = regmap_update_bits(lmk->regmap,
1121					 LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1122					 LMK04832_BIT_DCLKX_Y_DCC,
1123					 FIELD_PREP(LMK04832_BIT_DCLKX_Y_DCC, 1));
1124		if (ret)
1125			return ret;
1126	}
1127
1128	/*
1129	 * While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC
1130	 * procedure requires to first program Divide-by-4 and then back to
1131	 * Divide-by-2 or Divide-by-3 before doing SYNC.
1132	 */
1133	if (dclk_div == 2 || dclk_div == 3) {
1134		ret = regmap_update_bits(lmk->regmap,
1135					 LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1136					 LMK04832_BIT_DCLK_DIV_MSB, 0x00);
1137		if (ret)
1138			return ret;
1139
1140		ret = regmap_write(lmk->regmap,
1141				   LMK04832_REG_CLKOUT_CTRL0(dclk->id), 0x04);
1142		if (ret)
1143			return ret;
1144	}
1145
1146	ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
1147			   FIELD_GET(0x0ff, dclk_div));
1148	if (ret)
1149		return ret;
1150
1151	ret = regmap_update_bits(lmk->regmap,
1152				  LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1153				  LMK04832_BIT_DCLK_DIV_MSB,
1154				  FIELD_GET(0x300, dclk_div));
1155	if (ret)
1156		return ret;
1157
1158	ret = lmk04832_sclk_sync_sequence(lmk);
1159	if (ret)
1160		dev_err(lmk->dev, "SYNC sequence failed\n");
1161
1162	return ret;
1163}
1164
1165static const struct clk_ops lmk04832_dclk_ops = {
1166	.is_enabled = lmk04832_dclk_is_enabled,
1167	.prepare = lmk04832_dclk_prepare,
1168	.unprepare = lmk04832_dclk_unprepare,
1169	.recalc_rate = lmk04832_dclk_recalc_rate,
1170	.determine_rate = lmk04832_dclk_determine_rate,
1171	.set_rate = lmk04832_dclk_set_rate,
1172};
1173
1174static int lmk04832_clkout_is_enabled(struct clk_hw *hw)
1175{
1176	struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1177	struct lmk04832 *lmk = clkout->lmk;
1178	unsigned int clkoutx_y_pd;
1179	unsigned int sclkx_y_pd;
1180	unsigned int tmp;
1181	u32 enabled;
1182	int ret;
1183	u8 fmt;
1184
1185	ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(clkout->id),
1186			  &clkoutx_y_pd);
1187	if (ret)
1188		return ret;
1189
1190	enabled = !FIELD_GET(LMK04832_BIT_CLKOUTX_Y_PD, clkoutx_y_pd);
1191
1192	ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1193			  &tmp);
1194	if (ret)
1195		return ret;
1196
1197	if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) {
1198		ret = regmap_read(lmk->regmap,
1199				  LMK04832_REG_CLKOUT_CTRL4(clkout->id),
1200				  &sclkx_y_pd);
1201		if (ret)
1202			return ret;
1203
1204		enabled = enabled && !FIELD_GET(LMK04832_BIT_SCLK_PD, sclkx_y_pd);
1205	}
1206
1207	ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id),
1208			  &tmp);
1209	if (ret)
1210		return ret;
1211
1212	if (clkout->id % 2)
1213		fmt = FIELD_GET(0xf0, tmp);
1214	else
1215		fmt = FIELD_GET(0x0f, tmp);
1216
1217	return enabled && !fmt;
1218}
1219
1220static int lmk04832_clkout_prepare(struct clk_hw *hw)
1221{
1222	struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1223	struct lmk04832 *lmk = clkout->lmk;
1224	unsigned int tmp;
1225	int ret;
1226
1227	if (clkout->format == LMK04832_VAL_CLKOUT_FMT_POWERDOWN)
1228		dev_err(lmk->dev, "prepared %s but format is powerdown\n",
1229			clk_hw_get_name(hw));
1230
1231	ret = regmap_update_bits(lmk->regmap,
1232				 LMK04832_REG_CLKOUT_CTRL2(clkout->id),
1233				 LMK04832_BIT_CLKOUTX_Y_PD, 0x00);
1234	if (ret)
1235		return ret;
1236
1237	ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1238			  &tmp);
1239	if (ret)
1240		return ret;
1241
1242	if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) {
1243		ret = regmap_update_bits(lmk->regmap,
1244					 LMK04832_REG_CLKOUT_CTRL4(clkout->id),
1245					 LMK04832_BIT_SCLK_PD, 0x00);
1246		if (ret)
1247			return ret;
1248	}
1249
1250	return regmap_update_bits(lmk->regmap,
1251				  LMK04832_REG_CLKOUT_FMT(clkout->id),
1252				  LMK04832_BIT_CLKOUT_FMT(clkout->id),
1253				  clkout->format << 4 * (clkout->id % 2));
1254}
1255
1256static void lmk04832_clkout_unprepare(struct clk_hw *hw)
1257{
1258	struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1259	struct lmk04832 *lmk = clkout->lmk;
1260
1261	regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id),
1262			   LMK04832_BIT_CLKOUT_FMT(clkout->id),
1263			   0x00);
1264}
1265
1266static int lmk04832_clkout_set_parent(struct clk_hw *hw, uint8_t index)
1267{
1268	struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1269	struct lmk04832 *lmk = clkout->lmk;
1270
1271	return regmap_update_bits(lmk->regmap,
1272				  LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1273				  LMK04832_BIT_CLKOUT_SRC_MUX,
1274				  FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX,
1275					     index));
1276}
1277
1278static uint8_t lmk04832_clkout_get_parent(struct clk_hw *hw)
1279{
1280	struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1281	struct lmk04832 *lmk = clkout->lmk;
1282	unsigned int tmp;
1283	int ret;
1284
1285	ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1286			  &tmp);
1287	if (ret)
1288		return ret;
1289
1290	return FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp);
1291}
1292
1293static const struct clk_ops lmk04832_clkout_ops = {
1294	.is_enabled = lmk04832_clkout_is_enabled,
1295	.prepare = lmk04832_clkout_prepare,
1296	.unprepare = lmk04832_clkout_unprepare,
1297	.determine_rate = __clk_mux_determine_rate,
1298	.set_parent = lmk04832_clkout_set_parent,
1299	.get_parent = lmk04832_clkout_get_parent,
1300};
1301
1302static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num)
1303{
1304	char name[] = "lmk-clkoutXX";
1305	char dclk_name[] = "lmk-dclkXX_YY";
1306	const char *parent_names[2];
1307	struct clk_init_data init;
1308	int dclk_num = num / 2;
1309	int ret;
1310
1311	if (num % 2 == 0) {
1312		sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1);
1313		init.name = dclk_name;
1314		parent_names[0] = clk_hw_get_name(&lmk->vco);
1315		init.parent_names = parent_names;
1316		init.ops = &lmk04832_dclk_ops;
1317		init.flags = CLK_SET_RATE_PARENT;
1318		init.num_parents = 1;
1319
1320		lmk->dclk[dclk_num].id = num;
1321		lmk->dclk[dclk_num].lmk = lmk;
1322		lmk->dclk[dclk_num].hw.init = &init;
1323
1324		ret = devm_clk_hw_register(lmk->dev, &lmk->dclk[dclk_num].hw);
1325		if (ret)
1326			return ret;
1327	} else {
1328		sprintf(dclk_name, "lmk-dclk%02d_%02d", num - 1, num);
1329	}
1330
1331	if (of_property_read_string_index(lmk->dev->of_node,
1332					  "clock-output-names",
1333					  num, &init.name)) {
1334		sprintf(name, "lmk-clkout%02d", num);
1335		init.name = name;
1336	}
1337
1338	parent_names[0] = dclk_name;
1339	parent_names[1] = clk_hw_get_name(&lmk->sclk);
1340	init.parent_names = parent_names;
1341	init.ops = &lmk04832_clkout_ops;
1342	init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
1343	init.num_parents = ARRAY_SIZE(parent_names);
1344
1345	lmk->clkout[num].id = num;
1346	lmk->clkout[num].lmk = lmk;
1347	lmk->clkout[num].hw.init = &init;
1348	lmk->clk_data->hws[num] = &lmk->clkout[num].hw;
1349
1350	/* Set initial parent */
1351	regmap_update_bits(lmk->regmap,
1352			   LMK04832_REG_CLKOUT_SRC_MUX(num),
1353			   LMK04832_BIT_CLKOUT_SRC_MUX,
1354			   FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX,
1355				      lmk->clkout[num].sysref));
1356
1357	return devm_clk_hw_register(lmk->dev, &lmk->clkout[num].hw);
1358}
1359
1360static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
1361{
1362	int reg;
1363	int ret;
1364	int val = FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
1365			     LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
1366		  FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
1367			     LMK04832_VAL_CLKIN_SEL_TYPE_OUT);
1368
1369	dev_info(lmk->dev, "setting up 4-wire mode\n");
1370	ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W,
1371			   LMK04832_BIT_SPI_3WIRE_DIS);
1372	if (ret)
1373		return ret;
1374
1375	switch (rdbk_pin) {
1376	case RDBK_CLKIN_SEL0:
1377		reg = LMK04832_REG_CLKIN_SEL0;
1378		break;
1379	case RDBK_CLKIN_SEL1:
1380		reg = LMK04832_REG_CLKIN_SEL1;
1381		break;
1382	case RDBK_RESET:
1383		reg = LMK04832_REG_CLKIN_RST;
1384		break;
1385	case RDBK_PLL1_LD:
1386		reg = LMK04832_REG_PLL1_LD;
1387		val = FIELD_PREP(LMK04832_BIT_PLL1_LD_MUX,
1388				 LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK) |
1389		      FIELD_PREP(LMK04832_BIT_PLL1_LD_TYPE,
1390				 LMK04832_VAL_PLL1_LD_TYPE_OUT_PP);
1391		break;
1392	default:
1393		return -EINVAL;
1394	}
1395
1396	return regmap_write(lmk->regmap, reg, val);
1397}
1398
1399static int lmk04832_probe(struct spi_device *spi)
1400{
1401	const struct lmk04832_device_info *info;
1402	int rdbk_pin = RDBK_CLKIN_SEL1;
1403	struct device_node *child;
1404	struct lmk04832 *lmk;
1405	u8 tmp[3];
1406	int ret;
1407	int i;
1408
1409	info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data];
1410
1411	lmk = devm_kzalloc(&spi->dev, sizeof(struct lmk04832), GFP_KERNEL);
1412	if (!lmk)
1413		return -ENOMEM;
1414
1415	lmk->dev = &spi->dev;
1416
1417	lmk->oscin = devm_clk_get_enabled(lmk->dev, "oscin");
1418	if (IS_ERR(lmk->oscin)) {
1419		dev_err(lmk->dev, "failed to get oscin clock\n");
1420		return PTR_ERR(lmk->oscin);
1421	}
1422
1423	lmk->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
1424						  GPIOD_OUT_LOW);
1425
1426	lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1,
1427				 sizeof(struct lmk_dclk), GFP_KERNEL);
1428	if (!lmk->dclk) {
1429		ret = -ENOMEM;
1430		return ret;
1431	}
1432
1433	lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels,
1434				   sizeof(*lmk->clkout), GFP_KERNEL);
1435	if (!lmk->clkout) {
1436		ret = -ENOMEM;
1437		return ret;
1438	}
1439
1440	lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws,
1441							   info->num_channels),
1442				     GFP_KERNEL);
1443	if (!lmk->clk_data) {
1444		ret = -ENOMEM;
1445		return ret;
1446	}
1447
1448	device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate);
1449
1450	lmk->sysref_ddly = 8;
1451	device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly);
1452
1453	lmk->sysref_mux = LMK04832_VAL_SYSREF_MUX_CONTINUOUS;
1454	device_property_read_u32(lmk->dev, "ti,sysref-mux",
1455				 &lmk->sysref_mux);
1456
1457	lmk->sync_mode = LMK04832_VAL_SYNC_MODE_OFF;
1458	device_property_read_u32(lmk->dev, "ti,sync-mode",
1459				 &lmk->sync_mode);
1460
1461	lmk->sysref_pulse_cnt = 4;
1462	device_property_read_u32(lmk->dev, "ti,sysref-pulse-count",
1463				 &lmk->sysref_pulse_cnt);
1464
1465	for_each_child_of_node(lmk->dev->of_node, child) {
1466		int reg;
1467
1468		ret = of_property_read_u32(child, "reg", &reg);
1469		if (ret) {
1470			dev_err(lmk->dev, "missing reg property in child: %s\n",
1471				child->full_name);
1472			of_node_put(child);
1473			return ret;
1474		}
1475
1476		of_property_read_u32(child, "ti,clkout-fmt",
1477				     &lmk->clkout[reg].format);
1478
1479		if (lmk->clkout[reg].format >= 0x0a && reg % 2 == 0
1480		    && reg != 8 && reg != 10)
1481			dev_err(lmk->dev, "invalid format for clkout%02d\n",
1482				reg);
1483
1484		lmk->clkout[reg].sysref =
1485			of_property_read_bool(child, "ti,clkout-sysref");
1486	}
1487
1488	lmk->regmap = devm_regmap_init_spi(spi, &regmap_config);
1489	if (IS_ERR(lmk->regmap)) {
1490		dev_err(lmk->dev, "%s: regmap allocation failed: %ld\n",
1491
1492			__func__, PTR_ERR(lmk->regmap));
1493		ret = PTR_ERR(lmk->regmap);
1494		return ret;
1495	}
1496
1497	regmap_write(lmk->regmap, LMK04832_REG_RST3W, LMK04832_BIT_RESET);
1498
1499	if (!(spi->mode & SPI_3WIRE)) {
1500		device_property_read_u32(lmk->dev, "ti,spi-4wire-rdbk",
1501					 &rdbk_pin);
1502		ret = lmk04832_set_spi_rdbk(lmk, rdbk_pin);
1503		if (ret)
1504			return ret;
1505	}
1506
1507	regmap_bulk_read(lmk->regmap, LMK04832_REG_ID_PROD_MSB, &tmp, 3);
1508	if ((tmp[0] << 8 | tmp[1]) != info->pid || tmp[2] != info->maskrev) {
1509		dev_err(lmk->dev, "unsupported device type: pid 0x%04x, maskrev 0x%02x\n",
1510			tmp[0] << 8 | tmp[1], tmp[2]);
1511		ret = -EINVAL;
1512		return ret;
1513	}
1514
1515	ret = lmk04832_register_vco(lmk);
1516	if (ret) {
1517		dev_err(lmk->dev, "failed to init device clock path\n");
1518		return ret;
1519	}
1520
1521	if (lmk->vco_rate) {
1522		dev_info(lmk->dev, "setting VCO rate to %u Hz\n", lmk->vco_rate);
1523		ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate);
1524		if (ret) {
1525			dev_err(lmk->dev, "failed to set VCO rate\n");
1526			return ret;
1527		}
1528	}
1529
1530	ret = lmk04832_register_sclk(lmk);
1531	if (ret) {
1532		dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n");
1533		return ret;
1534	}
1535
1536	for (i = 0; i < info->num_channels; i++) {
1537		ret = lmk04832_register_clkout(lmk, i);
1538		if (ret) {
1539			dev_err(lmk->dev, "failed to register clk %d\n", i);
1540			return ret;
1541		}
1542	}
1543
1544	lmk->clk_data->num = info->num_channels;
1545	ret = devm_of_clk_add_hw_provider(lmk->dev, of_clk_hw_onecell_get,
1546					  lmk->clk_data);
1547	if (ret) {
1548		dev_err(lmk->dev, "failed to add provider (%d)\n", ret);
1549		return ret;
1550	}
1551
1552	spi_set_drvdata(spi, lmk);
1553
1554	return 0;
1555}
1556
1557static const struct spi_device_id lmk04832_id[] = {
1558	{ "lmk04832", LMK04832 },
1559	{}
1560};
1561MODULE_DEVICE_TABLE(spi, lmk04832_id);
1562
1563static const struct of_device_id lmk04832_of_id[] = {
1564	{ .compatible = "ti,lmk04832" },
1565	{}
1566};
1567MODULE_DEVICE_TABLE(of, lmk04832_of_id);
1568
1569static struct spi_driver lmk04832_driver = {
1570	.driver = {
1571		.name	= "lmk04832",
1572		.of_match_table = lmk04832_of_id,
1573	},
1574	.probe		= lmk04832_probe,
1575	.id_table	= lmk04832_id,
1576};
1577module_spi_driver(lmk04832_driver);
1578
1579MODULE_AUTHOR("Liam Beguin <lvb@xiphos.com>");
1580MODULE_DESCRIPTION("Texas Instruments LMK04832");
1581MODULE_LICENSE("GPL v2");