clk-cdce925.c

  1/*
  2 * Driver for TI Multi PLL CDCE913/925/937/949 clock synthesizer
  3 *
  4 * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1,
  5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
  6 * basis. Clients can directly request any frequency that the chip can
  7 * deliver using the standard clk framework. In addition, the device can
  8 * be configured and activated via the devicetree.
  9 *
 10 * Copyright (C) 2014, Topic Embedded Products
 11 * Licenced under GPL
 12 */
 13#include <linux/clk.h>
 14#include <linux/clk-provider.h>
 15#include <linux/delay.h>
 16#include <linux/module.h>
 17#include <linux/i2c.h>
 18#include <linux/regmap.h>
 19#include <linux/regulator/consumer.h>
 20#include <linux/slab.h>
 21#include <linux/gcd.h>
 22
 23/* Each chip has different number of PLLs and outputs, for example:
 24 * The CECE925 has 2 PLLs which can be routed through dividers to 5 outputs.
 25 * Model this as 2 PLL clocks which are parents to the outputs.
 26 */
 27
 28struct clk_cdce925_chip_info {
 29	int num_plls;
 30	int num_outputs;
 31};
 32
 33#define MAX_NUMBER_OF_PLLS	4
 34#define MAX_NUMBER_OF_OUTPUTS	9
 35
 36#define CDCE925_REG_GLOBAL1	0x01
 37#define CDCE925_REG_Y1SPIPDIVH	0x02
 38#define CDCE925_REG_PDIVL	0x03
 39#define CDCE925_REG_XCSEL	0x05
 40/* PLL parameters start at 0x10, steps of 0x10 */
 41#define CDCE925_OFFSET_PLL	0x10
 42/* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */
 43#define CDCE925_PLL_MUX_OUTPUTS	0x14
 44#define CDCE925_PLL_MULDIV	0x18
 45
 46#define CDCE925_PLL_FREQUENCY_MIN	 80000000ul
 47#define CDCE925_PLL_FREQUENCY_MAX	230000000ul
 48struct clk_cdce925_chip;
 49
 50struct clk_cdce925_output {
 51	struct clk_hw hw;
 52	struct clk_cdce925_chip *chip;
 53	u8 index;
 54	u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
 55};
 56#define to_clk_cdce925_output(_hw) \
 57	container_of(_hw, struct clk_cdce925_output, hw)
 58
 59struct clk_cdce925_pll {
 60	struct clk_hw hw;
 61	struct clk_cdce925_chip *chip;
 62	u8 index;
 63	u16 m;   /* 1..511 */
 64	u16 n;   /* 1..4095 */
 65};
 66#define to_clk_cdce925_pll(_hw)	container_of(_hw, struct clk_cdce925_pll, hw)
 67
 68struct clk_cdce925_chip {
 69	struct regmap *regmap;
 70	struct i2c_client *i2c_client;
 71	const struct clk_cdce925_chip_info *chip_info;
 72	struct clk_cdce925_pll pll[MAX_NUMBER_OF_PLLS];
 73	struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS];
 74};
 75
 76/* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */
 77
 78static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate,
 79	u16 n, u16 m)
 80{
 81	if ((!m || !n) || (m == n))
 82		return parent_rate; /* In bypass mode runs at same frequency */
 83	return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m);
 84}
 85
 86static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw,
 87		unsigned long parent_rate)
 88{
 89	/* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */
 90	struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
 91
 92	return cdce925_pll_calculate_rate(parent_rate, data->n, data->m);
 93}
 94
 95static void cdce925_pll_find_rate(unsigned long rate,
 96		unsigned long parent_rate, u16 *n, u16 *m)
 97{
 98	unsigned long un;
 99	unsigned long um;
100	unsigned long g;
101
102	if (rate <= parent_rate) {
103		/* Can always deliver parent_rate in bypass mode */
104		*n = 0;
105		*m = 0;
106	} else {
107		/* In PLL mode, need to apply min/max range */
108		if (rate < CDCE925_PLL_FREQUENCY_MIN)
109			rate = CDCE925_PLL_FREQUENCY_MIN;
110		else if (rate > CDCE925_PLL_FREQUENCY_MAX)
111			rate = CDCE925_PLL_FREQUENCY_MAX;
112
113		g = gcd(rate, parent_rate);
114		um = parent_rate / g;
115		un = rate / g;
116		/* When outside hw range, reduce to fit (rounding errors) */
117		while ((un > 4095) || (um > 511)) {
118			un >>= 1;
119			um >>= 1;
120		}
121		if (un == 0)
122			un = 1;
123		if (um == 0)
124			um = 1;
125
126		*n = un;
127		*m = um;
128	}
129}
130
131static int cdce925_pll_determine_rate(struct clk_hw *hw,
132				      struct clk_rate_request *req)
133{
134	u16 n, m;
135
136	cdce925_pll_find_rate(req->rate, req->best_parent_rate, &n, &m);
137	req->rate = (long)cdce925_pll_calculate_rate(req->best_parent_rate, n, m);
138
139	return 0;
140}
141
142static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate,
143		unsigned long parent_rate)
144{
145	struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
146
147	if (!rate || (rate == parent_rate)) {
148		data->m = 0; /* Bypass mode */
149		data->n = 0;
150		return 0;
151	}
152
153	if ((rate < CDCE925_PLL_FREQUENCY_MIN) ||
154		(rate > CDCE925_PLL_FREQUENCY_MAX)) {
155		pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate);
156		return -EINVAL;
157	}
158
159	if (rate < parent_rate) {
160		pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__,
161			rate, parent_rate);
162		return -EINVAL;
163	}
164
165	cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m);
166	return 0;
167}
168
169
170/* calculate p = max(0, 4 - int(log2 (n/m))) */
171static u8 cdce925_pll_calc_p(u16 n, u16 m)
172{
173	u8 p;
174	u16 r = n / m;
175
176	if (r >= 16)
177		return 0;
178	p = 4;
179	while (r > 1) {
180		r >>= 1;
181		--p;
182	}
183	return p;
184}
185
186/* Returns VCO range bits for VCO1_0_RANGE */
187static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m)
188{
189	struct clk *parent = clk_get_parent(hw->clk);
190	unsigned long rate = clk_get_rate(parent);
191
192	rate = mult_frac(rate, (unsigned long)n, (unsigned long)m);
193	if (rate >= 175000000)
194		return 0x3;
195	if (rate >= 150000000)
196		return 0x02;
197	if (rate >= 125000000)
198		return 0x01;
199	return 0x00;
200}
201
202/* I2C clock, hence everything must happen in (un)prepare because this
203 * may sleep */
204static int cdce925_pll_prepare(struct clk_hw *hw)
205{
206	struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
207	u16 n = data->n;
208	u16 m = data->m;
209	u16 r;
210	u8 q;
211	u8 p;
212	u16 nn;
213	u8 pll[4]; /* Bits are spread out over 4 byte registers */
214	u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
215	unsigned i;
216
217	if ((!m || !n) || (m == n)) {
218		/* Set PLL mux to bypass mode, leave the rest as is */
219		regmap_update_bits(data->chip->regmap,
220			reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
221	} else {
222		/* According to data sheet: */
223		/* p = max(0, 4 - int(log2 (n/m))) */
224		p = cdce925_pll_calc_p(n, m);
225		/* nn = n * 2^p */
226		nn = n * BIT(p);
227		/* q = int(nn/m) */
228		q = nn / m;
229		if ((q < 16) || (q > 63)) {
230			pr_debug("%s invalid q=%d\n", __func__, q);
231			return -EINVAL;
232		}
233		r = nn - (m*q);
234		if (r > 511) {
235			pr_debug("%s invalid r=%d\n", __func__, r);
236			return -EINVAL;
237		}
238		pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__,
239			n, m, p, q, r);
240		/* encode into register bits */
241		pll[0] = n >> 4;
242		pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F);
243		pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07);
244		pll[3] = ((q & 0x07) << 5) | (p << 2) |
245				cdce925_pll_calc_range_bits(hw, n, m);
246		/* Write to registers */
247		for (i = 0; i < ARRAY_SIZE(pll); ++i)
248			regmap_write(data->chip->regmap,
249				reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]);
250		/* Enable PLL */
251		regmap_update_bits(data->chip->regmap,
252			reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00);
253	}
254
255	return 0;
256}
257
258static void cdce925_pll_unprepare(struct clk_hw *hw)
259{
260	struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
261	u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
262
263	regmap_update_bits(data->chip->regmap,
264			reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
265}
266
267static const struct clk_ops cdce925_pll_ops = {
268	.prepare = cdce925_pll_prepare,
269	.unprepare = cdce925_pll_unprepare,
270	.recalc_rate = cdce925_pll_recalc_rate,
271	.determine_rate = cdce925_pll_determine_rate,
272	.set_rate = cdce925_pll_set_rate,
273};
274
275
276static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv)
277{
278	switch (data->index) {
279	case 0:
280		regmap_update_bits(data->chip->regmap,
281			CDCE925_REG_Y1SPIPDIVH,
282			0x03, (pdiv >> 8) & 0x03);
283		regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF);
284		break;
285	case 1:
286		regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv);
287		break;
288	case 2:
289		regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv);
290		break;
291	case 3:
292		regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv);
293		break;
294	case 4:
295		regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv);
296		break;
297	case 5:
298		regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv);
299		break;
300	case 6:
301		regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv);
302		break;
303	case 7:
304		regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv);
305		break;
306	case 8:
307		regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv);
308		break;
309	}
310}
311
312static void cdce925_clk_activate(struct clk_cdce925_output *data)
313{
314	switch (data->index) {
315	case 0:
316		regmap_update_bits(data->chip->regmap,
317			CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c);
318		break;
319	case 1:
320	case 2:
321		regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03);
322		break;
323	case 3:
324	case 4:
325		regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03);
326		break;
327	case 5:
328	case 6:
329		regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03);
330		break;
331	case 7:
332	case 8:
333		regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03);
334		break;
335	}
336}
337
338static int cdce925_clk_prepare(struct clk_hw *hw)
339{
340	struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
341
342	cdce925_clk_set_pdiv(data, data->pdiv);
343	cdce925_clk_activate(data);
344	return 0;
345}
346
347static void cdce925_clk_unprepare(struct clk_hw *hw)
348{
349	struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
350
351	/* Disable clock by setting divider to "0" */
352	cdce925_clk_set_pdiv(data, 0);
353}
354
355static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw,
356		unsigned long parent_rate)
357{
358	struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
359
360	if (data->pdiv)
361		return parent_rate / data->pdiv;
362	return 0;
363}
364
365static u16 cdce925_calc_divider(unsigned long rate,
366		unsigned long parent_rate)
367{
368	unsigned long divider;
369
370	if (!rate)
371		return 0;
372	if (rate >= parent_rate)
373		return 1;
374
375	divider = DIV_ROUND_CLOSEST(parent_rate, rate);
376	if (divider > 0x7F)
377		divider = 0x7F;
378
379	return (u16)divider;
380}
381
382static unsigned long cdce925_clk_best_parent_rate(
383	struct clk_hw *hw, unsigned long rate)
384{
385	struct clk *pll = clk_get_parent(hw->clk);
386	struct clk *root = clk_get_parent(pll);
387	unsigned long root_rate = clk_get_rate(root);
388	unsigned long best_rate_error = rate;
389	u16 pdiv_min;
390	u16 pdiv_max;
391	u16 pdiv_best;
392	u16 pdiv_now;
393
394	if (root_rate % rate == 0)
395		return root_rate; /* Don't need the PLL, use bypass */
396
397	pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate));
398	pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate);
399
400	if (pdiv_min > pdiv_max)
401		return 0; /* No can do? */
402
403	pdiv_best = pdiv_min;
404	for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) {
405		unsigned long target_rate = rate * pdiv_now;
406		long pll_rate = clk_round_rate(pll, target_rate);
407		unsigned long actual_rate;
408		unsigned long rate_error;
409
410		if (pll_rate <= 0)
411			continue;
412		actual_rate = pll_rate / pdiv_now;
413		rate_error = abs((long)actual_rate - (long)rate);
414		if (rate_error < best_rate_error) {
415			pdiv_best = pdiv_now;
416			best_rate_error = rate_error;
417		}
418		/* TODO: Consider PLL frequency based on smaller n/m values
419		 * and pick the better one if the error is equal */
420	}
421
422	return rate * pdiv_best;
423}
424
425static int cdce925_clk_determine_rate(struct clk_hw *hw,
426				      struct clk_rate_request *req)
427{
428	unsigned long l_parent_rate = req->best_parent_rate;
429	u16 divider = cdce925_calc_divider(req->rate, l_parent_rate);
430
431	if (l_parent_rate / divider != req->rate) {
432		l_parent_rate = cdce925_clk_best_parent_rate(hw, req->rate);
433		divider = cdce925_calc_divider(req->rate, l_parent_rate);
434		req->best_parent_rate = l_parent_rate;
435	}
436
437	if (divider)
438		req->rate = (long)(l_parent_rate / divider);
439	else
440		req->rate = 0;
441
442	return 0;
443}
444
445static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate,
446		unsigned long parent_rate)
447{
448	struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
449
450	data->pdiv = cdce925_calc_divider(rate, parent_rate);
451
452	return 0;
453}
454
455static const struct clk_ops cdce925_clk_ops = {
456	.prepare = cdce925_clk_prepare,
457	.unprepare = cdce925_clk_unprepare,
458	.recalc_rate = cdce925_clk_recalc_rate,
459	.determine_rate = cdce925_clk_determine_rate,
460	.set_rate = cdce925_clk_set_rate,
461};
462
463
464static u16 cdce925_y1_calc_divider(unsigned long rate,
465		unsigned long parent_rate)
466{
467	unsigned long divider;
468
469	if (!rate)
470		return 0;
471	if (rate >= parent_rate)
472		return 1;
473
474	divider = DIV_ROUND_CLOSEST(parent_rate, rate);
475	if (divider > 0x3FF) /* Y1 has 10-bit divider */
476		divider = 0x3FF;
477
478	return (u16)divider;
479}
480
481static int cdce925_clk_y1_determine_rate(struct clk_hw *hw,
482					 struct clk_rate_request *req)
483{
484	unsigned long l_parent_rate = req->best_parent_rate;
485	u16 divider = cdce925_y1_calc_divider(req->rate, l_parent_rate);
486
487	if (divider)
488		req->rate = (long)(l_parent_rate / divider);
489	else
490		req->rate = 0;
491
492	return 0;
493}
494
495static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate,
496		unsigned long parent_rate)
497{
498	struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
499
500	data->pdiv = cdce925_y1_calc_divider(rate, parent_rate);
501
502	return 0;
503}
504
505static const struct clk_ops cdce925_clk_y1_ops = {
506	.prepare = cdce925_clk_prepare,
507	.unprepare = cdce925_clk_unprepare,
508	.recalc_rate = cdce925_clk_recalc_rate,
509	.determine_rate = cdce925_clk_y1_determine_rate,
510	.set_rate = cdce925_clk_y1_set_rate,
511};
512
513#define CDCE925_I2C_COMMAND_BLOCK_TRANSFER	0x00
514#define CDCE925_I2C_COMMAND_BYTE_TRANSFER	0x80
515
516static int cdce925_regmap_i2c_write(
517	void *context, const void *data, size_t count)
518{
519	struct device *dev = context;
520	struct i2c_client *i2c = to_i2c_client(dev);
521	int ret;
522	u8 reg_data[2];
523
524	if (count != 2)
525		return -ENOTSUPP;
526
527	/* First byte is command code */
528	reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0];
529	reg_data[1] = ((u8 *)data)[1];
530
531	dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count,
532			reg_data[0], reg_data[1]);
533
534	ret = i2c_master_send(i2c, reg_data, count);
535	if (likely(ret == count))
536		return 0;
537	else if (ret < 0)
538		return ret;
539	else
540		return -EIO;
541}
542
543static int cdce925_regmap_i2c_read(void *context,
544	   const void *reg, size_t reg_size, void *val, size_t val_size)
545{
546	struct device *dev = context;
547	struct i2c_client *i2c = to_i2c_client(dev);
548	struct i2c_msg xfer[2];
549	int ret;
550	u8 reg_data[2];
551
552	if (reg_size != 1)
553		return -ENOTSUPP;
554
555	xfer[0].addr = i2c->addr;
556	xfer[0].flags = 0;
557	xfer[0].buf = reg_data;
558	if (val_size == 1) {
559		reg_data[0] =
560			CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0];
561		xfer[0].len = 1;
562	} else {
563		reg_data[0] =
564			CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0];
565		reg_data[1] = val_size;
566		xfer[0].len = 2;
567	}
568
569	xfer[1].addr = i2c->addr;
570	xfer[1].flags = I2C_M_RD;
571	xfer[1].len = val_size;
572	xfer[1].buf = val;
573
574	ret = i2c_transfer(i2c->adapter, xfer, 2);
575	if (likely(ret == 2)) {
576		dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__,
577				reg_size, val_size, reg_data[0], *((u8 *)val));
578		return 0;
579	} else if (ret < 0)
580		return ret;
581	else
582		return -EIO;
583}
584
585static struct clk_hw *
586of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data)
587{
588	struct clk_cdce925_chip *data = _data;
589	unsigned int idx = clkspec->args[0];
590
591	if (idx >= ARRAY_SIZE(data->clk)) {
592		pr_err("%s: invalid index %u\n", __func__, idx);
593		return ERR_PTR(-EINVAL);
594	}
595
596	return &data->clk[idx].hw;
597}
598
599static int cdce925_regulator_enable(struct device *dev, const char *name)
600{
601	int err;
602
603	err = devm_regulator_get_enable(dev, name);
604	if (err)
605		dev_err_probe(dev, err, "Failed to enable %s:\n", name);
606
607	return err;
608}
609
610/* The CDCE925 uses a funky way to read/write registers. Bulk mode is
611 * just weird, so just use the single byte mode exclusively. */
612static const struct regmap_bus regmap_cdce925_bus = {
613	.write = cdce925_regmap_i2c_write,
614	.read = cdce925_regmap_i2c_read,
615};
616
617static int cdce925_probe(struct i2c_client *client)
618{
619	struct clk_cdce925_chip *data;
620	struct device_node *node = client->dev.of_node;
621	const char *parent_name;
622	const char *pll_clk_name[MAX_NUMBER_OF_PLLS] = {NULL,};
623	struct clk_init_data init;
624	u32 value;
625	int i;
626	int err;
627	struct device_node *np_output;
628	char child_name[6];
629	struct regmap_config config = {
630		.name = "configuration0",
631		.reg_bits = 8,
632		.val_bits = 8,
633		.cache_type = REGCACHE_MAPLE,
634	};
635
636	dev_dbg(&client->dev, "%s\n", __func__);
637
638	err = cdce925_regulator_enable(&client->dev, "vdd");
639	if (err)
640		return err;
641
642	err = cdce925_regulator_enable(&client->dev, "vddout");
643	if (err)
644		return err;
645
646	data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
647	if (!data)
648		return -ENOMEM;
649
650	data->i2c_client = client;
651	data->chip_info = i2c_get_match_data(client);
652	config.max_register = CDCE925_OFFSET_PLL +
653		data->chip_info->num_plls * 0x10 - 1;
654	data->regmap = devm_regmap_init(&client->dev, &regmap_cdce925_bus,
655			&client->dev, &config);
656	if (IS_ERR(data->regmap)) {
657		dev_err(&client->dev, "failed to allocate register map\n");
658		return PTR_ERR(data->regmap);
659	}
660	i2c_set_clientdata(client, data);
661
662	parent_name = of_clk_get_parent_name(node, 0);
663	if (!parent_name) {
664		dev_err(&client->dev, "missing parent clock\n");
665		return -ENODEV;
666	}
667	dev_dbg(&client->dev, "parent is: %s\n", parent_name);
668
669	if (of_property_read_u32(node, "xtal-load-pf", &value) == 0)
670		regmap_write(data->regmap,
671			CDCE925_REG_XCSEL, (value << 3) & 0xF8);
672	/* PWDN bit */
673	regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0);
674
675	/* Set input source for Y1 to be the XTAL */
676	regmap_update_bits(data->regmap, 0x02, BIT(7), 0);
677
678	init.ops = &cdce925_pll_ops;
679	init.flags = 0;
680	init.parent_names = &parent_name;
681	init.num_parents = 1;
682
683	/* Register PLL clocks */
684	for (i = 0; i < data->chip_info->num_plls; ++i) {
685		pll_clk_name[i] = kasprintf(GFP_KERNEL, "%pOFn.pll%d",
686			client->dev.of_node, i);
687		if (!pll_clk_name[i]) {
688			err = -ENOMEM;
689			goto error;
690		}
691		init.name = pll_clk_name[i];
692		data->pll[i].chip = data;
693		data->pll[i].hw.init = &init;
694		data->pll[i].index = i;
695		err = devm_clk_hw_register(&client->dev, &data->pll[i].hw);
696		if (err) {
697			dev_err(&client->dev, "Failed register PLL %d\n", i);
698			goto error;
699		}
700		sprintf(child_name, "PLL%d", i+1);
701		np_output = of_get_child_by_name(node, child_name);
702		if (!np_output)
703			continue;
704		if (!of_property_read_u32(np_output,
705			"clock-frequency", &value)) {
706			err = clk_set_rate(data->pll[i].hw.clk, value);
707			if (err)
708				dev_err(&client->dev,
709					"unable to set PLL frequency %ud\n",
710					value);
711		}
712		if (!of_property_read_u32(np_output,
713			"spread-spectrum", &value)) {
714			u8 flag = of_property_read_bool(np_output,
715				"spread-spectrum-center") ? 0x80 : 0x00;
716			regmap_update_bits(data->regmap,
717				0x16 + (i*CDCE925_OFFSET_PLL),
718				0x80, flag);
719			regmap_update_bits(data->regmap,
720				0x12 + (i*CDCE925_OFFSET_PLL),
721				0x07, value & 0x07);
722		}
723		of_node_put(np_output);
724	}
725
726	/* Register output clock Y1 */
727	init.ops = &cdce925_clk_y1_ops;
728	init.flags = 0;
729	init.num_parents = 1;
730	init.parent_names = &parent_name; /* Mux Y1 to input */
731	init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node);
732	if (!init.name) {
733		err = -ENOMEM;
734		goto error;
735	}
736	data->clk[0].chip = data;
737	data->clk[0].hw.init = &init;
738	data->clk[0].index = 0;
739	data->clk[0].pdiv = 1;
740	err = devm_clk_hw_register(&client->dev, &data->clk[0].hw);
741	kfree(init.name); /* clock framework made a copy of the name */
742	if (err) {
743		dev_err(&client->dev, "clock registration Y1 failed\n");
744		goto error;
745	}
746
747	/* Register output clocks Y2 .. Y5*/
748	init.ops = &cdce925_clk_ops;
749	init.flags = CLK_SET_RATE_PARENT;
750	init.num_parents = 1;
751	for (i = 1; i < data->chip_info->num_outputs; ++i) {
752		init.name = kasprintf(GFP_KERNEL, "%pOFn.Y%d",
753			client->dev.of_node, i+1);
754		if (!init.name) {
755			err = -ENOMEM;
756			goto error;
757		}
758		data->clk[i].chip = data;
759		data->clk[i].hw.init = &init;
760		data->clk[i].index = i;
761		data->clk[i].pdiv = 1;
762		switch (i) {
763		case 1:
764		case 2:
765			/* Mux Y2/3 to PLL1 */
766			init.parent_names = &pll_clk_name[0];
767			break;
768		case 3:
769		case 4:
770			/* Mux Y4/5 to PLL2 */
771			init.parent_names = &pll_clk_name[1];
772			break;
773		case 5:
774		case 6:
775			/* Mux Y6/7 to PLL3 */
776			init.parent_names = &pll_clk_name[2];
777			break;
778		case 7:
779		case 8:
780			/* Mux Y8/9 to PLL4 */
781			init.parent_names = &pll_clk_name[3];
782			break;
783		}
784		err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
785		kfree(init.name); /* clock framework made a copy of the name */
786		if (err) {
787			dev_err(&client->dev, "clock registration failed\n");
788			goto error;
789		}
790	}
791
792	/* Register the output clocks */
793	err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get,
794				  data);
795	if (err)
796		dev_err(&client->dev, "unable to add OF clock provider\n");
797
798	err = 0;
799
800error:
801	for (i = 0; i < data->chip_info->num_plls; ++i)
802		/* clock framework made a copy of the name */
803		kfree(pll_clk_name[i]);
804
805	return err;
806}
807
808static const struct clk_cdce925_chip_info clk_cdce913_info = {
809	.num_plls = 1,
810	.num_outputs = 3,
811};
812
813static const struct clk_cdce925_chip_info clk_cdce925_info = {
814	.num_plls = 2,
815	.num_outputs = 5,
816};
817
818static const struct clk_cdce925_chip_info clk_cdce937_info = {
819	.num_plls = 3,
820	.num_outputs = 7,
821};
822
823static const struct clk_cdce925_chip_info clk_cdce949_info = {
824	.num_plls = 4,
825	.num_outputs = 9,
826};
827
828static const struct i2c_device_id cdce925_id[] = {
829	{ "cdce913", (kernel_ulong_t)&clk_cdce913_info },
830	{ "cdce925", (kernel_ulong_t)&clk_cdce925_info },
831	{ "cdce937", (kernel_ulong_t)&clk_cdce937_info },
832	{ "cdce949", (kernel_ulong_t)&clk_cdce949_info },
833	{ }
834};
835MODULE_DEVICE_TABLE(i2c, cdce925_id);
836
837static const struct of_device_id clk_cdce925_of_match[] = {
838	{ .compatible = "ti,cdce913", .data = &clk_cdce913_info },
839	{ .compatible = "ti,cdce925", .data = &clk_cdce925_info },
840	{ .compatible = "ti,cdce937", .data = &clk_cdce937_info },
841	{ .compatible = "ti,cdce949", .data = &clk_cdce949_info },
842	{ }
843};
844MODULE_DEVICE_TABLE(of, clk_cdce925_of_match);
845
846static struct i2c_driver cdce925_driver = {
847	.driver = {
848		.name = "cdce925",
849		.of_match_table = clk_cdce925_of_match,
850	},
851	.probe		= cdce925_probe,
852	.id_table	= cdce925_id,
853};
854module_i2c_driver(cdce925_driver);
855
856MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
857MODULE_DESCRIPTION("TI CDCE913/925/937/949 driver");
858MODULE_LICENSE("GPL");