clk-bcm2835.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2010,2015 Broadcom
   4 * Copyright (C) 2012 Stephen Warren
   5 */
   6
   7/**
   8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
   9 *
  10 * The clock tree on the 2835 has several levels.  There's a root
  11 * oscillator running at 19.2Mhz.  After the oscillator there are 5
  12 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
  13 * and "HDMI displays".  Those 5 PLLs each can divide their output to
  14 * produce up to 4 channels.  Finally, there is the level of clocks to
  15 * be consumed by other hardware components (like "H264" or "HDMI
  16 * state machine"), which divide off of some subset of the PLL
  17 * channels.
  18 *
  19 * All of the clocks in the tree are exposed in the DT, because the DT
  20 * may want to make assignments of the final layer of clocks to the
  21 * PLL channels, and some components of the hardware will actually
  22 * skip layers of the tree (for example, the pixel clock comes
  23 * directly from the PLLH PIX channel without using a CM_*CTL clock
  24 * generator).
  25 */
  26
  27#include <linux/clk-provider.h>
  28#include <linux/clkdev.h>
  29#include <linux/clk.h>
  30#include <linux/debugfs.h>
  31#include <linux/delay.h>
  32#include <linux/io.h>
  33#include <linux/math.h>
  34#include <linux/module.h>
  35#include <linux/of.h>
  36#include <linux/platform_device.h>
  37#include <linux/slab.h>
  38#include <dt-bindings/clock/bcm2835.h>
  39
  40#define CM_PASSWORD		0x5a000000
  41
  42#define CM_GNRICCTL		0x000
  43#define CM_GNRICDIV		0x004
  44# define CM_DIV_FRAC_BITS	12
  45# define CM_DIV_FRAC_MASK	GENMASK(CM_DIV_FRAC_BITS - 1, 0)
  46
  47#define CM_VPUCTL		0x008
  48#define CM_VPUDIV		0x00c
  49#define CM_SYSCTL		0x010
  50#define CM_SYSDIV		0x014
  51#define CM_PERIACTL		0x018
  52#define CM_PERIADIV		0x01c
  53#define CM_PERIICTL		0x020
  54#define CM_PERIIDIV		0x024
  55#define CM_H264CTL		0x028
  56#define CM_H264DIV		0x02c
  57#define CM_ISPCTL		0x030
  58#define CM_ISPDIV		0x034
  59#define CM_V3DCTL		0x038
  60#define CM_V3DDIV		0x03c
  61#define CM_CAM0CTL		0x040
  62#define CM_CAM0DIV		0x044
  63#define CM_CAM1CTL		0x048
  64#define CM_CAM1DIV		0x04c
  65#define CM_CCP2CTL		0x050
  66#define CM_CCP2DIV		0x054
  67#define CM_DSI0ECTL		0x058
  68#define CM_DSI0EDIV		0x05c
  69#define CM_DSI0PCTL		0x060
  70#define CM_DSI0PDIV		0x064
  71#define CM_DPICTL		0x068
  72#define CM_DPIDIV		0x06c
  73#define CM_GP0CTL		0x070
  74#define CM_GP0DIV		0x074
  75#define CM_GP1CTL		0x078
  76#define CM_GP1DIV		0x07c
  77#define CM_GP2CTL		0x080
  78#define CM_GP2DIV		0x084
  79#define CM_HSMCTL		0x088
  80#define CM_HSMDIV		0x08c
  81#define CM_OTPCTL		0x090
  82#define CM_OTPDIV		0x094
  83#define CM_PCMCTL		0x098
  84#define CM_PCMDIV		0x09c
  85#define CM_PWMCTL		0x0a0
  86#define CM_PWMDIV		0x0a4
  87#define CM_SLIMCTL		0x0a8
  88#define CM_SLIMDIV		0x0ac
  89#define CM_SMICTL		0x0b0
  90#define CM_SMIDIV		0x0b4
  91/* no definition for 0x0b8  and 0x0bc */
  92#define CM_TCNTCTL		0x0c0
  93# define CM_TCNT_SRC1_SHIFT		12
  94#define CM_TCNTCNT		0x0c4
  95#define CM_TECCTL		0x0c8
  96#define CM_TECDIV		0x0cc
  97#define CM_TD0CTL		0x0d0
  98#define CM_TD0DIV		0x0d4
  99#define CM_TD1CTL		0x0d8
 100#define CM_TD1DIV		0x0dc
 101#define CM_TSENSCTL		0x0e0
 102#define CM_TSENSDIV		0x0e4
 103#define CM_TIMERCTL		0x0e8
 104#define CM_TIMERDIV		0x0ec
 105#define CM_UARTCTL		0x0f0
 106#define CM_UARTDIV		0x0f4
 107#define CM_VECCTL		0x0f8
 108#define CM_VECDIV		0x0fc
 109#define CM_PULSECTL		0x190
 110#define CM_PULSEDIV		0x194
 111#define CM_SDCCTL		0x1a8
 112#define CM_SDCDIV		0x1ac
 113#define CM_ARMCTL		0x1b0
 114#define CM_AVEOCTL		0x1b8
 115#define CM_AVEODIV		0x1bc
 116#define CM_EMMCCTL		0x1c0
 117#define CM_EMMCDIV		0x1c4
 118#define CM_EMMC2CTL		0x1d0
 119#define CM_EMMC2DIV		0x1d4
 120
 121/* General bits for the CM_*CTL regs */
 122# define CM_ENABLE			BIT(4)
 123# define CM_KILL			BIT(5)
 124# define CM_GATE_BIT			6
 125# define CM_GATE			BIT(CM_GATE_BIT)
 126# define CM_BUSY			BIT(7)
 127# define CM_BUSYD			BIT(8)
 128# define CM_FRAC			BIT(9)
 129# define CM_SRC_SHIFT			0
 130# define CM_SRC_BITS			4
 131# define CM_SRC_MASK			0xf
 132# define CM_SRC_GND			0
 133# define CM_SRC_OSC			1
 134# define CM_SRC_TESTDEBUG0		2
 135# define CM_SRC_TESTDEBUG1		3
 136# define CM_SRC_PLLA_CORE		4
 137# define CM_SRC_PLLA_PER		4
 138# define CM_SRC_PLLC_CORE0		5
 139# define CM_SRC_PLLC_PER		5
 140# define CM_SRC_PLLC_CORE1		8
 141# define CM_SRC_PLLD_CORE		6
 142# define CM_SRC_PLLD_PER		6
 143# define CM_SRC_PLLH_AUX		7
 144# define CM_SRC_PLLC_CORE1		8
 145# define CM_SRC_PLLC_CORE2		9
 146
 147#define CM_OSCCOUNT		0x100
 148
 149#define CM_PLLA			0x104
 150# define CM_PLL_ANARST			BIT(8)
 151# define CM_PLLA_HOLDPER		BIT(7)
 152# define CM_PLLA_LOADPER		BIT(6)
 153# define CM_PLLA_HOLDCORE		BIT(5)
 154# define CM_PLLA_LOADCORE		BIT(4)
 155# define CM_PLLA_HOLDCCP2		BIT(3)
 156# define CM_PLLA_LOADCCP2		BIT(2)
 157# define CM_PLLA_HOLDDSI0		BIT(1)
 158# define CM_PLLA_LOADDSI0		BIT(0)
 159
 160#define CM_PLLC			0x108
 161# define CM_PLLC_HOLDPER		BIT(7)
 162# define CM_PLLC_LOADPER		BIT(6)
 163# define CM_PLLC_HOLDCORE2		BIT(5)
 164# define CM_PLLC_LOADCORE2		BIT(4)
 165# define CM_PLLC_HOLDCORE1		BIT(3)
 166# define CM_PLLC_LOADCORE1		BIT(2)
 167# define CM_PLLC_HOLDCORE0		BIT(1)
 168# define CM_PLLC_LOADCORE0		BIT(0)
 169
 170#define CM_PLLD			0x10c
 171# define CM_PLLD_HOLDPER		BIT(7)
 172# define CM_PLLD_LOADPER		BIT(6)
 173# define CM_PLLD_HOLDCORE		BIT(5)
 174# define CM_PLLD_LOADCORE		BIT(4)
 175# define CM_PLLD_HOLDDSI1		BIT(3)
 176# define CM_PLLD_LOADDSI1		BIT(2)
 177# define CM_PLLD_HOLDDSI0		BIT(1)
 178# define CM_PLLD_LOADDSI0		BIT(0)
 179
 180#define CM_PLLH			0x110
 181# define CM_PLLH_LOADRCAL		BIT(2)
 182# define CM_PLLH_LOADAUX		BIT(1)
 183# define CM_PLLH_LOADPIX		BIT(0)
 184
 185#define CM_LOCK			0x114
 186# define CM_LOCK_FLOCKH			BIT(12)
 187# define CM_LOCK_FLOCKD			BIT(11)
 188# define CM_LOCK_FLOCKC			BIT(10)
 189# define CM_LOCK_FLOCKB			BIT(9)
 190# define CM_LOCK_FLOCKA			BIT(8)
 191
 192#define CM_EVENT		0x118
 193#define CM_DSI1ECTL		0x158
 194#define CM_DSI1EDIV		0x15c
 195#define CM_DSI1PCTL		0x160
 196#define CM_DSI1PDIV		0x164
 197#define CM_DFTCTL		0x168
 198#define CM_DFTDIV		0x16c
 199
 200#define CM_PLLB			0x170
 201# define CM_PLLB_HOLDARM		BIT(1)
 202# define CM_PLLB_LOADARM		BIT(0)
 203
 204#define A2W_PLLA_CTRL		0x1100
 205#define A2W_PLLC_CTRL		0x1120
 206#define A2W_PLLD_CTRL		0x1140
 207#define A2W_PLLH_CTRL		0x1160
 208#define A2W_PLLB_CTRL		0x11e0
 209# define A2W_PLL_CTRL_PRST_DISABLE	BIT(17)
 210# define A2W_PLL_CTRL_PWRDN		BIT(16)
 211# define A2W_PLL_CTRL_PDIV_MASK		0x000007000
 212# define A2W_PLL_CTRL_PDIV_SHIFT	12
 213# define A2W_PLL_CTRL_NDIV_MASK		0x0000003ff
 214# define A2W_PLL_CTRL_NDIV_SHIFT	0
 215
 216#define A2W_PLLA_ANA0		0x1010
 217#define A2W_PLLC_ANA0		0x1030
 218#define A2W_PLLD_ANA0		0x1050
 219#define A2W_PLLH_ANA0		0x1070
 220#define A2W_PLLB_ANA0		0x10f0
 221
 222#define A2W_PLL_KA_SHIFT	7
 223#define A2W_PLL_KA_MASK		GENMASK(9, 7)
 224#define A2W_PLL_KI_SHIFT	19
 225#define A2W_PLL_KI_MASK		GENMASK(21, 19)
 226#define A2W_PLL_KP_SHIFT	15
 227#define A2W_PLL_KP_MASK		GENMASK(18, 15)
 228
 229#define A2W_PLLH_KA_SHIFT	19
 230#define A2W_PLLH_KA_MASK	GENMASK(21, 19)
 231#define A2W_PLLH_KI_LOW_SHIFT	22
 232#define A2W_PLLH_KI_LOW_MASK	GENMASK(23, 22)
 233#define A2W_PLLH_KI_HIGH_SHIFT	0
 234#define A2W_PLLH_KI_HIGH_MASK	GENMASK(0, 0)
 235#define A2W_PLLH_KP_SHIFT	1
 236#define A2W_PLLH_KP_MASK	GENMASK(4, 1)
 237
 238#define A2W_XOSC_CTRL		0x1190
 239# define A2W_XOSC_CTRL_PLLB_ENABLE	BIT(7)
 240# define A2W_XOSC_CTRL_PLLA_ENABLE	BIT(6)
 241# define A2W_XOSC_CTRL_PLLD_ENABLE	BIT(5)
 242# define A2W_XOSC_CTRL_DDR_ENABLE	BIT(4)
 243# define A2W_XOSC_CTRL_CPR1_ENABLE	BIT(3)
 244# define A2W_XOSC_CTRL_USB_ENABLE	BIT(2)
 245# define A2W_XOSC_CTRL_HDMI_ENABLE	BIT(1)
 246# define A2W_XOSC_CTRL_PLLC_ENABLE	BIT(0)
 247
 248#define A2W_PLLA_FRAC		0x1200
 249#define A2W_PLLC_FRAC		0x1220
 250#define A2W_PLLD_FRAC		0x1240
 251#define A2W_PLLH_FRAC		0x1260
 252#define A2W_PLLB_FRAC		0x12e0
 253# define A2W_PLL_FRAC_MASK		((1 << A2W_PLL_FRAC_BITS) - 1)
 254# define A2W_PLL_FRAC_BITS		20
 255
 256#define A2W_PLL_CHANNEL_DISABLE		BIT(8)
 257#define A2W_PLL_DIV_BITS		8
 258#define A2W_PLL_DIV_SHIFT		0
 259
 260#define A2W_PLLA_DSI0		0x1300
 261#define A2W_PLLA_CORE		0x1400
 262#define A2W_PLLA_PER		0x1500
 263#define A2W_PLLA_CCP2		0x1600
 264
 265#define A2W_PLLC_CORE2		0x1320
 266#define A2W_PLLC_CORE1		0x1420
 267#define A2W_PLLC_PER		0x1520
 268#define A2W_PLLC_CORE0		0x1620
 269
 270#define A2W_PLLD_DSI0		0x1340
 271#define A2W_PLLD_CORE		0x1440
 272#define A2W_PLLD_PER		0x1540
 273#define A2W_PLLD_DSI1		0x1640
 274
 275#define A2W_PLLH_AUX		0x1360
 276#define A2W_PLLH_RCAL		0x1460
 277#define A2W_PLLH_PIX		0x1560
 278#define A2W_PLLH_STS		0x1660
 279
 280#define A2W_PLLH_CTRLR		0x1960
 281#define A2W_PLLH_FRACR		0x1a60
 282#define A2W_PLLH_AUXR		0x1b60
 283#define A2W_PLLH_RCALR		0x1c60
 284#define A2W_PLLH_PIXR		0x1d60
 285#define A2W_PLLH_STSR		0x1e60
 286
 287#define A2W_PLLB_ARM		0x13e0
 288#define A2W_PLLB_SP0		0x14e0
 289#define A2W_PLLB_SP1		0x15e0
 290#define A2W_PLLB_SP2		0x16e0
 291
 292#define LOCK_TIMEOUT_NS		100000000
 293#define BCM2835_MAX_FB_RATE	1750000000u
 294
 295#define SOC_BCM2835		BIT(0)
 296#define SOC_BCM2711		BIT(1)
 297#define SOC_ALL			(SOC_BCM2835 | SOC_BCM2711)
 298
 299/*
 300 * Names of clocks used within the driver that need to be replaced
 301 * with an external parent's name.  This array is in the order that
 302 * the clocks node in the DT references external clocks.
 303 */
 304static const char *const cprman_parent_names[] = {
 305	"xosc",
 306	"dsi0_byte",
 307	"dsi0_ddr2",
 308	"dsi0_ddr",
 309	"dsi1_byte",
 310	"dsi1_ddr2",
 311	"dsi1_ddr",
 312};
 313
 314struct bcm2835_cprman {
 315	struct device *dev;
 316	void __iomem *regs;
 317	spinlock_t regs_lock; /* spinlock for all clocks */
 318	unsigned int soc;
 319
 320	/*
 321	 * Real names of cprman clock parents looked up through
 322	 * of_clk_get_parent_name(), which will be used in the
 323	 * parent_names[] arrays for clock registration.
 324	 */
 325	const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)];
 326
 327	/* Must be last */
 328	struct clk_hw_onecell_data onecell;
 329};
 330
 331struct cprman_plat_data {
 332	unsigned int soc;
 333};
 334
 335static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
 336{
 337	writel(CM_PASSWORD | val, cprman->regs + reg);
 338}
 339
 340static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)
 341{
 342	return readl(cprman->regs + reg);
 343}
 344
 345/* Does a cycle of measuring a clock through the TCNT clock, which may
 346 * source from many other clocks in the system.
 347 */
 348static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,
 349					      u32 tcnt_mux)
 350{
 351	u32 osccount = 19200; /* 1ms */
 352	u32 count;
 353	ktime_t timeout;
 354
 355	spin_lock(&cprman->regs_lock);
 356
 357	cprman_write(cprman, CM_TCNTCTL, CM_KILL);
 358
 359	cprman_write(cprman, CM_TCNTCTL,
 360		     (tcnt_mux & CM_SRC_MASK) |
 361		     (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT);
 362
 363	cprman_write(cprman, CM_OSCCOUNT, osccount);
 364
 365	/* do a kind delay at the start */
 366	mdelay(1);
 367
 368	/* Finish off whatever is left of OSCCOUNT */
 369	timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
 370	while (cprman_read(cprman, CM_OSCCOUNT)) {
 371		if (ktime_after(ktime_get(), timeout)) {
 372			dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n");
 373			count = 0;
 374			goto out;
 375		}
 376		cpu_relax();
 377	}
 378
 379	/* Wait for BUSY to clear. */
 380	timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
 381	while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {
 382		if (ktime_after(ktime_get(), timeout)) {
 383			dev_err(cprman->dev, "timeout waiting for !BUSY\n");
 384			count = 0;
 385			goto out;
 386		}
 387		cpu_relax();
 388	}
 389
 390	count = cprman_read(cprman, CM_TCNTCNT);
 391
 392	cprman_write(cprman, CM_TCNTCTL, 0);
 393
 394out:
 395	spin_unlock(&cprman->regs_lock);
 396
 397	return count * 1000;
 398}
 399
 400static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
 401				   const struct debugfs_reg32 *regs,
 402				   size_t nregs, struct dentry *dentry)
 403{
 404	struct debugfs_regset32 *regset;
 405
 406	regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
 407	if (!regset)
 408		return;
 409
 410	regset->regs = regs;
 411	regset->nregs = nregs;
 412	regset->base = cprman->regs + base;
 413
 414	debugfs_create_regset32("regdump", S_IRUGO, dentry, regset);
 415}
 416
 417struct bcm2835_pll_data {
 418	const char *name;
 419	u32 cm_ctrl_reg;
 420	u32 a2w_ctrl_reg;
 421	u32 frac_reg;
 422	u32 ana_reg_base;
 423	u32 reference_enable_mask;
 424	/* Bit in CM_LOCK to indicate when the PLL has locked. */
 425	u32 lock_mask;
 426	u32 flags;
 427
 428	const struct bcm2835_pll_ana_bits *ana;
 429
 430	unsigned long min_rate;
 431	unsigned long max_rate;
 432	/*
 433	 * Highest rate for the VCO before we have to use the
 434	 * pre-divide-by-2.
 435	 */
 436	unsigned long max_fb_rate;
 437};
 438
 439struct bcm2835_pll_ana_bits {
 440	u32 mask0;
 441	u32 set0;
 442	u32 mask1;
 443	u32 set1;
 444	u32 mask3;
 445	u32 set3;
 446	u32 fb_prediv_mask;
 447};
 448
 449static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {
 450	.mask0 = 0,
 451	.set0 = 0,
 452	.mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK,
 453	.set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT),
 454	.mask3 = A2W_PLL_KA_MASK,
 455	.set3 = (2 << A2W_PLL_KA_SHIFT),
 456	.fb_prediv_mask = BIT(14),
 457};
 458
 459static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {
 460	.mask0 = A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK,
 461	.set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),
 462	.mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK,
 463	.set1 = (6 << A2W_PLLH_KP_SHIFT),
 464	.mask3 = 0,
 465	.set3 = 0,
 466	.fb_prediv_mask = BIT(11),
 467};
 468
 469struct bcm2835_pll_divider_data {
 470	const char *name;
 471	const char *source_pll;
 472
 473	u32 cm_reg;
 474	u32 a2w_reg;
 475
 476	u32 load_mask;
 477	u32 hold_mask;
 478	u32 fixed_divider;
 479	u32 flags;
 480};
 481
 482struct bcm2835_clock_data {
 483	const char *name;
 484
 485	const char *const *parents;
 486	int num_mux_parents;
 487
 488	/* Bitmap encoding which parents accept rate change propagation. */
 489	unsigned int set_rate_parent;
 490
 491	u32 ctl_reg;
 492	u32 div_reg;
 493
 494	/* Number of integer bits in the divider */
 495	u32 int_bits;
 496	/* Number of fractional bits in the divider */
 497	u32 frac_bits;
 498
 499	u32 flags;
 500
 501	bool is_vpu_clock;
 502	bool is_mash_clock;
 503	bool low_jitter;
 504
 505	u32 tcnt_mux;
 506
 507	bool round_up;
 508};
 509
 510struct bcm2835_gate_data {
 511	const char *name;
 512	const char *parent;
 513
 514	u32 ctl_reg;
 515};
 516
 517struct bcm2835_pll {
 518	struct clk_hw hw;
 519	struct bcm2835_cprman *cprman;
 520	const struct bcm2835_pll_data *data;
 521};
 522
 523static int bcm2835_pll_is_on(struct clk_hw *hw)
 524{
 525	struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
 526	struct bcm2835_cprman *cprman = pll->cprman;
 527	const struct bcm2835_pll_data *data = pll->data;
 528
 529	return cprman_read(cprman, data->a2w_ctrl_reg) &
 530		A2W_PLL_CTRL_PRST_DISABLE;
 531}
 532
 533static u32 bcm2835_pll_get_prediv_mask(struct bcm2835_cprman *cprman,
 534				       const struct bcm2835_pll_data *data)
 535{
 536	/*
 537	 * On BCM2711 there isn't a pre-divisor available in the PLL feedback
 538	 * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed
 539	 * for to for VCO RANGE bits.
 540	 */
 541	if (cprman->soc & SOC_BCM2711)
 542		return 0;
 543
 544	return data->ana->fb_prediv_mask;
 545}
 546
 547static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,
 548					     unsigned long parent_rate,
 549					     u32 *ndiv, u32 *fdiv)
 550{
 551	u64 div;
 552
 553	div = (u64)rate << A2W_PLL_FRAC_BITS;
 554	do_div(div, parent_rate);
 555
 556	*ndiv = div >> A2W_PLL_FRAC_BITS;
 557	*fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
 558}
 559
 560static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
 561					   u32 ndiv, u32 fdiv, u32 pdiv)
 562{
 563	u64 rate;
 564
 565	if (pdiv == 0)
 566		return 0;
 567
 568	rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);
 569	do_div(rate, pdiv);
 570	return rate >> A2W_PLL_FRAC_BITS;
 571}
 572
 573static int bcm2835_pll_determine_rate(struct clk_hw *hw,
 574				      struct clk_rate_request *req)
 575{
 576	struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
 577	const struct bcm2835_pll_data *data = pll->data;
 578	u32 ndiv, fdiv;
 579
 580	req->rate = clamp(req->rate, data->min_rate, data->max_rate);
 581
 582	bcm2835_pll_choose_ndiv_and_fdiv(req->rate, req->best_parent_rate,
 583					 &ndiv, &fdiv);
 584
 585	req->rate = bcm2835_pll_rate_from_divisors(req->best_parent_rate,
 586						   ndiv, fdiv,
 587						   1);
 588
 589	return 0;
 590}
 591
 592static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
 593					  unsigned long parent_rate)
 594{
 595	struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
 596	struct bcm2835_cprman *cprman = pll->cprman;
 597	const struct bcm2835_pll_data *data = pll->data;
 598	u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);
 599	u32 ndiv, pdiv, fdiv;
 600	bool using_prediv;
 601
 602	if (parent_rate == 0)
 603		return 0;
 604
 605	fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;
 606	ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT;
 607	pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT;
 608	using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
 609		       bcm2835_pll_get_prediv_mask(cprman, data);
 610
 611	if (using_prediv) {
 612		ndiv *= 2;
 613		fdiv *= 2;
 614	}
 615
 616	return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
 617}
 618
 619static void bcm2835_pll_off(struct clk_hw *hw)
 620{
 621	struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
 622	struct bcm2835_cprman *cprman = pll->cprman;
 623	const struct bcm2835_pll_data *data = pll->data;
 624
 625	spin_lock(&cprman->regs_lock);
 626	cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
 627	cprman_write(cprman, data->a2w_ctrl_reg,
 628		     cprman_read(cprman, data->a2w_ctrl_reg) |
 629		     A2W_PLL_CTRL_PWRDN);
 630	spin_unlock(&cprman->regs_lock);
 631}
 632
 633static int bcm2835_pll_on(struct clk_hw *hw)
 634{
 635	struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
 636	struct bcm2835_cprman *cprman = pll->cprman;
 637	const struct bcm2835_pll_data *data = pll->data;
 638	ktime_t timeout;
 639
 640	cprman_write(cprman, data->a2w_ctrl_reg,
 641		     cprman_read(cprman, data->a2w_ctrl_reg) &
 642		     ~A2W_PLL_CTRL_PWRDN);
 643
 644	/* Take the PLL out of reset. */
 645	spin_lock(&cprman->regs_lock);
 646	cprman_write(cprman, data->cm_ctrl_reg,
 647		     cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
 648	spin_unlock(&cprman->regs_lock);
 649
 650	/* Wait for the PLL to lock. */
 651	timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
 652	while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {
 653		if (ktime_after(ktime_get(), timeout)) {
 654			dev_err(cprman->dev, "%s: couldn't lock PLL\n",
 655				clk_hw_get_name(hw));
 656			return -ETIMEDOUT;
 657		}
 658
 659		cpu_relax();
 660	}
 661
 662	cprman_write(cprman, data->a2w_ctrl_reg,
 663		     cprman_read(cprman, data->a2w_ctrl_reg) |
 664		     A2W_PLL_CTRL_PRST_DISABLE);
 665
 666	return 0;
 667}
 668
 669static void
 670bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana)
 671{
 672	int i;
 673
 674	/*
 675	 * ANA register setup is done as a series of writes to
 676	 * ANA3-ANA0, in that order.  This lets us write all 4
 677	 * registers as a single cycle of the serdes interface (taking
 678	 * 100 xosc clocks), whereas if we were to update ana0, 1, and
 679	 * 3 individually through their partial-write registers, each
 680	 * would be their own serdes cycle.
 681	 */
 682	for (i = 3; i >= 0; i--)
 683		cprman_write(cprman, ana_reg_base + i * 4, ana[i]);
 684}
 685
 686static int bcm2835_pll_set_rate(struct clk_hw *hw,
 687				unsigned long rate, unsigned long parent_rate)
 688{
 689	struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
 690	struct bcm2835_cprman *cprman = pll->cprman;
 691	const struct bcm2835_pll_data *data = pll->data;
 692	u32 prediv_mask = bcm2835_pll_get_prediv_mask(cprman, data);
 693	bool was_using_prediv, use_fb_prediv, do_ana_setup_first;
 694	u32 ndiv, fdiv, a2w_ctl;
 695	u32 ana[4];
 696	int i;
 697
 698	if (rate > data->max_fb_rate) {
 699		use_fb_prediv = true;
 700		rate /= 2;
 701	} else {
 702		use_fb_prediv = false;
 703	}
 704
 705	bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);
 706
 707	for (i = 3; i >= 0; i--)
 708		ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
 709
 710	was_using_prediv = ana[1] & prediv_mask;
 711
 712	ana[0] &= ~data->ana->mask0;
 713	ana[0] |= data->ana->set0;
 714	ana[1] &= ~data->ana->mask1;
 715	ana[1] |= data->ana->set1;
 716	ana[3] &= ~data->ana->mask3;
 717	ana[3] |= data->ana->set3;
 718
 719	if (was_using_prediv && !use_fb_prediv) {
 720		ana[1] &= ~prediv_mask;
 721		do_ana_setup_first = true;
 722	} else if (!was_using_prediv && use_fb_prediv) {
 723		ana[1] |= prediv_mask;
 724		do_ana_setup_first = false;
 725	} else {
 726		do_ana_setup_first = true;
 727	}
 728
 729	/* Unmask the reference clock from the oscillator. */
 730	spin_lock(&cprman->regs_lock);
 731	cprman_write(cprman, A2W_XOSC_CTRL,
 732		     cprman_read(cprman, A2W_XOSC_CTRL) |
 733		     data->reference_enable_mask);
 734	spin_unlock(&cprman->regs_lock);
 735
 736	if (do_ana_setup_first)
 737		bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
 738
 739	/* Set the PLL multiplier from the oscillator. */
 740	cprman_write(cprman, data->frac_reg, fdiv);
 741
 742	a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);
 743	a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK;
 744	a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT;
 745	a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK;
 746	a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT;
 747	cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl);
 748
 749	if (!do_ana_setup_first)
 750		bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
 751
 752	return 0;
 753}
 754
 755static void bcm2835_pll_debug_init(struct clk_hw *hw,
 756				  struct dentry *dentry)
 757{
 758	struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
 759	struct bcm2835_cprman *cprman = pll->cprman;
 760	const struct bcm2835_pll_data *data = pll->data;
 761	struct debugfs_reg32 *regs;
 762
 763	regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
 764	if (!regs)
 765		return;
 766
 767	regs[0].name = "cm_ctrl";
 768	regs[0].offset = data->cm_ctrl_reg;
 769	regs[1].name = "a2w_ctrl";
 770	regs[1].offset = data->a2w_ctrl_reg;
 771	regs[2].name = "frac";
 772	regs[2].offset = data->frac_reg;
 773	regs[3].name = "ana0";
 774	regs[3].offset = data->ana_reg_base + 0 * 4;
 775	regs[4].name = "ana1";
 776	regs[4].offset = data->ana_reg_base + 1 * 4;
 777	regs[5].name = "ana2";
 778	regs[5].offset = data->ana_reg_base + 2 * 4;
 779	regs[6].name = "ana3";
 780	regs[6].offset = data->ana_reg_base + 3 * 4;
 781
 782	bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
 783}
 784
 785static const struct clk_ops bcm2835_pll_clk_ops = {
 786	.is_prepared = bcm2835_pll_is_on,
 787	.prepare = bcm2835_pll_on,
 788	.unprepare = bcm2835_pll_off,
 789	.recalc_rate = bcm2835_pll_get_rate,
 790	.set_rate = bcm2835_pll_set_rate,
 791	.determine_rate = bcm2835_pll_determine_rate,
 792	.debug_init = bcm2835_pll_debug_init,
 793};
 794
 795struct bcm2835_pll_divider {
 796	struct clk_divider div;
 797	struct bcm2835_cprman *cprman;
 798	const struct bcm2835_pll_divider_data *data;
 799};
 800
 801static struct bcm2835_pll_divider *
 802bcm2835_pll_divider_from_hw(struct clk_hw *hw)
 803{
 804	return container_of(hw, struct bcm2835_pll_divider, div.hw);
 805}
 806
 807static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
 808{
 809	struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
 810	struct bcm2835_cprman *cprman = divider->cprman;
 811	const struct bcm2835_pll_divider_data *data = divider->data;
 812
 813	return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
 814}
 815
 816static int bcm2835_pll_divider_determine_rate(struct clk_hw *hw,
 817					      struct clk_rate_request *req)
 818{
 819	return clk_divider_ops.determine_rate(hw, req);
 820}
 821
 822static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
 823						  unsigned long parent_rate)
 824{
 825	return clk_divider_ops.recalc_rate(hw, parent_rate);
 826}
 827
 828static void bcm2835_pll_divider_off(struct clk_hw *hw)
 829{
 830	struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
 831	struct bcm2835_cprman *cprman = divider->cprman;
 832	const struct bcm2835_pll_divider_data *data = divider->data;
 833
 834	spin_lock(&cprman->regs_lock);
 835	cprman_write(cprman, data->cm_reg,
 836		     (cprman_read(cprman, data->cm_reg) &
 837		      ~data->load_mask) | data->hold_mask);
 838	cprman_write(cprman, data->a2w_reg,
 839		     cprman_read(cprman, data->a2w_reg) |
 840		     A2W_PLL_CHANNEL_DISABLE);
 841	spin_unlock(&cprman->regs_lock);
 842}
 843
 844static int bcm2835_pll_divider_on(struct clk_hw *hw)
 845{
 846	struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
 847	struct bcm2835_cprman *cprman = divider->cprman;
 848	const struct bcm2835_pll_divider_data *data = divider->data;
 849
 850	spin_lock(&cprman->regs_lock);
 851	cprman_write(cprman, data->a2w_reg,
 852		     cprman_read(cprman, data->a2w_reg) &
 853		     ~A2W_PLL_CHANNEL_DISABLE);
 854
 855	cprman_write(cprman, data->cm_reg,
 856		     cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
 857	spin_unlock(&cprman->regs_lock);
 858
 859	return 0;
 860}
 861
 862static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
 863					unsigned long rate,
 864					unsigned long parent_rate)
 865{
 866	struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
 867	struct bcm2835_cprman *cprman = divider->cprman;
 868	const struct bcm2835_pll_divider_data *data = divider->data;
 869	u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
 870
 871	div = DIV_ROUND_UP_ULL(parent_rate, rate);
 872
 873	div = min(div, max_div);
 874	if (div == max_div)
 875		div = 0;
 876
 877	cprman_write(cprman, data->a2w_reg, div);
 878	cm = cprman_read(cprman, data->cm_reg);
 879	cprman_write(cprman, data->cm_reg, cm | data->load_mask);
 880	cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
 881
 882	return 0;
 883}
 884
 885static void bcm2835_pll_divider_debug_init(struct clk_hw *hw,
 886					   struct dentry *dentry)
 887{
 888	struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
 889	struct bcm2835_cprman *cprman = divider->cprman;
 890	const struct bcm2835_pll_divider_data *data = divider->data;
 891	struct debugfs_reg32 *regs;
 892
 893	regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
 894	if (!regs)
 895		return;
 896
 897	regs[0].name = "cm";
 898	regs[0].offset = data->cm_reg;
 899	regs[1].name = "a2w";
 900	regs[1].offset = data->a2w_reg;
 901
 902	bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
 903}
 904
 905static const struct clk_ops bcm2835_pll_divider_clk_ops = {
 906	.is_prepared = bcm2835_pll_divider_is_on,
 907	.prepare = bcm2835_pll_divider_on,
 908	.unprepare = bcm2835_pll_divider_off,
 909	.recalc_rate = bcm2835_pll_divider_get_rate,
 910	.set_rate = bcm2835_pll_divider_set_rate,
 911	.determine_rate = bcm2835_pll_divider_determine_rate,
 912	.debug_init = bcm2835_pll_divider_debug_init,
 913};
 914
 915/*
 916 * The CM dividers do fixed-point division, so we can't use the
 917 * generic integer divider code like the PLL dividers do (and we can't
 918 * fake it by having some fixed shifts preceding it in the clock tree,
 919 * because we'd run out of bits in a 32-bit unsigned long).
 920 */
 921struct bcm2835_clock {
 922	struct clk_hw hw;
 923	struct bcm2835_cprman *cprman;
 924	const struct bcm2835_clock_data *data;
 925};
 926
 927static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw)
 928{
 929	return container_of(hw, struct bcm2835_clock, hw);
 930}
 931
 932static int bcm2835_clock_is_on(struct clk_hw *hw)
 933{
 934	struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
 935	struct bcm2835_cprman *cprman = clock->cprman;
 936	const struct bcm2835_clock_data *data = clock->data;
 937
 938	return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;
 939}
 940
 941static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
 942				    unsigned long rate,
 943				    unsigned long parent_rate)
 944{
 945	struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
 946	const struct bcm2835_clock_data *data = clock->data;
 947	u32 unused_frac_mask =
 948		GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
 949	u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
 950	u32 div, mindiv, maxdiv;
 951
 952	do_div(temp, rate);
 953	div = temp;
 954	div &= ~unused_frac_mask;
 955
 956	/* different clamping limits apply for a mash clock */
 957	if (data->is_mash_clock) {
 958		/* clamp to min divider of 2 */
 959		mindiv = 2 << CM_DIV_FRAC_BITS;
 960		/* clamp to the highest possible integer divider */
 961		maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
 962	} else {
 963		/* clamp to min divider of 1 */
 964		mindiv = 1 << CM_DIV_FRAC_BITS;
 965		/* clamp to the highest possible fractional divider */
 966		maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
 967				 CM_DIV_FRAC_BITS - data->frac_bits);
 968	}
 969
 970	/* apply the clamping  limits */
 971	div = max_t(u32, div, mindiv);
 972	div = min_t(u32, div, maxdiv);
 973
 974	return div;
 975}
 976
 977static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
 978						     unsigned long parent_rate,
 979						     u32 div)
 980{
 981	const struct bcm2835_clock_data *data = clock->data;
 982	u64 temp;
 983
 984	if (data->int_bits == 0 && data->frac_bits == 0)
 985		return parent_rate;
 986
 987	/*
 988	 * The divisor is a 12.12 fixed point field, but only some of
 989	 * the bits are populated in any given clock.
 990	 */
 991	div >>= CM_DIV_FRAC_BITS - data->frac_bits;
 992	div &= (1 << (data->int_bits + data->frac_bits)) - 1;
 993
 994	if (div == 0)
 995		return 0;
 996
 997	temp = (u64)parent_rate << data->frac_bits;
 998
 999	do_div(temp, div);
1000
1001	return temp;
1002}
1003
1004static unsigned long bcm2835_round_rate(unsigned long rate)
1005{
1006	unsigned long scaler;
1007	unsigned long limit;
1008
1009	limit = rate / 100000;
1010
1011	scaler = 1;
1012	while (scaler < limit)
1013		scaler *= 10;
1014
1015	/*
1016	 * If increasing a clock by less than 0.1% changes it
1017	 * from ..999.. to ..000.., round up.
1018	 */
1019	if ((rate + scaler - 1) / scaler % 1000 == 0)
1020		rate = roundup(rate, scaler);
1021
1022	return rate;
1023}
1024
1025static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
1026					    unsigned long parent_rate)
1027{
1028	struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1029	struct bcm2835_cprman *cprman = clock->cprman;
1030	const struct bcm2835_clock_data *data = clock->data;
1031	unsigned long rate;
1032	u32 div;
1033
1034	if (data->int_bits == 0 && data->frac_bits == 0)
1035		return parent_rate;
1036
1037	div = cprman_read(cprman, data->div_reg);
1038
1039	rate = bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
1040
1041	if (data->round_up)
1042		rate = bcm2835_round_rate(rate);
1043
1044	return rate;
1045}
1046
1047static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
1048{
1049	struct bcm2835_cprman *cprman = clock->cprman;
1050	const struct bcm2835_clock_data *data = clock->data;
1051	ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
1052
1053	while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {
1054		if (ktime_after(ktime_get(), timeout)) {
1055			dev_err(cprman->dev, "%s: couldn't lock PLL\n",
1056				clk_hw_get_name(&clock->hw));
1057			return;
1058		}
1059		cpu_relax();
1060	}
1061}
1062
1063static void bcm2835_clock_off(struct clk_hw *hw)
1064{
1065	struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1066	struct bcm2835_cprman *cprman = clock->cprman;
1067	const struct bcm2835_clock_data *data = clock->data;
1068
1069	spin_lock(&cprman->regs_lock);
1070	cprman_write(cprman, data->ctl_reg,
1071		     cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);
1072	spin_unlock(&cprman->regs_lock);
1073
1074	/* BUSY will remain high until the divider completes its cycle. */
1075	bcm2835_clock_wait_busy(clock);
1076}
1077
1078static int bcm2835_clock_on(struct clk_hw *hw)
1079{
1080	struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1081	struct bcm2835_cprman *cprman = clock->cprman;
1082	const struct bcm2835_clock_data *data = clock->data;
1083
1084	spin_lock(&cprman->regs_lock);
1085	cprman_write(cprman, data->ctl_reg,
1086		     cprman_read(cprman, data->ctl_reg) |
1087		     CM_ENABLE |
1088		     CM_GATE);
1089	spin_unlock(&cprman->regs_lock);
1090
1091	/* Debug code to measure the clock once it's turned on to see
1092	 * if it's ticking at the rate we expect.
1093	 */
1094	if (data->tcnt_mux && false) {
1095		dev_info(cprman->dev,
1096			 "clk %s: rate %ld, measure %ld\n",
1097			 data->name,
1098			 clk_hw_get_rate(hw),
1099			 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux));
1100	}
1101
1102	return 0;
1103}
1104
1105static int bcm2835_clock_set_rate(struct clk_hw *hw,
1106				  unsigned long rate, unsigned long parent_rate)
1107{
1108	struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1109	struct bcm2835_cprman *cprman = clock->cprman;
1110	const struct bcm2835_clock_data *data = clock->data;
1111	u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate);
1112	u32 ctl;
1113
1114	spin_lock(&cprman->regs_lock);
1115
1116	/*
1117	 * Setting up frac support
1118	 *
1119	 * In principle it is recommended to stop/start the clock first,
1120	 * but as we set CLK_SET_RATE_GATE during registration of the
1121	 * clock this requirement should be take care of by the
1122	 * clk-framework.
1123	 */
1124	ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
1125	ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
1126	cprman_write(cprman, data->ctl_reg, ctl);
1127
1128	cprman_write(cprman, data->div_reg, div);
1129
1130	spin_unlock(&cprman->regs_lock);
1131
1132	return 0;
1133}
1134
1135static bool
1136bcm2835_clk_is_pllc(struct clk_hw *hw)
1137{
1138	if (!hw)
1139		return false;
1140
1141	return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;
1142}
1143
1144static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
1145							int parent_idx,
1146							unsigned long rate,
1147							u32 *div,
1148							unsigned long *prate,
1149							unsigned long *avgrate)
1150{
1151	struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1152	struct bcm2835_cprman *cprman = clock->cprman;
1153	const struct bcm2835_clock_data *data = clock->data;
1154	unsigned long best_rate = 0;
1155	u32 curdiv, mindiv, maxdiv;
1156	struct clk_hw *parent;
1157
1158	parent = clk_hw_get_parent_by_index(hw, parent_idx);
1159
1160	if (!(BIT(parent_idx) & data->set_rate_parent)) {
1161		*prate = clk_hw_get_rate(parent);
1162		*div = bcm2835_clock_choose_div(hw, rate, *prate);
1163
1164		*avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);
1165
1166		if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {
1167			unsigned long high, low;
1168			u32 int_div = *div & ~CM_DIV_FRAC_MASK;
1169
1170			high = bcm2835_clock_rate_from_divisor(clock, *prate,
1171							       int_div);
1172			int_div += CM_DIV_FRAC_MASK + 1;
1173			low = bcm2835_clock_rate_from_divisor(clock, *prate,
1174							      int_div);
1175
1176			/*
1177			 * Return a value which is the maximum deviation
1178			 * below the ideal rate, for use as a metric.
1179			 */
1180			return *avgrate - max(*avgrate - low, high - *avgrate);
1181		}
1182		return *avgrate;
1183	}
1184
1185	if (data->frac_bits)
1186		dev_warn(cprman->dev,
1187			"frac bits are not used when propagating rate change");
1188
1189	/* clamp to min divider of 2 if we're dealing with a mash clock */
1190	mindiv = data->is_mash_clock ? 2 : 1;
1191	maxdiv = BIT(data->int_bits) - 1;
1192
1193	/* TODO: Be smart, and only test a subset of the available divisors. */
1194	for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) {
1195		unsigned long tmp_rate;
1196
1197		tmp_rate = clk_hw_round_rate(parent, rate * curdiv);
1198		tmp_rate /= curdiv;
1199		if (curdiv == mindiv ||
1200		    (tmp_rate > best_rate && tmp_rate <= rate))
1201			best_rate = tmp_rate;
1202
1203		if (best_rate == rate)
1204			break;
1205	}
1206
1207	*div = curdiv << CM_DIV_FRAC_BITS;
1208	*prate = curdiv * best_rate;
1209	*avgrate = best_rate;
1210
1211	return best_rate;
1212}
1213
1214static int bcm2835_clock_determine_rate(struct clk_hw *hw,
1215					struct clk_rate_request *req)
1216{
1217	struct clk_hw *parent, *best_parent = NULL;
1218	bool current_parent_is_pllc;
1219	unsigned long rate, best_rate = 0;
1220	unsigned long prate, best_prate = 0;
1221	unsigned long avgrate, best_avgrate = 0;
1222	size_t i;
1223	u32 div;
1224
1225	current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw));
1226
1227	/*
1228	 * Select parent clock that results in the closest but lower rate
1229	 */
1230	for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
1231		parent = clk_hw_get_parent_by_index(hw, i);
1232		if (!parent)
1233			continue;
1234
1235		/*
1236		 * Don't choose a PLLC-derived clock as our parent
1237		 * unless it had been manually set that way.  PLLC's
1238		 * frequency gets adjusted by the firmware due to
1239		 * over-temp or under-voltage conditions, without
1240		 * prior notification to our clock consumer.
1241		 */
1242		if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)
1243			continue;
1244
1245		rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,
1246							  &div, &prate,
1247							  &avgrate);
1248		if (abs(req->rate - rate) < abs(req->rate - best_rate)) {
1249			best_parent = parent;
1250			best_prate = prate;
1251			best_rate = rate;
1252			best_avgrate = avgrate;
1253		}
1254	}
1255
1256	if (!best_parent)
1257		return -EINVAL;
1258
1259	req->best_parent_hw = best_parent;
1260	req->best_parent_rate = best_prate;
1261
1262	req->rate = best_avgrate;
1263
1264	return 0;
1265}
1266
1267static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)
1268{
1269	struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1270	struct bcm2835_cprman *cprman = clock->cprman;
1271	const struct bcm2835_clock_data *data = clock->data;
1272	u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;
1273
1274	cprman_write(cprman, data->ctl_reg, src);
1275	return 0;
1276}
1277
1278static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
1279{
1280	struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1281	struct bcm2835_cprman *cprman = clock->cprman;
1282	const struct bcm2835_clock_data *data = clock->data;
1283	u32 src = cprman_read(cprman, data->ctl_reg);
1284
1285	return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
1286}
1287
1288static const struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
1289	{
1290		.name = "ctl",
1291		.offset = 0,
1292	},
1293	{
1294		.name = "div",
1295		.offset = 4,
1296	},
1297};
1298
1299static void bcm2835_clock_debug_init(struct clk_hw *hw,
1300				    struct dentry *dentry)
1301{
1302	struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1303	struct bcm2835_cprman *cprman = clock->cprman;
1304	const struct bcm2835_clock_data *data = clock->data;
1305
1306	bcm2835_debugfs_regset(cprman, data->ctl_reg,
1307		bcm2835_debugfs_clock_reg32,
1308		ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
1309		dentry);
1310}
1311
1312static const struct clk_ops bcm2835_clock_clk_ops = {
1313	.is_prepared = bcm2835_clock_is_on,
1314	.prepare = bcm2835_clock_on,
1315	.unprepare = bcm2835_clock_off,
1316	.recalc_rate = bcm2835_clock_get_rate,
1317	.set_rate = bcm2835_clock_set_rate,
1318	.determine_rate = bcm2835_clock_determine_rate,
1319	.set_parent = bcm2835_clock_set_parent,
1320	.get_parent = bcm2835_clock_get_parent,
1321	.debug_init = bcm2835_clock_debug_init,
1322};
1323
1324static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
1325{
1326	return true;
1327}
1328
1329/*
1330 * The VPU clock can never be disabled (it doesn't have an ENABLE
1331 * bit), so it gets its own set of clock ops.
1332 */
1333static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
1334	.is_prepared = bcm2835_vpu_clock_is_on,
1335	.recalc_rate = bcm2835_clock_get_rate,
1336	.set_rate = bcm2835_clock_set_rate,
1337	.determine_rate = bcm2835_clock_determine_rate,
1338	.set_parent = bcm2835_clock_set_parent,
1339	.get_parent = bcm2835_clock_get_parent,
1340	.debug_init = bcm2835_clock_debug_init,
1341};
1342
1343static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
1344					   const void *data)
1345{
1346	const struct bcm2835_pll_data *pll_data = data;
1347	struct bcm2835_pll *pll;
1348	struct clk_init_data init;
1349	int ret;
1350
1351	memset(&init, 0, sizeof(init));
1352
1353	/* All of the PLLs derive from the external oscillator. */
1354	init.parent_names = &cprman->real_parent_names[0];
1355	init.num_parents = 1;
1356	init.name = pll_data->name;
1357	init.ops = &bcm2835_pll_clk_ops;
1358	init.flags = pll_data->flags | CLK_IGNORE_UNUSED;
1359
1360	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1361	if (!pll)
1362		return NULL;
1363
1364	pll->cprman = cprman;
1365	pll->data = pll_data;
1366	pll->hw.init = &init;
1367
1368	ret = devm_clk_hw_register(cprman->dev, &pll->hw);
1369	if (ret) {
1370		kfree(pll);
1371		return NULL;
1372	}
1373	return &pll->hw;
1374}
1375
1376static struct clk_hw *
1377bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
1378			     const void *data)
1379{
1380	const struct bcm2835_pll_divider_data *divider_data = data;
1381	struct bcm2835_pll_divider *divider;
1382	struct clk_init_data init;
1383	const char *divider_name;
1384	int ret;
1385
1386	if (divider_data->fixed_divider != 1) {
1387		divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
1388					      "%s_prediv", divider_data->name);
1389		if (!divider_name)
1390			return NULL;
1391	} else {
1392		divider_name = divider_data->name;
1393	}
1394
1395	memset(&init, 0, sizeof(init));
1396
1397	init.parent_names = &divider_data->source_pll;
1398	init.num_parents = 1;
1399	init.name = divider_name;
1400	init.ops = &bcm2835_pll_divider_clk_ops;
1401	init.flags = divider_data->flags | CLK_IGNORE_UNUSED;
1402
1403	divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
1404	if (!divider)
1405		return NULL;
1406
1407	divider->div.reg = cprman->regs + divider_data->a2w_reg;
1408	divider->div.shift = A2W_PLL_DIV_SHIFT;
1409	divider->div.width = A2W_PLL_DIV_BITS;
1410	divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
1411	divider->div.lock = &cprman->regs_lock;
1412	divider->div.hw.init = &init;
1413	divider->div.table = NULL;
1414
1415	divider->cprman = cprman;
1416	divider->data = divider_data;
1417
1418	ret = devm_clk_hw_register(cprman->dev, &divider->div.hw);
1419	if (ret)
1420		return ERR_PTR(ret);
1421
1422	/*
1423	 * PLLH's channels have a fixed divide by 10 afterwards, which
1424	 * is what our consumers are actually using.
1425	 */
1426	if (divider_data->fixed_divider != 1) {
1427		return clk_hw_register_fixed_factor(cprman->dev,
1428						    divider_data->name,
1429						    divider_name,
1430						    CLK_SET_RATE_PARENT,
1431						    1,
1432						    divider_data->fixed_divider);
1433	}
1434
1435	return &divider->div.hw;
1436}
1437
1438static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
1439					     const void *data)
1440{
1441	const struct bcm2835_clock_data *clock_data = data;
1442	struct bcm2835_clock *clock;
1443	struct clk_init_data init;
1444	const char *parents[1 << CM_SRC_BITS];
1445	size_t i;
1446	int ret;
1447
1448	/*
1449	 * Replace our strings referencing parent clocks with the
1450	 * actual clock-output-name of the parent.
1451	 */
1452	for (i = 0; i < clock_data->num_mux_parents; i++) {
1453		parents[i] = clock_data->parents[i];
1454
1455		ret = match_string(cprman_parent_names,
1456				   ARRAY_SIZE(cprman_parent_names),
1457				   parents[i]);
1458		if (ret >= 0)
1459			parents[i] = cprman->real_parent_names[ret];
1460	}
1461
1462	memset(&init, 0, sizeof(init));
1463	init.parent_names = parents;
1464	init.num_parents = clock_data->num_mux_parents;
1465	init.name = clock_data->name;
1466	init.flags = clock_data->flags | CLK_IGNORE_UNUSED;
1467
1468	/*
1469	 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate
1470	 * rate changes on at least of the parents.
1471	 */
1472	if (clock_data->set_rate_parent)
1473		init.flags |= CLK_SET_RATE_PARENT;
1474
1475	if (clock_data->is_vpu_clock) {
1476		init.ops = &bcm2835_vpu_clock_clk_ops;
1477	} else {
1478		init.ops = &bcm2835_clock_clk_ops;
1479		init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
1480
1481		/* If the clock wasn't actually enabled at boot, it's not
1482		 * critical.
1483		 */
1484		if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))
1485			init.flags &= ~CLK_IS_CRITICAL;
1486	}
1487
1488	clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
1489	if (!clock)
1490		return NULL;
1491
1492	clock->cprman = cprman;
1493	clock->data = clock_data;
1494	clock->hw.init = &init;
1495
1496	ret = devm_clk_hw_register(cprman->dev, &clock->hw);
1497	if (ret)
1498		return ERR_PTR(ret);
1499	return &clock->hw;
1500}
1501
1502static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman,
1503					    const void *data)
1504{
1505	const struct bcm2835_gate_data *gate_data = data;
1506
1507	return clk_hw_register_gate(cprman->dev, gate_data->name,
1508				    gate_data->parent,
1509				    CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1510				    cprman->regs + gate_data->ctl_reg,
1511				    CM_GATE_BIT, 0, &cprman->regs_lock);
1512}
1513
1514struct bcm2835_clk_desc {
1515	struct clk_hw *(*clk_register)(struct bcm2835_cprman *cprman,
1516				       const void *data);
1517	unsigned int supported;
1518	const void *data;
1519};
1520
1521/* assignment helper macros for different clock types */
1522#define _REGISTER(f, s, ...) { .clk_register = f, \
1523			       .supported = s,				\
1524			       .data = __VA_ARGS__ }
1525#define REGISTER_PLL(s, ...)	_REGISTER(&bcm2835_register_pll,	\
1526					  s,				\
1527					  &(struct bcm2835_pll_data)	\
1528					  {__VA_ARGS__})
1529#define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \
1530					   s,				  \
1531					   &(struct bcm2835_pll_divider_data) \
1532					   {__VA_ARGS__})
1533#define REGISTER_CLK(s, ...)	_REGISTER(&bcm2835_register_clock,	\
1534					  s,				\
1535					  &(struct bcm2835_clock_data)	\
1536					  {__VA_ARGS__})
1537#define REGISTER_GATE(s, ...)	_REGISTER(&bcm2835_register_gate,	\
1538					  s,				\
1539					  &(struct bcm2835_gate_data)	\
1540					  {__VA_ARGS__})
1541
1542/* parent mux arrays plus helper macros */
1543
1544/* main oscillator parent mux */
1545static const char *const bcm2835_clock_osc_parents[] = {
1546	"gnd",
1547	"xosc",
1548	"testdebug0",
1549	"testdebug1"
1550};
1551
1552#define REGISTER_OSC_CLK(s, ...)	REGISTER_CLK(			\
1553	s,								\
1554	.num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),	\
1555	.parents = bcm2835_clock_osc_parents,				\
1556	__VA_ARGS__)
1557
1558/* main peripheral parent mux */
1559static const char *const bcm2835_clock_per_parents[] = {
1560	"gnd",
1561	"xosc",
1562	"testdebug0",
1563	"testdebug1",
1564	"plla_per",
1565	"pllc_per",
1566	"plld_per",
1567	"pllh_aux",
1568};
1569
1570#define REGISTER_PER_CLK(s, ...)	REGISTER_CLK(			\
1571	s,								\
1572	.num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),	\
1573	.parents = bcm2835_clock_per_parents,				\
1574	__VA_ARGS__)
1575
1576/*
1577 * Restrict clock sources for the PCM peripheral to the oscillator and
1578 * PLLD_PER because other source may have varying rates or be switched
1579 * off.
1580 *
1581 * Prevent other sources from being selected by replacing their names in
1582 * the list of potential parents with dummy entries (entry index is
1583 * significant).
1584 */
1585static const char *const bcm2835_pcm_per_parents[] = {
1586	"-",
1587	"xosc",
1588	"-",
1589	"-",
1590	"-",
1591	"-",
1592	"plld_per",
1593	"-",
1594};
1595
1596#define REGISTER_PCM_CLK(s, ...)	REGISTER_CLK(			\
1597	s,								\
1598	.num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents),		\
1599	.parents = bcm2835_pcm_per_parents,				\
1600	__VA_ARGS__)
1601
1602/* main vpu parent mux */
1603static const char *const bcm2835_clock_vpu_parents[] = {
1604	"gnd",
1605	"xosc",
1606	"testdebug0",
1607	"testdebug1",
1608	"plla_core",
1609	"pllc_core0",
1610	"plld_core",
1611	"pllh_aux",
1612	"pllc_core1",
1613	"pllc_core2",
1614};
1615
1616#define REGISTER_VPU_CLK(s, ...)	REGISTER_CLK(			\
1617	s,								\
1618	.num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),	\
1619	.parents = bcm2835_clock_vpu_parents,				\
1620	__VA_ARGS__)
1621
1622/*
1623 * DSI parent clocks.  The DSI byte/DDR/DDR2 clocks come from the DSI
1624 * analog PHY.  The _inv variants are generated internally to cprman,
1625 * but we don't use them so they aren't hooked up.
1626 */
1627static const char *const bcm2835_clock_dsi0_parents[] = {
1628	"gnd",
1629	"xosc",
1630	"testdebug0",
1631	"testdebug1",
1632	"dsi0_ddr",
1633	"dsi0_ddr_inv",
1634	"dsi0_ddr2",
1635	"dsi0_ddr2_inv",
1636	"dsi0_byte",
1637	"dsi0_byte_inv",
1638};
1639
1640static const char *const bcm2835_clock_dsi1_parents[] = {
1641	"gnd",
1642	"xosc",
1643	"testdebug0",
1644	"testdebug1",
1645	"dsi1_ddr",
1646	"dsi1_ddr_inv",
1647	"dsi1_ddr2",
1648	"dsi1_ddr2_inv",
1649	"dsi1_byte",
1650	"dsi1_byte_inv",
1651};
1652
1653#define REGISTER_DSI0_CLK(s, ...)	REGISTER_CLK(			\
1654	s,								\
1655	.num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents),	\
1656	.parents = bcm2835_clock_dsi0_parents,				\
1657	__VA_ARGS__)
1658
1659#define REGISTER_DSI1_CLK(s, ...)	REGISTER_CLK(			\
1660	s,								\
1661	.num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents),	\
1662	.parents = bcm2835_clock_dsi1_parents,				\
1663	__VA_ARGS__)
1664
1665/*
1666 * the real definition of all the pll, pll_dividers and clocks
1667 * these make use of the above REGISTER_* macros
1668 */
1669static const struct bcm2835_clk_desc clk_desc_array[] = {
1670	/* the PLL + PLL dividers */
1671
1672	/*
1673	 * PLLA is the auxiliary PLL, used to drive the CCP2
1674	 * (Compact Camera Port 2) transmitter clock.
1675	 *
1676	 * It is in the PX LDO power domain, which is on when the
1677	 * AUDIO domain is on.
1678	 */
1679	[BCM2835_PLLA]		= REGISTER_PLL(
1680		SOC_ALL,
1681		.name = "plla",
1682		.cm_ctrl_reg = CM_PLLA,
1683		.a2w_ctrl_reg = A2W_PLLA_CTRL,
1684		.frac_reg = A2W_PLLA_FRAC,
1685		.ana_reg_base = A2W_PLLA_ANA0,
1686		.reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
1687		.lock_mask = CM_LOCK_FLOCKA,
1688
1689		.ana = &bcm2835_ana_default,
1690
1691		.min_rate = 600000000u,
1692		.max_rate = 2400000000u,
1693		.max_fb_rate = BCM2835_MAX_FB_RATE),
1694	[BCM2835_PLLA_CORE]	= REGISTER_PLL_DIV(
1695		SOC_ALL,
1696		.name = "plla_core",
1697		.source_pll = "plla",
1698		.cm_reg = CM_PLLA,
1699		.a2w_reg = A2W_PLLA_CORE,
1700		.load_mask = CM_PLLA_LOADCORE,
1701		.hold_mask = CM_PLLA_HOLDCORE,
1702		.fixed_divider = 1,
1703		.flags = CLK_SET_RATE_PARENT),
1704	[BCM2835_PLLA_PER]	= REGISTER_PLL_DIV(
1705		SOC_ALL,
1706		.name = "plla_per",
1707		.source_pll = "plla",
1708		.cm_reg = CM_PLLA,
1709		.a2w_reg = A2W_PLLA_PER,
1710		.load_mask = CM_PLLA_LOADPER,
1711		.hold_mask = CM_PLLA_HOLDPER,
1712		.fixed_divider = 1,
1713		.flags = CLK_SET_RATE_PARENT),
1714	[BCM2835_PLLA_DSI0]	= REGISTER_PLL_DIV(
1715		SOC_ALL,
1716		.name = "plla_dsi0",
1717		.source_pll = "plla",
1718		.cm_reg = CM_PLLA,
1719		.a2w_reg = A2W_PLLA_DSI0,
1720		.load_mask = CM_PLLA_LOADDSI0,
1721		.hold_mask = CM_PLLA_HOLDDSI0,
1722		.fixed_divider = 1),
1723	[BCM2835_PLLA_CCP2]	= REGISTER_PLL_DIV(
1724		SOC_ALL,
1725		.name = "plla_ccp2",
1726		.source_pll = "plla",
1727		.cm_reg = CM_PLLA,
1728		.a2w_reg = A2W_PLLA_CCP2,
1729		.load_mask = CM_PLLA_LOADCCP2,
1730		.hold_mask = CM_PLLA_HOLDCCP2,
1731		.fixed_divider = 1,
1732		.flags = CLK_SET_RATE_PARENT),
1733
1734	/* PLLB is used for the ARM's clock. */
1735	[BCM2835_PLLB]		= REGISTER_PLL(
1736		SOC_ALL,
1737		.name = "pllb",
1738		.cm_ctrl_reg = CM_PLLB,
1739		.a2w_ctrl_reg = A2W_PLLB_CTRL,
1740		.frac_reg = A2W_PLLB_FRAC,
1741		.ana_reg_base = A2W_PLLB_ANA0,
1742		.reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
1743		.lock_mask = CM_LOCK_FLOCKB,
1744
1745		.ana = &bcm2835_ana_default,
1746
1747		.min_rate = 600000000u,
1748		.max_rate = 3000000000u,
1749		.max_fb_rate = BCM2835_MAX_FB_RATE,
1750		.flags = CLK_GET_RATE_NOCACHE),
1751	[BCM2835_PLLB_ARM]	= REGISTER_PLL_DIV(
1752		SOC_ALL,
1753		.name = "pllb_arm",
1754		.source_pll = "pllb",
1755		.cm_reg = CM_PLLB,
1756		.a2w_reg = A2W_PLLB_ARM,
1757		.load_mask = CM_PLLB_LOADARM,
1758		.hold_mask = CM_PLLB_HOLDARM,
1759		.fixed_divider = 1,
1760		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE),
1761
1762	/*
1763	 * PLLC is the core PLL, used to drive the core VPU clock.
1764	 *
1765	 * It is in the PX LDO power domain, which is on when the
1766	 * AUDIO domain is on.
1767	 */
1768	[BCM2835_PLLC]		= REGISTER_PLL(
1769		SOC_ALL,
1770		.name = "pllc",
1771		.cm_ctrl_reg = CM_PLLC,
1772		.a2w_ctrl_reg = A2W_PLLC_CTRL,
1773		.frac_reg = A2W_PLLC_FRAC,
1774		.ana_reg_base = A2W_PLLC_ANA0,
1775		.reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1776		.lock_mask = CM_LOCK_FLOCKC,
1777
1778		.ana = &bcm2835_ana_default,
1779
1780		.min_rate = 600000000u,
1781		.max_rate = 3000000000u,
1782		.max_fb_rate = BCM2835_MAX_FB_RATE),
1783	[BCM2835_PLLC_CORE0]	= REGISTER_PLL_DIV(
1784		SOC_ALL,
1785		.name = "pllc_core0",
1786		.source_pll = "pllc",
1787		.cm_reg = CM_PLLC,
1788		.a2w_reg = A2W_PLLC_CORE0,
1789		.load_mask = CM_PLLC_LOADCORE0,
1790		.hold_mask = CM_PLLC_HOLDCORE0,
1791		.fixed_divider = 1,
1792		.flags = CLK_SET_RATE_PARENT),
1793	[BCM2835_PLLC_CORE1]	= REGISTER_PLL_DIV(
1794		SOC_ALL,
1795		.name = "pllc_core1",
1796		.source_pll = "pllc",
1797		.cm_reg = CM_PLLC,
1798		.a2w_reg = A2W_PLLC_CORE1,
1799		.load_mask = CM_PLLC_LOADCORE1,
1800		.hold_mask = CM_PLLC_HOLDCORE1,
1801		.fixed_divider = 1,
1802		.flags = CLK_SET_RATE_PARENT),
1803	[BCM2835_PLLC_CORE2]	= REGISTER_PLL_DIV(
1804		SOC_ALL,
1805		.name = "pllc_core2",
1806		.source_pll = "pllc",
1807		.cm_reg = CM_PLLC,
1808		.a2w_reg = A2W_PLLC_CORE2,
1809		.load_mask = CM_PLLC_LOADCORE2,
1810		.hold_mask = CM_PLLC_HOLDCORE2,
1811		.fixed_divider = 1,
1812		.flags = CLK_SET_RATE_PARENT),
1813	[BCM2835_PLLC_PER]	= REGISTER_PLL_DIV(
1814		SOC_ALL,
1815		.name = "pllc_per",
1816		.source_pll = "pllc",
1817		.cm_reg = CM_PLLC,
1818		.a2w_reg = A2W_PLLC_PER,
1819		.load_mask = CM_PLLC_LOADPER,
1820		.hold_mask = CM_PLLC_HOLDPER,
1821		.fixed_divider = 1,
1822		.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1823
1824	/*
1825	 * PLLD is the display PLL, used to drive DSI display panels.
1826	 *
1827	 * It is in the PX LDO power domain, which is on when the
1828	 * AUDIO domain is on.
1829	 */
1830	[BCM2835_PLLD]		= REGISTER_PLL(
1831		SOC_ALL,
1832		.name = "plld",
1833		.cm_ctrl_reg = CM_PLLD,
1834		.a2w_ctrl_reg = A2W_PLLD_CTRL,
1835		.frac_reg = A2W_PLLD_FRAC,
1836		.ana_reg_base = A2W_PLLD_ANA0,
1837		.reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
1838		.lock_mask = CM_LOCK_FLOCKD,
1839
1840		.ana = &bcm2835_ana_default,
1841
1842		.min_rate = 600000000u,
1843		.max_rate = 2400000000u,
1844		.max_fb_rate = BCM2835_MAX_FB_RATE),
1845	[BCM2835_PLLD_CORE]	= REGISTER_PLL_DIV(
1846		SOC_ALL,
1847		.name = "plld_core",
1848		.source_pll = "plld",
1849		.cm_reg = CM_PLLD,
1850		.a2w_reg = A2W_PLLD_CORE,
1851		.load_mask = CM_PLLD_LOADCORE,
1852		.hold_mask = CM_PLLD_HOLDCORE,
1853		.fixed_divider = 1,
1854		.flags = CLK_SET_RATE_PARENT),
1855	/*
1856	 * VPU firmware assumes that PLLD_PER isn't disabled by the ARM core.
1857	 * Otherwise this could cause firmware lookups. That's why we mark
1858	 * it as critical.
1859	 */
1860	[BCM2835_PLLD_PER]	= REGISTER_PLL_DIV(
1861		SOC_ALL,
1862		.name = "plld_per",
1863		.source_pll = "plld",
1864		.cm_reg = CM_PLLD,
1865		.a2w_reg = A2W_PLLD_PER,
1866		.load_mask = CM_PLLD_LOADPER,
1867		.hold_mask = CM_PLLD_HOLDPER,
1868		.fixed_divider = 1,
1869		.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1870	[BCM2835_PLLD_DSI0]	= REGISTER_PLL_DIV(
1871		SOC_ALL,
1872		.name = "plld_dsi0",
1873		.source_pll = "plld",
1874		.cm_reg = CM_PLLD,
1875		.a2w_reg = A2W_PLLD_DSI0,
1876		.load_mask = CM_PLLD_LOADDSI0,
1877		.hold_mask = CM_PLLD_HOLDDSI0,
1878		.fixed_divider = 1),
1879	[BCM2835_PLLD_DSI1]	= REGISTER_PLL_DIV(
1880		SOC_ALL,
1881		.name = "plld_dsi1",
1882		.source_pll = "plld",
1883		.cm_reg = CM_PLLD,
1884		.a2w_reg = A2W_PLLD_DSI1,
1885		.load_mask = CM_PLLD_LOADDSI1,
1886		.hold_mask = CM_PLLD_HOLDDSI1,
1887		.fixed_divider = 1),
1888
1889	/*
1890	 * PLLH is used to supply the pixel clock or the AUX clock for the
1891	 * TV encoder.
1892	 *
1893	 * It is in the HDMI power domain.
1894	 */
1895	[BCM2835_PLLH]		= REGISTER_PLL(
1896		SOC_BCM2835,
1897		"pllh",
1898		.cm_ctrl_reg = CM_PLLH,
1899		.a2w_ctrl_reg = A2W_PLLH_CTRL,
1900		.frac_reg = A2W_PLLH_FRAC,
1901		.ana_reg_base = A2W_PLLH_ANA0,
1902		.reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1903		.lock_mask = CM_LOCK_FLOCKH,
1904
1905		.ana = &bcm2835_ana_pllh,
1906
1907		.min_rate = 600000000u,
1908		.max_rate = 3000000000u,
1909		.max_fb_rate = BCM2835_MAX_FB_RATE),
1910	[BCM2835_PLLH_RCAL]	= REGISTER_PLL_DIV(
1911		SOC_BCM2835,
1912		.name = "pllh_rcal",
1913		.source_pll = "pllh",
1914		.cm_reg = CM_PLLH,
1915		.a2w_reg = A2W_PLLH_RCAL,
1916		.load_mask = CM_PLLH_LOADRCAL,
1917		.hold_mask = 0,
1918		.fixed_divider = 10,
1919		.flags = CLK_SET_RATE_PARENT),
1920	[BCM2835_PLLH_AUX]	= REGISTER_PLL_DIV(
1921		SOC_BCM2835,
1922		.name = "pllh_aux",
1923		.source_pll = "pllh",
1924		.cm_reg = CM_PLLH,
1925		.a2w_reg = A2W_PLLH_AUX,
1926		.load_mask = CM_PLLH_LOADAUX,
1927		.hold_mask = 0,
1928		.fixed_divider = 1,
1929		.flags = CLK_SET_RATE_PARENT),
1930	[BCM2835_PLLH_PIX]	= REGISTER_PLL_DIV(
1931		SOC_BCM2835,
1932		.name = "pllh_pix",
1933		.source_pll = "pllh",
1934		.cm_reg = CM_PLLH,
1935		.a2w_reg = A2W_PLLH_PIX,
1936		.load_mask = CM_PLLH_LOADPIX,
1937		.hold_mask = 0,
1938		.fixed_divider = 10,
1939		.flags = CLK_SET_RATE_PARENT),
1940
1941	/* the clocks */
1942
1943	/* clocks with oscillator parent mux */
1944
1945	/* One Time Programmable Memory clock.  Maximum 10Mhz. */
1946	[BCM2835_CLOCK_OTP]	= REGISTER_OSC_CLK(
1947		SOC_ALL,
1948		.name = "otp",
1949		.ctl_reg = CM_OTPCTL,
1950		.div_reg = CM_OTPDIV,
1951		.int_bits = 4,
1952		.frac_bits = 0,
1953		.tcnt_mux = 6),
1954	/*
1955	 * Used for a 1Mhz clock for the system clocksource, and also used
1956	 * bythe watchdog timer and the camera pulse generator.
1957	 */
1958	[BCM2835_CLOCK_TIMER]	= REGISTER_OSC_CLK(
1959		SOC_ALL,
1960		.name = "timer",
1961		.ctl_reg = CM_TIMERCTL,
1962		.div_reg = CM_TIMERDIV,
1963		.int_bits = 6,
1964		.frac_bits = 12),
1965	/*
1966	 * Clock for the temperature sensor.
1967	 * Generally run at 2Mhz, max 5Mhz.
1968	 */
1969	[BCM2835_CLOCK_TSENS]	= REGISTER_OSC_CLK(
1970		SOC_ALL,
1971		.name = "tsens",
1972		.ctl_reg = CM_TSENSCTL,
1973		.div_reg = CM_TSENSDIV,
1974		.int_bits = 5,
1975		.frac_bits = 0),
1976	[BCM2835_CLOCK_TEC]	= REGISTER_OSC_CLK(
1977		SOC_ALL,
1978		.name = "tec",
1979		.ctl_reg = CM_TECCTL,
1980		.div_reg = CM_TECDIV,
1981		.int_bits = 6,
1982		.frac_bits = 0),
1983
1984	/* clocks with vpu parent mux */
1985	[BCM2835_CLOCK_H264]	= REGISTER_VPU_CLK(
1986		SOC_ALL,
1987		.name = "h264",
1988		.ctl_reg = CM_H264CTL,
1989		.div_reg = CM_H264DIV,
1990		.int_bits = 4,
1991		.frac_bits = 8,
1992		.tcnt_mux = 1),
1993	[BCM2835_CLOCK_ISP]	= REGISTER_VPU_CLK(
1994		SOC_ALL,
1995		.name = "isp",
1996		.ctl_reg = CM_ISPCTL,
1997		.div_reg = CM_ISPDIV,
1998		.int_bits = 4,
1999		.frac_bits = 8,
2000		.tcnt_mux = 2),
2001
2002	/*
2003	 * Secondary SDRAM clock.  Used for low-voltage modes when the PLL
2004	 * in the SDRAM controller can't be used.
2005	 */
2006	[BCM2835_CLOCK_SDRAM]	= REGISTER_VPU_CLK(
2007		SOC_ALL,
2008		.name = "sdram",
2009		.ctl_reg = CM_SDCCTL,
2010		.div_reg = CM_SDCDIV,
2011		.int_bits = 6,
2012		.frac_bits = 0,
2013		.tcnt_mux = 3),
2014	[BCM2835_CLOCK_V3D]	= REGISTER_VPU_CLK(
2015		SOC_ALL,
2016		.name = "v3d",
2017		.ctl_reg = CM_V3DCTL,
2018		.div_reg = CM_V3DDIV,
2019		.int_bits = 4,
2020		.frac_bits = 8,
2021		.tcnt_mux = 4),
2022	/*
2023	 * VPU clock.  This doesn't have an enable bit, since it drives
2024	 * the bus for everything else, and is special so it doesn't need
2025	 * to be gated for rate changes.  It is also known as "clk_audio"
2026	 * in various hardware documentation.
2027	 */
2028	[BCM2835_CLOCK_VPU]	= REGISTER_VPU_CLK(
2029		SOC_ALL,
2030		.name = "vpu",
2031		.ctl_reg = CM_VPUCTL,
2032		.div_reg = CM_VPUDIV,
2033		.int_bits = 12,
2034		.frac_bits = 8,
2035		.flags = CLK_IS_CRITICAL,
2036		.is_vpu_clock = true,
2037		.tcnt_mux = 5),
2038
2039	/* clocks with per parent mux */
2040	[BCM2835_CLOCK_AVEO]	= REGISTER_PER_CLK(
2041		SOC_ALL,
2042		.name = "aveo",
2043		.ctl_reg = CM_AVEOCTL,
2044		.div_reg = CM_AVEODIV,
2045		.int_bits = 4,
2046		.frac_bits = 0,
2047		.tcnt_mux = 38),
2048	[BCM2835_CLOCK_CAM0]	= REGISTER_PER_CLK(
2049		SOC_ALL,
2050		.name = "cam0",
2051		.ctl_reg = CM_CAM0CTL,
2052		.div_reg = CM_CAM0DIV,
2053		.int_bits = 4,
2054		.frac_bits = 8,
2055		.tcnt_mux = 14),
2056	[BCM2835_CLOCK_CAM1]	= REGISTER_PER_CLK(
2057		SOC_ALL,
2058		.name = "cam1",
2059		.ctl_reg = CM_CAM1CTL,
2060		.div_reg = CM_CAM1DIV,
2061		.int_bits = 4,
2062		.frac_bits = 8,
2063		.tcnt_mux = 15),
2064	[BCM2835_CLOCK_DFT]	= REGISTER_PER_CLK(
2065		SOC_ALL,
2066		.name = "dft",
2067		.ctl_reg = CM_DFTCTL,
2068		.div_reg = CM_DFTDIV,
2069		.int_bits = 5,
2070		.frac_bits = 0),
2071	[BCM2835_CLOCK_DPI]	= REGISTER_PER_CLK(
2072		SOC_ALL,
2073		.name = "dpi",
2074		.ctl_reg = CM_DPICTL,
2075		.div_reg = CM_DPIDIV,
2076		.int_bits = 4,
2077		.frac_bits = 8,
2078		.tcnt_mux = 17),
2079
2080	/* Arasan EMMC clock */
2081	[BCM2835_CLOCK_EMMC]	= REGISTER_PER_CLK(
2082		SOC_ALL,
2083		.name = "emmc",
2084		.ctl_reg = CM_EMMCCTL,
2085		.div_reg = CM_EMMCDIV,
2086		.int_bits = 4,
2087		.frac_bits = 8,
2088		.tcnt_mux = 39),
2089
2090	/* EMMC2 clock (only available for BCM2711) */
2091	[BCM2711_CLOCK_EMMC2]	= REGISTER_PER_CLK(
2092		SOC_BCM2711,
2093		.name = "emmc2",
2094		.ctl_reg = CM_EMMC2CTL,
2095		.div_reg = CM_EMMC2DIV,
2096		.int_bits = 4,
2097		.frac_bits = 8,
2098		.tcnt_mux = 42),
2099
2100	/* General purpose (GPIO) clocks */
2101	[BCM2835_CLOCK_GP0]	= REGISTER_PER_CLK(
2102		SOC_ALL,
2103		.name = "gp0",
2104		.ctl_reg = CM_GP0CTL,
2105		.div_reg = CM_GP0DIV,
2106		.int_bits = 12,
2107		.frac_bits = 12,
2108		.is_mash_clock = true,
2109		.tcnt_mux = 20),
2110	[BCM2835_CLOCK_GP1]	= REGISTER_PER_CLK(
2111		SOC_ALL,
2112		.name = "gp1",
2113		.ctl_reg = CM_GP1CTL,
2114		.div_reg = CM_GP1DIV,
2115		.int_bits = 12,
2116		.frac_bits = 12,
2117		.flags = CLK_IS_CRITICAL,
2118		.is_mash_clock = true,
2119		.tcnt_mux = 21),
2120	[BCM2835_CLOCK_GP2]	= REGISTER_PER_CLK(
2121		SOC_ALL,
2122		.name = "gp2",
2123		.ctl_reg = CM_GP2CTL,
2124		.div_reg = CM_GP2DIV,
2125		.int_bits = 12,
2126		.frac_bits = 12,
2127		.flags = CLK_IS_CRITICAL),
2128
2129	/* HDMI state machine */
2130	[BCM2835_CLOCK_HSM]	= REGISTER_PER_CLK(
2131		SOC_ALL,
2132		.name = "hsm",
2133		.ctl_reg = CM_HSMCTL,
2134		.div_reg = CM_HSMDIV,
2135		.int_bits = 4,
2136		.frac_bits = 8,
2137		.tcnt_mux = 22),
2138	[BCM2835_CLOCK_PCM]	= REGISTER_PCM_CLK(
2139		SOC_ALL,
2140		.name = "pcm",
2141		.ctl_reg = CM_PCMCTL,
2142		.div_reg = CM_PCMDIV,
2143		.int_bits = 12,
2144		.frac_bits = 12,
2145		.is_mash_clock = true,
2146		.low_jitter = true,
2147		.tcnt_mux = 23),
2148	[BCM2835_CLOCK_PWM]	= REGISTER_PER_CLK(
2149		SOC_ALL,
2150		.name = "pwm",
2151		.ctl_reg = CM_PWMCTL,
2152		.div_reg = CM_PWMDIV,
2153		.int_bits = 12,
2154		.frac_bits = 12,
2155		.is_mash_clock = true,
2156		.tcnt_mux = 24),
2157	[BCM2835_CLOCK_SLIM]	= REGISTER_PER_CLK(
2158		SOC_ALL,
2159		.name = "slim",
2160		.ctl_reg = CM_SLIMCTL,
2161		.div_reg = CM_SLIMDIV,
2162		.int_bits = 12,
2163		.frac_bits = 12,
2164		.is_mash_clock = true,
2165		.tcnt_mux = 25),
2166	[BCM2835_CLOCK_SMI]	= REGISTER_PER_CLK(
2167		SOC_ALL,
2168		.name = "smi",
2169		.ctl_reg = CM_SMICTL,
2170		.div_reg = CM_SMIDIV,
2171		.int_bits = 4,
2172		.frac_bits = 8,
2173		.tcnt_mux = 27),
2174	[BCM2835_CLOCK_UART]	= REGISTER_PER_CLK(
2175		SOC_ALL,
2176		.name = "uart",
2177		.ctl_reg = CM_UARTCTL,
2178		.div_reg = CM_UARTDIV,
2179		.int_bits = 10,
2180		.frac_bits = 12,
2181		.tcnt_mux = 28,
2182		.round_up = true),
2183
2184	/* TV encoder clock.  Only operating frequency is 108Mhz.  */
2185	[BCM2835_CLOCK_VEC]	= REGISTER_PER_CLK(
2186		SOC_ALL,
2187		.name = "vec",
2188		.ctl_reg = CM_VECCTL,
2189		.div_reg = CM_VECDIV,
2190		.int_bits = 4,
2191		.frac_bits = 0,
2192		/*
2193		 * Allow rate change propagation only on PLLH_AUX which is
2194		 * assigned index 7 in the parent array.
2195		 */
2196		.set_rate_parent = BIT(7),
2197		.tcnt_mux = 29),
2198
2199	/* dsi clocks */
2200	[BCM2835_CLOCK_DSI0E]	= REGISTER_PER_CLK(
2201		SOC_ALL,
2202		.name = "dsi0e",
2203		.ctl_reg = CM_DSI0ECTL,
2204		.div_reg = CM_DSI0EDIV,
2205		.int_bits = 4,
2206		.frac_bits = 8,
2207		.tcnt_mux = 18),
2208	[BCM2835_CLOCK_DSI1E]	= REGISTER_PER_CLK(
2209		SOC_ALL,
2210		.name = "dsi1e",
2211		.ctl_reg = CM_DSI1ECTL,
2212		.div_reg = CM_DSI1EDIV,
2213		.int_bits = 4,
2214		.frac_bits = 8,
2215		.tcnt_mux = 19),
2216	[BCM2835_CLOCK_DSI0P]	= REGISTER_DSI0_CLK(
2217		SOC_ALL,
2218		.name = "dsi0p",
2219		.ctl_reg = CM_DSI0PCTL,
2220		.div_reg = CM_DSI0PDIV,
2221		.int_bits = 0,
2222		.frac_bits = 0,
2223		.tcnt_mux = 12),
2224	[BCM2835_CLOCK_DSI1P]	= REGISTER_DSI1_CLK(
2225		SOC_ALL,
2226		.name = "dsi1p",
2227		.ctl_reg = CM_DSI1PCTL,
2228		.div_reg = CM_DSI1PDIV,
2229		.int_bits = 0,
2230		.frac_bits = 0,
2231		.tcnt_mux = 13),
2232
2233	/* the gates */
2234
2235	/*
2236	 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
2237	 * you have the debug bit set in the power manager, which we
2238	 * don't bother exposing) are individual gates off of the
2239	 * non-stop vpu clock.
2240	 */
2241	[BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
2242		SOC_ALL,
2243		.name = "peri_image",
2244		.parent = "vpu",
2245		.ctl_reg = CM_PERIICTL),
2246};
2247
2248/*
2249 * Permanently take a reference on the parent of the SDRAM clock.
2250 *
2251 * While the SDRAM is being driven by its dedicated PLL most of the
2252 * time, there is a little loop running in the firmware that
2253 * periodically switches the SDRAM to using our CM clock to do PVT
2254 * recalibration, with the assumption that the previously configured
2255 * SDRAM parent is still enabled and running.
2256 */
2257static int bcm2835_mark_sdc_parent_critical(struct clk *sdc)
2258{
2259	struct clk *parent = clk_get_parent(sdc);
2260
2261	if (IS_ERR(parent))
2262		return PTR_ERR(parent);
2263
2264	return clk_prepare_enable(parent);
2265}
2266
2267static int bcm2835_clk_probe(struct platform_device *pdev)
2268{
2269	struct device *dev = &pdev->dev;
2270	struct clk_hw **hws;
2271	struct bcm2835_cprman *cprman;
2272	const struct bcm2835_clk_desc *desc;
2273	const size_t asize = ARRAY_SIZE(clk_desc_array);
2274	const struct cprman_plat_data *pdata;
2275	size_t i;
2276	int ret;
2277
2278	pdata = of_device_get_match_data(&pdev->dev);
2279	if (!pdata)
2280		return -ENODEV;
2281
2282	cprman = devm_kzalloc(dev,
2283			      struct_size(cprman, onecell.hws, asize),
2284			      GFP_KERNEL);
2285	if (!cprman)
2286		return -ENOMEM;
2287
2288	spin_lock_init(&cprman->regs_lock);
2289	cprman->dev = dev;
2290	cprman->regs = devm_platform_ioremap_resource(pdev, 0);
2291	if (IS_ERR(cprman->regs))
2292		return PTR_ERR(cprman->regs);
2293
2294	memcpy(cprman->real_parent_names, cprman_parent_names,
2295	       sizeof(cprman_parent_names));
2296	of_clk_parent_fill(dev->of_node, cprman->real_parent_names,
2297			   ARRAY_SIZE(cprman_parent_names));
2298
2299	/*
2300	 * Make sure the external oscillator has been registered.
2301	 *
2302	 * The other (DSI) clocks are not present on older device
2303	 * trees, which we still need to support for backwards
2304	 * compatibility.
2305	 */
2306	if (!cprman->real_parent_names[0])
2307		return -ENODEV;
2308
2309	platform_set_drvdata(pdev, cprman);
2310
2311	cprman->onecell.num = asize;
2312	cprman->soc = pdata->soc;
2313	hws = cprman->onecell.hws;
2314
2315	for (i = 0; i < asize; i++) {
2316		desc = &clk_desc_array[i];
2317		if (desc->clk_register && desc->data &&
2318		    (desc->supported & pdata->soc)) {
2319			hws[i] = desc->clk_register(cprman, desc->data);
2320		}
2321	}
2322
2323	ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
2324	if (ret)
2325		return ret;
2326
2327	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
2328				      &cprman->onecell);
2329}
2330
2331static const struct cprman_plat_data cprman_bcm2835_plat_data = {
2332	.soc = SOC_BCM2835,
2333};
2334
2335static const struct cprman_plat_data cprman_bcm2711_plat_data = {
2336	.soc = SOC_BCM2711,
2337};
2338
2339static const struct of_device_id bcm2835_clk_of_match[] = {
2340	{ .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
2341	{ .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
2342	{}
2343};
2344MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
2345
2346static struct platform_driver bcm2835_clk_driver = {
2347	.driver = {
2348		.name = "bcm2835-clk",
2349		.of_match_table = bcm2835_clk_of_match,
2350	},
2351	.probe          = bcm2835_clk_probe,
2352};
2353
2354builtin_platform_driver(bcm2835_clk_driver);
2355
2356MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
2357MODULE_DESCRIPTION("BCM2835 clock driver");