pmc.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * drivers/clk/at91/pmc.h
  4 *
  5 *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
  6 */
  7
  8#ifndef __PMC_H_
  9#define __PMC_H_
 10
 11#include <linux/io.h>
 12#include <linux/irqdomain.h>
 13#include <linux/regmap.h>
 14#include <linux/spinlock.h>
 15
 16#include <dt-bindings/clock/at91.h>
 17
 18extern spinlock_t pmc_pcr_lock;
 19
 20struct pmc_data {
 21	unsigned int ncore;
 22	struct clk_hw **chws;
 23	unsigned int nsystem;
 24	struct clk_hw **shws;
 25	unsigned int nperiph;
 26	struct clk_hw **phws;
 27	unsigned int ngck;
 28	struct clk_hw **ghws;
 29	unsigned int npck;
 30	struct clk_hw **pchws;
 31
 32	struct clk_hw *hwtable[];
 33};
 34
 35struct clk_range {
 36	unsigned long min;
 37	unsigned long max;
 38};
 39
 40#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
 41
 42struct clk_master_layout {
 43	u32 offset;
 44	u32 mask;
 45	u8 pres_shift;
 46};
 47
 48extern const struct clk_master_layout at91rm9200_master_layout;
 49extern const struct clk_master_layout at91sam9x5_master_layout;
 50
 51struct clk_master_characteristics {
 52	struct clk_range output;
 53	u32 divisors[5];
 54	u8 have_div3_pres;
 55};
 56
 57struct clk_pll_layout {
 58	u32 pllr_mask;
 59	u32 mul_mask;
 60	u32 frac_mask;
 61	u32 div_mask;
 62	u32 endiv_mask;
 63	u8 mul_shift;
 64	u8 frac_shift;
 65	u8 div_shift;
 66	u8 endiv_shift;
 67	u8 div2;
 68};
 69
 70extern const struct clk_pll_layout at91rm9200_pll_layout;
 71extern const struct clk_pll_layout at91sam9g45_pll_layout;
 72extern const struct clk_pll_layout at91sam9g20_pllb_layout;
 73extern const struct clk_pll_layout sama5d3_pll_layout;
 74
 75struct clk_pll_characteristics {
 76	struct clk_range input;
 77	int num_output;
 78	const struct clk_range *output;
 79	const struct clk_range *core_output;
 80	u16 *icpll;
 81	u8 *out;
 82	u8 upll : 1;
 83	u32 acr;
 84};
 85
 86struct clk_programmable_layout {
 87	u8 pres_mask;
 88	u8 pres_shift;
 89	u8 css_mask;
 90	u8 have_slck_mck;
 91	u8 is_pres_direct;
 92};
 93
 94extern const struct clk_programmable_layout at91rm9200_programmable_layout;
 95extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
 96extern const struct clk_programmable_layout at91sam9x5_programmable_layout;
 97
 98struct clk_pcr_layout {
 99	u32 offset;
100	u32 cmd;
101	u32 div_mask;
102	u32 gckcss_mask;
103	u32 pid_mask;
104};
105
106/**
107 * struct at91_clk_pms - Power management state for AT91 clock
108 * @rate: clock rate
109 * @parent_rate: clock parent rate
110 * @status: clock status (enabled or disabled)
111 * @parent: clock parent index
112 */
113struct at91_clk_pms {
114	unsigned long rate;
115	unsigned long parent_rate;
116	unsigned int status;
117	unsigned int parent;
118};
119
120#define ndck(a, s) (a[s - 1].id + 1)
121#define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1)
122
123#define PMC_INIT_TABLE(_table, _count)			\
124	do {						\
125		u8 _i;					\
126		for (_i = 0; _i < (_count); _i++)	\
127			(_table)[_i] = _i;		\
128	} while (0)
129
130#define PMC_FILL_TABLE(_to, _from, _count)		\
131	do {						\
132		u8 _i;					\
133		for (_i = 0; _i < (_count); _i++) {	\
134			(_to)[_i] = (_from)[_i];	\
135		}					\
136	} while (0)
137
138struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
139				   unsigned int nperiph, unsigned int ngck,
140				   unsigned int npck);
141
142int of_at91_get_clk_range(struct device_node *np, const char *propname,
143			  struct clk_range *range);
144
145struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data);
146
147struct clk_hw * __init
148at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,
149				 const char *parent_name);
150
151struct clk_hw * __init
152at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
153				const char *parent_name);
154
155struct clk_hw * __init
156at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
157				const char *parent_name);
158
159struct clk_hw * __init
160at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
161			    const struct clk_pcr_layout *layout,
162			    const char *name, const char **parent_names,
163			    struct clk_hw **parent_hws, u32 *mux_table,
164			    u8 num_parents, u8 id,
165			    const struct clk_range *range, int chg_pid);
166
167struct clk_hw * __init
168at91_clk_register_h32mx(struct regmap *regmap, const char *name,
169			const char *parent_name);
170
171struct clk_hw * __init
172at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
173			  const char * const *parent_names,
174			  unsigned int num_parents, u8 bus_id);
175
176struct clk_hw * __init
177at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name,
178			      u32 frequency, u32 accuracy);
179struct clk_hw * __init
180at91_clk_register_main_osc(struct regmap *regmap, const char *name,
181			   const char *parent_name,
182			   struct clk_parent_data *parent_data, bool bypass);
183struct clk_hw * __init
184at91_clk_register_rm9200_main(struct regmap *regmap,
185			      const char *name,
186			      const char *parent_name,
187			      struct clk_hw *parent_hw);
188struct clk_hw * __init
189at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name,
190			      const char **parent_names,
191			      struct clk_hw **parent_hws, int num_parents);
192
193struct clk_hw * __init
194at91_clk_register_master_pres(struct regmap *regmap, const char *name,
195			      int num_parents, const char **parent_names,
196			      struct clk_hw **parent_hws,
197			      const struct clk_master_layout *layout,
198			      const struct clk_master_characteristics *characteristics,
199			      spinlock_t *lock);
200
201struct clk_hw * __init
202at91_clk_register_master_div(struct regmap *regmap, const char *name,
203			     const char *parent_names, struct clk_hw *parent_hw,
204			     const struct clk_master_layout *layout,
205			     const struct clk_master_characteristics *characteristics,
206			     spinlock_t *lock, u32 flags, u32 safe_div);
207
208struct clk_hw * __init
209at91_clk_sama7g5_register_master(struct regmap *regmap,
210				 const char *name, int num_parents,
211				 const char **parent_names,
212				 struct clk_hw **parent_hws, u32 *mux_table,
213				 spinlock_t *lock, u8 id, bool critical,
214				 int chg_pid);
215
216struct clk_hw * __init
217at91_clk_register_peripheral(struct regmap *regmap, const char *name,
218			     const char *parent_name, struct clk_hw *parent_hw,
219			     u32 id);
220struct clk_hw * __init
221at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
222				    const struct clk_pcr_layout *layout,
223				    const char *name, const char *parent_name,
224				    struct clk_hw *parent_hw,
225				    u32 id, const struct clk_range *range,
226				    int chg_pid, unsigned long flags);
227
228struct clk_hw * __init
229at91_clk_register_pll(struct regmap *regmap, const char *name,
230		      const char *parent_name, u8 id,
231		      const struct clk_pll_layout *layout,
232		      const struct clk_pll_characteristics *characteristics);
233struct clk_hw * __init
234at91_clk_register_plldiv(struct regmap *regmap, const char *name,
235			 const char *parent_name);
236
237struct clk_hw * __init
238sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
239			     const char *name, const char *parent_name,
240			     struct clk_hw *parent_hw, u8 id,
241			     const struct clk_pll_characteristics *characteristics,
242			     const struct clk_pll_layout *layout, u32 flags,
243			     u32 safe_div);
244
245struct clk_hw * __init
246sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
247			      const char *name, const char *parent_name,
248			      struct clk_hw *parent_hw, u8 id,
249			      const struct clk_pll_characteristics *characteristics,
250			      const struct clk_pll_layout *layout, u32 flags);
251
252struct clk_hw * __init
253at91_clk_register_programmable(struct regmap *regmap, const char *name,
254			       const char **parent_names, struct clk_hw **parent_hws,
255			       u8 num_parents, u8 id,
256			       const struct clk_programmable_layout *layout,
257			       u32 *mux_table);
258
259struct clk_hw * __init
260at91_clk_register_sam9260_slow(struct regmap *regmap,
261			       const char *name,
262			       const char **parent_names,
263			       int num_parents);
264
265struct clk_hw * __init
266at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
267			    const char **parent_names, u8 num_parents);
268
269struct clk_hw * __init
270at91_clk_register_system(struct regmap *regmap, const char *name,
271			 const char *parent_name, struct clk_hw *parent_hw,
272			 u8 id, unsigned long flags);
273
274struct clk_hw * __init
275at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
276			    const char **parent_names, u8 num_parents);
277struct clk_hw * __init
278at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name,
279			     const char *parent_name);
280struct clk_hw * __init
281sam9x60_clk_register_usb(struct regmap *regmap, const char *name,
282			 const char **parent_names, u8 num_parents);
283struct clk_hw * __init
284at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,
285			    const char *parent_name, const u32 *divisors);
286
287struct clk_hw * __init
288at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
289		       const char *name, const char *parent_name,
290		       struct clk_hw *parent_hw);
291
292struct clk_hw * __init
293at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name,
294			       const char *parent_name, struct clk_hw *parent_hw);
295
296#endif /* __PMC_H_ */