tpm_tis_core.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2005, 2006 IBM Corporation
  4 * Copyright (C) 2014, 2015 Intel Corporation
  5 *
  6 * Authors:
  7 * Leendert van Doorn <leendert@watson.ibm.com>
  8 * Kylene Hall <kjhall@us.ibm.com>
  9 *
 10 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
 11 *
 12 * Device driver for TCG/TCPA TPM (trusted platform module).
 13 * Specifications at www.trustedcomputinggroup.org
 14 *
 15 * This device driver implements the TPM interface as defined in
 16 * the TCG TPM Interface Spec version 1.2, revision 1.0.
 17 */
 18
 19#ifndef __TPM_TIS_CORE_H__
 20#define __TPM_TIS_CORE_H__
 21
 22#include "tpm.h"
 23
 24enum tis_access {
 25	TPM_ACCESS_VALID = 0x80,
 26	TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
 27	TPM_ACCESS_REQUEST_PENDING = 0x04,
 28	TPM_ACCESS_REQUEST_USE = 0x02,
 29};
 30
 31enum tis_status {
 32	TPM_STS_VALID = 0x80,
 33	TPM_STS_COMMAND_READY = 0x40,
 34	TPM_STS_GO = 0x20,
 35	TPM_STS_DATA_AVAIL = 0x10,
 36	TPM_STS_DATA_EXPECT = 0x08,
 37	TPM_STS_RESPONSE_RETRY = 0x02,
 38	TPM_STS_READ_ZERO = 0x23, /* bits that must be zero on read */
 39};
 40
 41enum tis_int_flags {
 42	TPM_GLOBAL_INT_ENABLE = 0x80000000,
 43	TPM_INTF_BURST_COUNT_STATIC = 0x100,
 44	TPM_INTF_CMD_READY_INT = 0x080,
 45	TPM_INTF_INT_EDGE_FALLING = 0x040,
 46	TPM_INTF_INT_EDGE_RISING = 0x020,
 47	TPM_INTF_INT_LEVEL_LOW = 0x010,
 48	TPM_INTF_INT_LEVEL_HIGH = 0x008,
 49	TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
 50	TPM_INTF_STS_VALID_INT = 0x002,
 51	TPM_INTF_DATA_AVAIL_INT = 0x001,
 52};
 53
 54enum tis_defaults {
 55	TIS_MEM_LEN = 0x5000,
 56	TIS_SHORT_TIMEOUT = 750,	/* ms */
 57	TIS_LONG_TIMEOUT = 4000,	/* 4 secs */
 58	TIS_TIMEOUT_MIN_ATML = 14700,	/* usecs */
 59	TIS_TIMEOUT_MAX_ATML = 15000,	/* usecs */
 60};
 61
 62/* Some timeout values are needed before it is known whether the chip is
 63 * TPM 1.0 or TPM 2.0.
 64 */
 65#define TIS_TIMEOUT_A_MAX	max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A)
 66#define TIS_TIMEOUT_B_MAX	max_t(int, TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B)
 67#define TIS_TIMEOUT_C_MAX	max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C)
 68#define TIS_TIMEOUT_D_MAX	max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D)
 69
 70#define	TPM_ACCESS(l)			(0x0000 | ((l) << 12))
 71#define	TPM_INT_ENABLE(l)		(0x0008 | ((l) << 12))
 72#define	TPM_INT_VECTOR(l)		(0x000C | ((l) << 12))
 73#define	TPM_INT_STATUS(l)		(0x0010 | ((l) << 12))
 74#define	TPM_INTF_CAPS(l)		(0x0014 | ((l) << 12))
 75#define	TPM_STS(l)			(0x0018 | ((l) << 12))
 76#define	TPM_STS3(l)			(0x001b | ((l) << 12))
 77#define	TPM_DATA_FIFO(l)		(0x0024 | ((l) << 12))
 78
 79#define	TPM_DID_VID(l)			(0x0F00 | ((l) << 12))
 80#define	TPM_RID(l)			(0x0F04 | ((l) << 12))
 81
 82#define LPC_CNTRL_OFFSET		0x84
 83#define LPC_CLKRUN_EN			(1 << 2)
 84#define INTEL_LEGACY_BLK_BASE_ADDR	0xFED08000
 85#define ILB_REMAP_SIZE			0x100
 86
 87enum tpm_tis_flags {
 88	TPM_TIS_ITPM_WORKAROUND		= 0,
 89	TPM_TIS_INVALID_STATUS		= 1,
 90	TPM_TIS_DEFAULT_CANCELLATION	= 2,
 91	TPM_TIS_IRQ_TESTED		= 3,
 92	TPM_TIS_STATUS_VALID_RETRY	= 4,
 93};
 94
 95struct tpm_tis_data {
 96	struct tpm_chip *chip;
 97	u16 manufacturer_id;
 98	struct mutex locality_count_mutex;
 99	unsigned int locality_count;
100	int locality;
101	int irq;
102	struct work_struct free_irq_work;
103	unsigned long last_unhandled_irq;
104	unsigned int unhandled_irqs;
105	unsigned int int_mask;
106	unsigned long flags;
107	void __iomem *ilb_base_addr;
108	u16 clkrun_enabled;
109	wait_queue_head_t int_queue;
110	wait_queue_head_t read_queue;
111	const struct tpm_tis_phy_ops *phy_ops;
112	unsigned short rng_quality;
113	unsigned int timeout_min; /* usecs */
114	unsigned int timeout_max; /* usecs */
115};
116
117/*
118 * IO modes to indicate how many bytes should be read/written at once in the
119 * tpm_tis_phy_ops read_bytes/write_bytes calls. Use TPM_TIS_PHYS_8 to
120 * receive/transmit byte-wise, TPM_TIS_PHYS_16 for two bytes etc.
121 */
122enum tpm_tis_io_mode {
123	TPM_TIS_PHYS_8,
124	TPM_TIS_PHYS_16,
125	TPM_TIS_PHYS_32,
126};
127
128struct tpm_tis_phy_ops {
129	/* data is passed in little endian */
130	int (*read_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
131			  u8 *result, enum tpm_tis_io_mode mode);
132	int (*write_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
133			   const u8 *value, enum tpm_tis_io_mode mode);
134	int (*verify_crc)(struct tpm_tis_data *data, size_t len,
135			  const u8 *value);
136};
137
138static inline int tpm_tis_read_bytes(struct tpm_tis_data *data, u32 addr,
139				     u16 len, u8 *result)
140{
141	return data->phy_ops->read_bytes(data, addr, len, result,
142					 TPM_TIS_PHYS_8);
143}
144
145static inline int tpm_tis_read8(struct tpm_tis_data *data, u32 addr, u8 *result)
146{
147	return data->phy_ops->read_bytes(data, addr, 1, result, TPM_TIS_PHYS_8);
148}
149
150static inline int tpm_tis_read16(struct tpm_tis_data *data, u32 addr,
151				 u16 *result)
152{
153	__le16 result_le;
154	int rc;
155
156	rc = data->phy_ops->read_bytes(data, addr, sizeof(u16),
157				       (u8 *)&result_le, TPM_TIS_PHYS_16);
158	if (!rc)
159		*result = le16_to_cpu(result_le);
160
161	return rc;
162}
163
164static inline int tpm_tis_read32(struct tpm_tis_data *data, u32 addr,
165				 u32 *result)
166{
167	__le32 result_le;
168	int rc;
169
170	rc = data->phy_ops->read_bytes(data, addr, sizeof(u32),
171				       (u8 *)&result_le, TPM_TIS_PHYS_32);
172	if (!rc)
173		*result = le32_to_cpu(result_le);
174
175	return rc;
176}
177
178static inline int tpm_tis_write_bytes(struct tpm_tis_data *data, u32 addr,
179				      u16 len, const u8 *value)
180{
181	return data->phy_ops->write_bytes(data, addr, len, value,
182					  TPM_TIS_PHYS_8);
183}
184
185static inline int tpm_tis_write8(struct tpm_tis_data *data, u32 addr, u8 value)
186{
187	return data->phy_ops->write_bytes(data, addr, 1, &value,
188					  TPM_TIS_PHYS_8);
189}
190
191static inline int tpm_tis_write32(struct tpm_tis_data *data, u32 addr,
192				  u32 value)
193{
194	__le32 value_le;
195	int rc;
196
197	value_le = cpu_to_le32(value);
198	rc =  data->phy_ops->write_bytes(data, addr, sizeof(u32),
199					 (u8 *)&value_le, TPM_TIS_PHYS_32);
200	return rc;
201}
202
203static inline int tpm_tis_verify_crc(struct tpm_tis_data *data, size_t len,
204				     const u8 *value)
205{
206	if (!data->phy_ops->verify_crc)
207		return 0;
208	return data->phy_ops->verify_crc(data, len, value);
209}
210
211static inline bool is_bsw(void)
212{
213#ifdef CONFIG_X86
214	return (boot_cpu_data.x86_vfm == INTEL_ATOM_AIRMONT) ? 1 : 0;
215#else
216	return false;
217#endif
218}
219
220void tpm_tis_remove(struct tpm_chip *chip);
221int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
222		      const struct tpm_tis_phy_ops *phy_ops,
223		      acpi_handle acpi_dev_handle);
224
225#ifdef CONFIG_PM_SLEEP
226int tpm_tis_resume(struct device *dev);
227#endif
228
229#endif