tpm_nsc.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2004 IBM Corporation
  4 *
  5 * Authors:
  6 * Leendert van Doorn <leendert@watson.ibm.com>
  7 * Dave Safford <safford@watson.ibm.com>
  8 * Reiner Sailer <sailer@watson.ibm.com>
  9 * Kylene Hall <kjhall@us.ibm.com>
 10 *
 11 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
 12 *
 13 * Device driver for TCG/TCPA TPM (trusted platform module).
 14 * Specifications at www.trustedcomputinggroup.org	 
 15 */
 16
 17#include <linux/platform_device.h>
 18#include <linux/slab.h>
 19#include "tpm.h"
 20
 21/* National definitions */
 22enum tpm_nsc_addr{
 23	TPM_NSC_IRQ = 0x07,
 24	TPM_NSC_BASE0_HI = 0x60,
 25	TPM_NSC_BASE0_LO = 0x61,
 26	TPM_NSC_BASE1_HI = 0x62,
 27	TPM_NSC_BASE1_LO = 0x63
 28};
 29
 30enum tpm_nsc_index {
 31	NSC_LDN_INDEX = 0x07,
 32	NSC_SID_INDEX = 0x20,
 33	NSC_LDC_INDEX = 0x30,
 34	NSC_DIO_INDEX = 0x60,
 35	NSC_CIO_INDEX = 0x62,
 36	NSC_IRQ_INDEX = 0x70,
 37	NSC_ITS_INDEX = 0x71
 38};
 39
 40enum tpm_nsc_status_loc {
 41	NSC_STATUS = 0x01,
 42	NSC_COMMAND = 0x01,
 43	NSC_DATA = 0x00
 44};
 45
 46/* status bits */
 47enum tpm_nsc_status {
 48	NSC_STATUS_OBF = 0x01,	/* output buffer full */
 49	NSC_STATUS_IBF = 0x02,	/* input buffer full */
 50	NSC_STATUS_F0 = 0x04,	/* F0 */
 51	NSC_STATUS_A2 = 0x08,	/* A2 */
 52	NSC_STATUS_RDY = 0x10,	/* ready to receive command */
 53	NSC_STATUS_IBR = 0x20	/* ready to receive data */
 54};
 55
 56/* command bits */
 57enum tpm_nsc_cmd_mode {
 58	NSC_COMMAND_NORMAL = 0x01,	/* normal mode */
 59	NSC_COMMAND_EOC = 0x03,
 60	NSC_COMMAND_CANCEL = 0x22
 61};
 62
 63struct tpm_nsc_priv {
 64	unsigned long base;
 65};
 66
 67/*
 68 * Wait for a certain status to appear
 69 */
 70static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
 71{
 72	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
 73	unsigned long stop;
 74
 75	/* status immediately available check */
 76	*data = inb(priv->base + NSC_STATUS);
 77	if ((*data & mask) == val)
 78		return 0;
 79
 80	/* wait for status */
 81	stop = jiffies + 10 * HZ;
 82	do {
 83		msleep(TPM_TIMEOUT);
 84		*data = inb(priv->base + 1);
 85		if ((*data & mask) == val)
 86			return 0;
 87	}
 88	while (time_before(jiffies, stop));
 89
 90	return -EBUSY;
 91}
 92
 93static int nsc_wait_for_ready(struct tpm_chip *chip)
 94{
 95	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
 96	int status;
 97	unsigned long stop;
 98
 99	/* status immediately available check */
100	status = inb(priv->base + NSC_STATUS);
101	if (status & NSC_STATUS_OBF)
102		status = inb(priv->base + NSC_DATA);
103	if (status & NSC_STATUS_RDY)
104		return 0;
105
106	/* wait for status */
107	stop = jiffies + 100;
108	do {
109		msleep(TPM_TIMEOUT);
110		status = inb(priv->base + NSC_STATUS);
111		if (status & NSC_STATUS_OBF)
112			status = inb(priv->base + NSC_DATA);
113		if (status & NSC_STATUS_RDY)
114			return 0;
115	}
116	while (time_before(jiffies, stop));
117
118	dev_info(&chip->dev, "wait for ready failed\n");
119	return -EBUSY;
120}
121
122
123static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
124{
125	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
126	u8 *buffer = buf;
127	u8 data, *p;
128	u32 size;
129	__be32 *native_size;
130
131	if (count < 6)
132		return -EIO;
133
134	if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
135		dev_err(&chip->dev, "F0 timeout\n");
136		return -EIO;
137	}
138
139	data = inb(priv->base + NSC_DATA);
140	if (data != NSC_COMMAND_NORMAL) {
141		dev_err(&chip->dev, "not in normal mode (0x%x)\n",
142			data);
143		return -EIO;
144	}
145
146	/* read the whole packet */
147	for (p = buffer; p < &buffer[count]; p++) {
148		if (wait_for_stat
149		    (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
150			dev_err(&chip->dev,
151				"OBF timeout (while reading data)\n");
152			return -EIO;
153		}
154		if (data & NSC_STATUS_F0)
155			break;
156		*p = inb(priv->base + NSC_DATA);
157	}
158
159	if ((data & NSC_STATUS_F0) == 0 &&
160	(wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) {
161		dev_err(&chip->dev, "F0 not set\n");
162		return -EIO;
163	}
164
165	data = inb(priv->base + NSC_DATA);
166	if (data != NSC_COMMAND_EOC) {
167		dev_err(&chip->dev,
168			"expected end of command(0x%x)\n", data);
169		return -EIO;
170	}
171
172	native_size = (__force __be32 *) (buf + 2);
173	size = be32_to_cpu(*native_size);
174
175	if (count < size)
176		return -EIO;
177
178	return size;
179}
180
181static int tpm_nsc_send(struct tpm_chip *chip, u8 *buf, size_t bufsiz,
182			size_t count)
183{
184	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
185	u8 data;
186	int i;
187
188	/*
189	 * If we hit the chip with back to back commands it locks up
190	 * and never set IBF. Hitting it with this "hammer" seems to
191	 * fix it. Not sure why this is needed, we followed the flow
192	 * chart in the manual to the letter.
193	 */
194	outb(NSC_COMMAND_CANCEL, priv->base + NSC_COMMAND);
195
196	if (nsc_wait_for_ready(chip) != 0)
197		return -EIO;
198
199	if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
200		dev_err(&chip->dev, "IBF timeout\n");
201		return -EIO;
202	}
203
204	outb(NSC_COMMAND_NORMAL, priv->base + NSC_COMMAND);
205	if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
206		dev_err(&chip->dev, "IBR timeout\n");
207		return -EIO;
208	}
209
210	for (i = 0; i < count; i++) {
211		if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
212			dev_err(&chip->dev,
213				"IBF timeout (while writing data)\n");
214			return -EIO;
215		}
216		outb(buf[i], priv->base + NSC_DATA);
217	}
218
219	if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
220		dev_err(&chip->dev, "IBF timeout\n");
221		return -EIO;
222	}
223	outb(NSC_COMMAND_EOC, priv->base + NSC_COMMAND);
224
225	return 0;
226}
227
228static void tpm_nsc_cancel(struct tpm_chip *chip)
229{
230	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
231
232	outb(NSC_COMMAND_CANCEL, priv->base + NSC_COMMAND);
233}
234
235static u8 tpm_nsc_status(struct tpm_chip *chip)
236{
237	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
238
239	return inb(priv->base + NSC_STATUS);
240}
241
242static bool tpm_nsc_req_canceled(struct tpm_chip *chip, u8 status)
243{
244	return (status == NSC_STATUS_RDY);
245}
246
247static const struct tpm_class_ops tpm_nsc = {
248	.recv = tpm_nsc_recv,
249	.send = tpm_nsc_send,
250	.cancel = tpm_nsc_cancel,
251	.status = tpm_nsc_status,
252	.req_complete_mask = NSC_STATUS_OBF,
253	.req_complete_val = NSC_STATUS_OBF,
254	.req_canceled = tpm_nsc_req_canceled,
255};
256
257static struct platform_device *pdev = NULL;
258
259static void tpm_nsc_remove(struct device *dev)
260{
261	struct tpm_chip *chip = dev_get_drvdata(dev);
262	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
263
264	tpm_chip_unregister(chip);
265	release_region(priv->base, 2);
266}
267
268static SIMPLE_DEV_PM_OPS(tpm_nsc_pm, tpm_pm_suspend, tpm_pm_resume);
269
270static struct platform_driver nsc_drv = {
271	.driver          = {
272		.name    = "tpm_nsc",
273		.pm      = &tpm_nsc_pm,
274	},
275};
276
277static inline int tpm_read_index(int base, int index)
278{
279	outb(index, base);
280	return inb(base+1) & 0xFF;
281}
282
283static inline void tpm_write_index(int base, int index, int value)
284{
285	outb(index, base);
286	outb(value & 0xFF, base+1);
287}
288
289static int __init init_nsc(void)
290{
291	int rc = 0;
292	int lo, hi, err;
293	int nscAddrBase = TPM_ADDR;
294	struct tpm_chip *chip;
295	unsigned long base;
296	struct tpm_nsc_priv *priv;
297
298	/* verify that it is a National part (SID) */
299	if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) {
300		nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)|
301			(tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE);
302		if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6)
303			return -ENODEV;
304	}
305
306	err = platform_driver_register(&nsc_drv);
307	if (err)
308		return err;
309
310	hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI);
311	lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO);
312	base = (hi<<8) | lo;
313
314	/* enable the DPM module */
315	tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01);
316
317	pdev = platform_device_alloc("tpm_nscl0", -1);
318	if (!pdev) {
319		rc = -ENOMEM;
320		goto err_unreg_drv;
321	}
322
323	pdev->num_resources = 0;
324	pdev->dev.driver = &nsc_drv.driver;
325	pdev->dev.release = tpm_nsc_remove;
326
327	if ((rc = platform_device_add(pdev)) < 0)
328		goto err_put_dev;
329
330	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
331	if (!priv) {
332		rc = -ENOMEM;
333		goto err_del_dev;
334	}
335
336	priv->base = base;
337
338	if (request_region(base, 2, "tpm_nsc0") == NULL ) {
339		rc = -EBUSY;
340		goto err_del_dev;
341	}
342
343	chip = tpmm_chip_alloc(&pdev->dev, &tpm_nsc);
344	if (IS_ERR(chip)) {
345		rc = -ENODEV;
346		goto err_rel_reg;
347	}
348
349	dev_set_drvdata(&chip->dev, priv);
350
351	rc = tpm_chip_register(chip);
352	if (rc)
353		goto err_rel_reg;
354
355	dev_dbg(&pdev->dev, "NSC TPM detected\n");
356	dev_dbg(&pdev->dev,
357		"NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
358		tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20),
359		tpm_read_index(nscAddrBase,0x27));
360	dev_dbg(&pdev->dev,
361		"NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
362		tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25),
363		tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28));
364	dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n",
365		(tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61));
366	dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n",
367		(tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63));
368	dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n",
369		tpm_read_index(nscAddrBase,0x70));
370	dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n",
371		tpm_read_index(nscAddrBase,0x71));
372	dev_dbg(&pdev->dev,
373		"NSC DMA channel select0 0x%x, select1 0x%x\n",
374		tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75));
375	dev_dbg(&pdev->dev,
376		"NSC Config "
377		"0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
378		tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1),
379		tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3),
380		tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5),
381		tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7),
382		tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9));
383
384	dev_info(&pdev->dev,
385		 "NSC TPM revision %d\n",
386		 tpm_read_index(nscAddrBase, 0x27) & 0x1F);
387
388	return 0;
389
390err_rel_reg:
391	release_region(base, 2);
392err_del_dev:
393	platform_device_del(pdev);
394err_put_dev:
395	platform_device_put(pdev);
396err_unreg_drv:
397	platform_driver_unregister(&nsc_drv);
398	return rc;
399}
400
401static void __exit cleanup_nsc(void)
402{
403	if (pdev) {
404		tpm_nsc_remove(&pdev->dev);
405		platform_device_unregister(pdev);
406	}
407
408	platform_driver_unregister(&nsc_drv);
409}
410
411module_init(init_nsc);
412module_exit(cleanup_nsc);
413
414MODULE_AUTHOR("Leendert van Doorn <leendert@watson.ibm.com>");
415MODULE_DESCRIPTION("TPM Driver");
416MODULE_VERSION("2.0");
417MODULE_LICENSE("GPL");