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pci_generic.c
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linux-6.19.14/drivers/bus/mhi/host/pci_generic.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * MHI PCI driver - MHI over PCI controller driver 4 * 5 * This module is a generic driver for registering MHI-over-PCI devices, 6 * such as PCIe QCOM modems. 7 * 8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org> 9 */ 10 11#include <linux/delay.h> 12#include <linux/device.h> 13#include <linux/mhi.h> 14#include <linux/module.h> 15#include <linux/pci.h> 16#include <linux/pm_runtime.h> 17#include <linux/timer.h> 18#include <linux/workqueue.h> 19 20#define MHI_PCI_DEFAULT_BAR_NUM 0 21 22#define MHI_POST_RESET_DELAY_MS 2000 23 24#define HEALTH_CHECK_PERIOD (HZ * 2) 25 26/* PCI VID definitions */ 27#define PCI_VENDOR_ID_THALES 0x1269 28#define PCI_VENDOR_ID_QUECTEL 0x1eac 29#define PCI_VENDOR_ID_NETPRISMA 0x203e 30 31#define MHI_EDL_DB 91 32#define MHI_EDL_COOKIE 0xEDEDEDED 33 34/** 35 * struct mhi_pci_dev_info - MHI PCI device specific information 36 * @config: MHI controller configuration 37 * @vf_config: MHI controller configuration for Virtual function (optional) 38 * @name: name of the PCI module 39 * @fw: firmware path (if any) 40 * @edl: emergency download mode firmware path (if any) 41 * @edl_trigger: capable of triggering EDL mode in the device (if supported) 42 * @bar_num: PCI base address register to use for MHI MMIO register space 43 * @dma_data_width: DMA transfer word size (32 or 64 bits) 44 * @vf_dma_data_width: DMA transfer word size for VF's (optional) 45 * @mru_default: default MRU size for MBIM network packets 46 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead 47 * of inband wake support (such as sdx24) 48 * @no_m3: M3 not supported 49 * @reset_on_remove: Set true for devices that require SoC during driver removal 50 */ 51struct mhi_pci_dev_info { 52 const struct mhi_controller_config *config; 53 const struct mhi_controller_config *vf_config; 54 const char *name; 55 const char *fw; 56 const char *edl; 57 bool edl_trigger; 58 unsigned int bar_num; 59 unsigned int dma_data_width; 60 unsigned int vf_dma_data_width; 61 unsigned int mru_default; 62 bool sideband_wake; 63 bool no_m3; 64 bool reset_on_remove; 65}; 66 67#define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ 68 { \ 69 .num = ch_num, \ 70 .name = ch_name, \ 71 .num_elements = el_count, \ 72 .event_ring = ev_ring, \ 73 .dir = DMA_TO_DEVICE, \ 74 .ee_mask = BIT(MHI_EE_AMSS), \ 75 .pollcfg = 0, \ 76 .doorbell = MHI_DB_BRST_DISABLE, \ 77 .lpm_notify = false, \ 78 .offload_channel = false, \ 79 .doorbell_mode_switch = false, \ 80 } \ 81 82#define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \ 83 { \ 84 .num = ch_num, \ 85 .name = ch_name, \ 86 .num_elements = el_count, \ 87 .event_ring = ev_ring, \ 88 .dir = DMA_FROM_DEVICE, \ 89 .ee_mask = BIT(MHI_EE_AMSS), \ 90 .pollcfg = 0, \ 91 .doorbell = MHI_DB_BRST_DISABLE, \ 92 .lpm_notify = false, \ 93 .offload_channel = false, \ 94 .doorbell_mode_switch = false, \ 95 } 96 97#define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ 98 { \ 99 .num_elements = el_count, \ 100 .irq_moderation_ms = 0, \ 101 .irq = (ev_ring) + 1, \ 102 .priority = 1, \ 103 .mode = MHI_DB_BRST_DISABLE, \ 104 .data_type = MHI_ER_CTRL, \ 105 .hardware_event = false, \ 106 .client_managed = false, \ 107 .offload_channel = false, \ 108 } 109 110#define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ 111 { \ 112 .num = ch_num, \ 113 .name = ch_name, \ 114 .num_elements = el_count, \ 115 .event_ring = ev_ring, \ 116 .dir = DMA_TO_DEVICE, \ 117 .ee_mask = BIT(MHI_EE_AMSS), \ 118 .pollcfg = 0, \ 119 .doorbell = MHI_DB_BRST_ENABLE, \ 120 .lpm_notify = false, \ 121 .offload_channel = false, \ 122 .doorbell_mode_switch = true, \ 123 } \ 124 125#define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ 126 { \ 127 .num = ch_num, \ 128 .name = ch_name, \ 129 .num_elements = el_count, \ 130 .event_ring = ev_ring, \ 131 .dir = DMA_FROM_DEVICE, \ 132 .ee_mask = BIT(MHI_EE_AMSS), \ 133 .pollcfg = 0, \ 134 .doorbell = MHI_DB_BRST_ENABLE, \ 135 .lpm_notify = false, \ 136 .offload_channel = false, \ 137 .doorbell_mode_switch = true, \ 138 } 139 140#define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ 141 { \ 142 .num = ch_num, \ 143 .name = ch_name, \ 144 .num_elements = el_count, \ 145 .event_ring = ev_ring, \ 146 .dir = DMA_TO_DEVICE, \ 147 .ee_mask = BIT(MHI_EE_SBL), \ 148 .pollcfg = 0, \ 149 .doorbell = MHI_DB_BRST_DISABLE, \ 150 .lpm_notify = false, \ 151 .offload_channel = false, \ 152 .doorbell_mode_switch = false, \ 153 } \ 154 155#define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ 156 { \ 157 .num = ch_num, \ 158 .name = ch_name, \ 159 .num_elements = el_count, \ 160 .event_ring = ev_ring, \ 161 .dir = DMA_FROM_DEVICE, \ 162 .ee_mask = BIT(MHI_EE_SBL), \ 163 .pollcfg = 0, \ 164 .doorbell = MHI_DB_BRST_DISABLE, \ 165 .lpm_notify = false, \ 166 .offload_channel = false, \ 167 .doorbell_mode_switch = false, \ 168 } 169 170#define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \ 171 { \ 172 .num = ch_num, \ 173 .name = ch_name, \ 174 .num_elements = el_count, \ 175 .event_ring = ev_ring, \ 176 .dir = DMA_TO_DEVICE, \ 177 .ee_mask = BIT(MHI_EE_FP), \ 178 .pollcfg = 0, \ 179 .doorbell = MHI_DB_BRST_DISABLE, \ 180 .lpm_notify = false, \ 181 .offload_channel = false, \ 182 .doorbell_mode_switch = false, \ 183 } \ 184 185#define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \ 186 { \ 187 .num = ch_num, \ 188 .name = ch_name, \ 189 .num_elements = el_count, \ 190 .event_ring = ev_ring, \ 191 .dir = DMA_FROM_DEVICE, \ 192 .ee_mask = BIT(MHI_EE_FP), \ 193 .pollcfg = 0, \ 194 .doorbell = MHI_DB_BRST_DISABLE, \ 195 .lpm_notify = false, \ 196 .offload_channel = false, \ 197 .doorbell_mode_switch = false, \ 198 } 199 200#define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ 201 { \ 202 .num_elements = el_count, \ 203 .irq_moderation_ms = 5, \ 204 .irq = (ev_ring) + 1, \ 205 .priority = 1, \ 206 .mode = MHI_DB_BRST_DISABLE, \ 207 .data_type = MHI_ER_DATA, \ 208 .hardware_event = false, \ 209 .client_managed = false, \ 210 .offload_channel = false, \ 211 } 212 213#define MHI_EVENT_CONFIG_SW_DATA(ev_ring, el_count) \ 214 { \ 215 .num_elements = el_count, \ 216 .irq_moderation_ms = 0, \ 217 .irq = (ev_ring) + 1, \ 218 .priority = 1, \ 219 .mode = MHI_DB_BRST_DISABLE, \ 220 .data_type = MHI_ER_DATA, \ 221 .hardware_event = false, \ 222 .client_managed = false, \ 223 .offload_channel = false, \ 224 } 225 226#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ 227 { \ 228 .num_elements = el_count, \ 229 .irq_moderation_ms = 1, \ 230 .irq = (ev_ring) + 1, \ 231 .priority = 1, \ 232 .mode = MHI_DB_BRST_DISABLE, \ 233 .data_type = MHI_ER_DATA, \ 234 .hardware_event = true, \ 235 .client_managed = false, \ 236 .offload_channel = false, \ 237 .channel = ch_num, \ 238 } 239 240static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = { 241 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2), 242 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2), 243 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1), 244 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1), 245 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3), 246 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3), 247 MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3), 248 MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4), 249 MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4), 250 MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4), 251 MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4), 252 MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4), 253 MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4), 254 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5), 255 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5), 256}; 257 258static struct mhi_event_config mhi_qcom_qdu100_events[] = { 259 /* first ring is control+data ring */ 260 MHI_EVENT_CONFIG_CTRL(0, 64), 261 /* SAHARA dedicated event ring */ 262 MHI_EVENT_CONFIG_SW_DATA(1, 256), 263 /* Software channels dedicated event ring */ 264 MHI_EVENT_CONFIG_SW_DATA(2, 64), 265 MHI_EVENT_CONFIG_SW_DATA(3, 256), 266 MHI_EVENT_CONFIG_SW_DATA(4, 256), 267 /* Software IP channels dedicated event ring */ 268 MHI_EVENT_CONFIG_SW_DATA(5, 512), 269 MHI_EVENT_CONFIG_SW_DATA(6, 512), 270 MHI_EVENT_CONFIG_SW_DATA(7, 512), 271}; 272 273static const struct mhi_controller_config mhi_qcom_qdu100_config = { 274 .max_channels = 128, 275 .timeout_ms = 120000, 276 .num_channels = ARRAY_SIZE(mhi_qcom_qdu100_channels), 277 .ch_cfg = mhi_qcom_qdu100_channels, 278 .num_events = ARRAY_SIZE(mhi_qcom_qdu100_events), 279 .event_cfg = mhi_qcom_qdu100_events, 280}; 281 282static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = { 283 .name = "qcom-qdu100", 284 .fw = "qcom/qdu100/xbl_s.melf", 285 .edl_trigger = true, 286 .config = &mhi_qcom_qdu100_config, 287 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 288 .dma_data_width = 32, 289 .vf_dma_data_width = 40, 290 .sideband_wake = false, 291 .no_m3 = true, 292 .reset_on_remove = true, 293}; 294 295static const struct mhi_channel_config mhi_qcom_sa8775p_channels[] = { 296 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 2048, 1), 297 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 2048, 2), 298}; 299 300static struct mhi_event_config mhi_qcom_sa8775p_events[] = { 301 /* first ring is control+data ring */ 302 MHI_EVENT_CONFIG_CTRL(0, 64), 303 /* Software channels dedicated event ring */ 304 MHI_EVENT_CONFIG_SW_DATA(1, 64), 305 MHI_EVENT_CONFIG_SW_DATA(2, 64), 306}; 307 308static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { 309 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), 310 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), 311 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0), 312 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0), 313 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0), 314 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), 315 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), 316 MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0), 317 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 318 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 319 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 64, 2), 320 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 64, 3), 321 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 4), 322 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 5), 323}; 324 325static struct mhi_event_config modem_qcom_v1_mhi_events[] = { 326 /* first ring is control+data ring */ 327 MHI_EVENT_CONFIG_CTRL(0, 64), 328 /* DIAG dedicated event ring */ 329 MHI_EVENT_CONFIG_DATA(1, 128), 330 /* Software channels dedicated event ring */ 331 MHI_EVENT_CONFIG_SW_DATA(2, 64), 332 MHI_EVENT_CONFIG_SW_DATA(3, 64), 333 /* Hardware channels request dedicated hardware event rings */ 334 MHI_EVENT_CONFIG_HW_DATA(4, 1024, 100), 335 MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101) 336}; 337 338static const struct mhi_controller_config mhi_qcom_sa8775p_config = { 339 .max_channels = 128, 340 .timeout_ms = 8000, 341 .num_channels = ARRAY_SIZE(mhi_qcom_sa8775p_channels), 342 .ch_cfg = mhi_qcom_sa8775p_channels, 343 .num_events = ARRAY_SIZE(mhi_qcom_sa8775p_events), 344 .event_cfg = mhi_qcom_sa8775p_events, 345}; 346 347static const struct mhi_controller_config modem_qcom_v2_mhiv_config = { 348 .max_channels = 128, 349 .timeout_ms = 8000, 350 .ready_timeout_ms = 50000, 351 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 352 .ch_cfg = modem_qcom_v1_mhi_channels, 353 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 354 .event_cfg = modem_qcom_v1_mhi_events, 355}; 356 357static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { 358 .max_channels = 128, 359 .timeout_ms = 8000, 360 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 361 .ch_cfg = modem_qcom_v1_mhi_channels, 362 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 363 .event_cfg = modem_qcom_v1_mhi_events, 364}; 365 366static const struct mhi_pci_dev_info mhi_qcom_sa8775p_info = { 367 .name = "qcom-sa8775p", 368 .edl_trigger = false, 369 .config = &mhi_qcom_sa8775p_config, 370 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 371 .dma_data_width = 32, 372 .mru_default = 32768, 373 .sideband_wake = false, 374}; 375 376static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = { 377 .name = "qcom-sdx75m", 378 .fw = "qcom/sdx75m/xbl.elf", 379 .edl = "qcom/sdx75m/edl.mbn", 380 .edl_trigger = true, 381 .config = &modem_qcom_v2_mhiv_config, 382 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 383 .dma_data_width = 32, 384 .sideband_wake = false, 385}; 386 387static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = { 388 .name = "qcom-sdx65m", 389 .fw = "qcom/sdx65m/xbl.elf", 390 .edl = "qcom/sdx65m/edl.mbn", 391 .edl_trigger = true, 392 .config = &modem_qcom_v1_mhiv_config, 393 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 394 .dma_data_width = 32, 395 .sideband_wake = false, 396}; 397 398static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { 399 .name = "qcom-sdx55m", 400 .fw = "qcom/sdx55m/sbl1.mbn", 401 .edl = "qcom/sdx55m/edl.mbn", 402 .edl_trigger = true, 403 .config = &modem_qcom_v1_mhiv_config, 404 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 405 .dma_data_width = 32, 406 .mru_default = 32768, 407 .sideband_wake = false, 408}; 409 410static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { 411 .name = "qcom-sdx24", 412 .edl = "qcom/prog_firehose_sdx24.mbn", 413 .config = &modem_qcom_v1_mhiv_config, 414 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 415 .dma_data_width = 32, 416 .sideband_wake = true, 417}; 418 419static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { 420 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), 421 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), 422 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 423 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 424 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 425 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 426 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 427 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 428 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 429 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 430 /* The EDL firmware is a flash-programmer exposing firehose protocol */ 431 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 432 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 433 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 434 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 435}; 436 437static struct mhi_event_config mhi_quectel_em1xx_events[] = { 438 MHI_EVENT_CONFIG_CTRL(0, 128), 439 MHI_EVENT_CONFIG_DATA(1, 128), 440 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 441 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 442}; 443 444static const struct mhi_controller_config modem_quectel_em1xx_config = { 445 .max_channels = 128, 446 .timeout_ms = 20000, 447 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), 448 .ch_cfg = mhi_quectel_em1xx_channels, 449 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), 450 .event_cfg = mhi_quectel_em1xx_events, 451}; 452 453static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { 454 .name = "quectel-em1xx", 455 .edl = "qcom/prog_firehose_sdx24.mbn", 456 .config = &modem_quectel_em1xx_config, 457 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 458 .dma_data_width = 32, 459 .mru_default = 32768, 460 .sideband_wake = true, 461}; 462 463static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = { 464 .name = "quectel-rm5xx", 465 .edl = "qcom/prog_firehose_sdx6x.elf", 466 .config = &modem_quectel_em1xx_config, 467 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 468 .dma_data_width = 32, 469 .mru_default = 32768, 470 .sideband_wake = true, 471}; 472 473static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { 474 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), 475 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), 476 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 477 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 478 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 479 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 480 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 481 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 482 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 483 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 484 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 485 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 486}; 487 488static const struct mhi_channel_config mhi_foxconn_sdx61_channels[] = { 489 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), 490 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), 491 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 492 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 493 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 494 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 495 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 496 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 497 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 498 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 499 MHI_CHANNEL_CONFIG_UL(50, "NMEA", 32, 0), 500 MHI_CHANNEL_CONFIG_DL(51, "NMEA", 32, 0), 501 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 502 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 503}; 504 505static struct mhi_event_config mhi_foxconn_sdx55_events[] = { 506 MHI_EVENT_CONFIG_CTRL(0, 128), 507 MHI_EVENT_CONFIG_DATA(1, 128), 508 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 509 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 510}; 511 512static const struct mhi_controller_config modem_foxconn_sdx55_config = { 513 .max_channels = 128, 514 .timeout_ms = 20000, 515 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 516 .ch_cfg = mhi_foxconn_sdx55_channels, 517 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 518 .event_cfg = mhi_foxconn_sdx55_events, 519}; 520 521static const struct mhi_controller_config modem_foxconn_sdx61_config = { 522 .max_channels = 128, 523 .timeout_ms = 20000, 524 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx61_channels), 525 .ch_cfg = mhi_foxconn_sdx61_channels, 526 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 527 .event_cfg = mhi_foxconn_sdx55_events, 528}; 529 530static const struct mhi_controller_config modem_foxconn_sdx72_config = { 531 .max_channels = 128, 532 .timeout_ms = 20000, 533 .ready_timeout_ms = 50000, 534 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 535 .ch_cfg = mhi_foxconn_sdx55_channels, 536 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 537 .event_cfg = mhi_foxconn_sdx55_events, 538}; 539 540static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { 541 .name = "foxconn-sdx55", 542 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 543 .edl_trigger = true, 544 .config = &modem_foxconn_sdx55_config, 545 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 546 .dma_data_width = 32, 547 .mru_default = 32768, 548 .sideband_wake = false, 549}; 550 551static const struct mhi_pci_dev_info mhi_foxconn_t99w175_info = { 552 .name = "foxconn-t99w175", 553 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 554 .edl_trigger = true, 555 .config = &modem_foxconn_sdx55_config, 556 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 557 .dma_data_width = 32, 558 .mru_default = 32768, 559 .sideband_wake = false, 560}; 561 562static const struct mhi_pci_dev_info mhi_foxconn_dw5930e_info = { 563 .name = "foxconn-dw5930e", 564 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 565 .edl_trigger = true, 566 .config = &modem_foxconn_sdx55_config, 567 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 568 .dma_data_width = 32, 569 .mru_default = 32768, 570 .sideband_wake = false, 571}; 572 573static const struct mhi_pci_dev_info mhi_foxconn_t99w368_info = { 574 .name = "foxconn-t99w368", 575 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 576 .edl_trigger = true, 577 .config = &modem_foxconn_sdx55_config, 578 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 579 .dma_data_width = 32, 580 .mru_default = 32768, 581 .sideband_wake = false, 582}; 583 584static const struct mhi_pci_dev_info mhi_foxconn_t99w373_info = { 585 .name = "foxconn-t99w373", 586 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 587 .edl_trigger = true, 588 .config = &modem_foxconn_sdx55_config, 589 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 590 .dma_data_width = 32, 591 .mru_default = 32768, 592 .sideband_wake = false, 593}; 594 595static const struct mhi_pci_dev_info mhi_foxconn_t99w510_info = { 596 .name = "foxconn-t99w510", 597 .edl = "qcom/sdx24m/foxconn/prog_firehose_sdx24.mbn", 598 .edl_trigger = true, 599 .config = &modem_foxconn_sdx55_config, 600 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 601 .dma_data_width = 32, 602 .mru_default = 32768, 603 .sideband_wake = false, 604}; 605 606static const struct mhi_pci_dev_info mhi_foxconn_dw5932e_info = { 607 .name = "foxconn-dw5932e", 608 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 609 .edl_trigger = true, 610 .config = &modem_foxconn_sdx55_config, 611 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 612 .dma_data_width = 32, 613 .mru_default = 32768, 614 .sideband_wake = false, 615}; 616 617static const struct mhi_pci_dev_info mhi_foxconn_t99w640_info = { 618 .name = "foxconn-t99w640", 619 .edl = "qcom/sdx72m/foxconn/edl.mbn", 620 .edl_trigger = true, 621 .config = &modem_foxconn_sdx72_config, 622 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 623 .dma_data_width = 32, 624 .mru_default = 32768, 625 .sideband_wake = false, 626}; 627 628static const struct mhi_pci_dev_info mhi_foxconn_dw5934e_info = { 629 .name = "foxconn-dw5934e", 630 .edl = "qcom/sdx72m/foxconn/edl.mbn", 631 .edl_trigger = true, 632 .config = &modem_foxconn_sdx72_config, 633 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 634 .dma_data_width = 32, 635 .mru_default = 32768, 636 .sideband_wake = false, 637}; 638 639static const struct mhi_pci_dev_info mhi_foxconn_t99w696_info = { 640 .name = "foxconn-t99w696", 641 .edl = "qcom/sdx61/foxconn/prog_firehose_lite.elf", 642 .edl_trigger = true, 643 .config = &modem_foxconn_sdx61_config, 644 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 645 .dma_data_width = 32, 646 .mru_default = 32768, 647 .sideband_wake = false, 648}; 649 650static const struct mhi_pci_dev_info mhi_foxconn_t99w760_info = { 651 .name = "foxconn-t99w760", 652 .edl = "qcom/sdx35/foxconn/xbl_s_devprg_ns.melf", 653 .edl_trigger = true, 654 .config = &modem_foxconn_sdx61_config, 655 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 656 .dma_data_width = 32, 657 .mru_default = 32768, 658 .sideband_wake = false, 659}; 660 661static const struct mhi_channel_config mhi_mv3x_channels[] = { 662 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0), 663 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0), 664 /* MBIM Control Channel */ 665 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0), 666 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0), 667 /* MBIM Data Channel */ 668 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2), 669 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3), 670}; 671 672static struct mhi_event_config mhi_mv3x_events[] = { 673 MHI_EVENT_CONFIG_CTRL(0, 256), 674 MHI_EVENT_CONFIG_DATA(1, 256), 675 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 676 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101), 677}; 678 679static const struct mhi_controller_config modem_mv3x_config = { 680 .max_channels = 128, 681 .timeout_ms = 20000, 682 .num_channels = ARRAY_SIZE(mhi_mv3x_channels), 683 .ch_cfg = mhi_mv3x_channels, 684 .num_events = ARRAY_SIZE(mhi_mv3x_events), 685 .event_cfg = mhi_mv3x_events, 686}; 687 688static const struct mhi_pci_dev_info mhi_mv31_info = { 689 .name = "cinterion-mv31", 690 .config = &modem_mv3x_config, 691 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 692 .dma_data_width = 32, 693 .mru_default = 32768, 694}; 695 696static const struct mhi_pci_dev_info mhi_mv32_info = { 697 .name = "cinterion-mv32", 698 .config = &modem_mv3x_config, 699 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 700 .dma_data_width = 32, 701 .mru_default = 32768, 702}; 703 704static const struct mhi_channel_config mhi_sierra_em919x_channels[] = { 705 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 706 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 256, 0), 707 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 0), 708 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 0), 709 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 128, 0), 710 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 128, 0), 711 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 712 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 713 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 714 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 715 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 512, 1), 716 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 512, 2), 717}; 718 719static struct mhi_event_config modem_sierra_em919x_mhi_events[] = { 720 /* first ring is control+data and DIAG ring */ 721 MHI_EVENT_CONFIG_CTRL(0, 2048), 722 /* Hardware channels request dedicated hardware event rings */ 723 MHI_EVENT_CONFIG_HW_DATA(1, 2048, 100), 724 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 725}; 726 727static const struct mhi_controller_config modem_sierra_em919x_config = { 728 .max_channels = 128, 729 .timeout_ms = 24000, 730 .num_channels = ARRAY_SIZE(mhi_sierra_em919x_channels), 731 .ch_cfg = mhi_sierra_em919x_channels, 732 .num_events = ARRAY_SIZE(modem_sierra_em919x_mhi_events), 733 .event_cfg = modem_sierra_em919x_mhi_events, 734}; 735 736static const struct mhi_pci_dev_info mhi_sierra_em919x_info = { 737 .name = "sierra-em919x", 738 .config = &modem_sierra_em919x_config, 739 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 740 .dma_data_width = 32, 741 .mru_default = 32768, 742 .sideband_wake = false, 743}; 744 745static const struct mhi_channel_config mhi_telit_fn980_hw_v1_channels[] = { 746 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 747 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 748 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 16, 0), 749 MHI_CHANNEL_CONFIG_DL(21, "IPCR", 16, 0), 750 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), 751 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), 752}; 753 754static struct mhi_event_config mhi_telit_fn980_hw_v1_events[] = { 755 MHI_EVENT_CONFIG_CTRL(0, 128), 756 MHI_EVENT_CONFIG_HW_DATA(1, 1024, 100), 757 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 758}; 759 760static const struct mhi_controller_config modem_telit_fn980_hw_v1_config = { 761 .max_channels = 128, 762 .timeout_ms = 20000, 763 .num_channels = ARRAY_SIZE(mhi_telit_fn980_hw_v1_channels), 764 .ch_cfg = mhi_telit_fn980_hw_v1_channels, 765 .num_events = ARRAY_SIZE(mhi_telit_fn980_hw_v1_events), 766 .event_cfg = mhi_telit_fn980_hw_v1_events, 767}; 768 769static const struct mhi_pci_dev_info mhi_telit_fn980_hw_v1_info = { 770 .name = "telit-fn980-hwv1", 771 .fw = "qcom/sdx55m/sbl1.mbn", 772 .edl = "qcom/sdx55m/edl.mbn", 773 .config = &modem_telit_fn980_hw_v1_config, 774 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 775 .dma_data_width = 32, 776 .mru_default = 32768, 777 .sideband_wake = false, 778}; 779 780static const struct mhi_channel_config mhi_telit_fn990_channels[] = { 781 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 782 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 783 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1), 784 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1), 785 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 786 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 787 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 788 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 789 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1), 790 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1), 791 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 792 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 793}; 794 795static struct mhi_event_config mhi_telit_fn990_events[] = { 796 MHI_EVENT_CONFIG_CTRL(0, 128), 797 MHI_EVENT_CONFIG_DATA(1, 128), 798 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 799 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) 800}; 801 802static const struct mhi_controller_config modem_telit_fn990_config = { 803 .max_channels = 128, 804 .timeout_ms = 20000, 805 .num_channels = ARRAY_SIZE(mhi_telit_fn990_channels), 806 .ch_cfg = mhi_telit_fn990_channels, 807 .num_events = ARRAY_SIZE(mhi_telit_fn990_events), 808 .event_cfg = mhi_telit_fn990_events, 809}; 810 811static const struct mhi_pci_dev_info mhi_telit_fn990_info = { 812 .name = "telit-fn990", 813 .config = &modem_telit_fn990_config, 814 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 815 .dma_data_width = 32, 816 .sideband_wake = false, 817 .mru_default = 32768, 818}; 819 820static const struct mhi_pci_dev_info mhi_telit_fe990a_info = { 821 .name = "telit-fe990a", 822 .config = &modem_telit_fn990_config, 823 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 824 .dma_data_width = 32, 825 .sideband_wake = false, 826 .mru_default = 32768, 827}; 828 829static const struct mhi_channel_config mhi_telit_fn920c04_channels[] = { 830 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 831 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 832 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1), 833 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1), 834 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 835 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 836 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 837 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 838 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 839 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 840 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1), 841 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1), 842 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2), 843 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3), 844}; 845 846static const struct mhi_controller_config modem_telit_fn920c04_config = { 847 .max_channels = 128, 848 .timeout_ms = 50000, 849 .num_channels = ARRAY_SIZE(mhi_telit_fn920c04_channels), 850 .ch_cfg = mhi_telit_fn920c04_channels, 851 .num_events = ARRAY_SIZE(mhi_telit_fn990_events), 852 .event_cfg = mhi_telit_fn990_events, 853}; 854 855static const struct mhi_pci_dev_info mhi_telit_fn920c04_info = { 856 .name = "telit-fn920c04", 857 .config = &modem_telit_fn920c04_config, 858 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 859 .dma_data_width = 32, 860 .sideband_wake = false, 861 .mru_default = 32768, 862 .edl_trigger = true, 863}; 864 865static const struct mhi_pci_dev_info mhi_telit_fn990b40_info = { 866 .name = "telit-fn990b40", 867 .config = &modem_telit_fn920c04_config, 868 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 869 .dma_data_width = 32, 870 .sideband_wake = false, 871 .mru_default = 32768, 872 .edl_trigger = true, 873}; 874 875static const struct mhi_pci_dev_info mhi_telit_fe990b40_info = { 876 .name = "telit-fe990b40", 877 .config = &modem_telit_fn920c04_config, 878 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 879 .dma_data_width = 32, 880 .sideband_wake = false, 881 .mru_default = 32768, 882 .edl_trigger = true, 883}; 884 885static const struct mhi_pci_dev_info mhi_netprisma_lcur57_info = { 886 .name = "netprisma-lcur57", 887 .edl = "qcom/prog_firehose_sdx24.mbn", 888 .config = &modem_quectel_em1xx_config, 889 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 890 .dma_data_width = 32, 891 .mru_default = 32768, 892 .sideband_wake = true, 893}; 894 895static const struct mhi_pci_dev_info mhi_netprisma_fcun69_info = { 896 .name = "netprisma-fcun69", 897 .edl = "qcom/prog_firehose_sdx6x.elf", 898 .config = &modem_quectel_em1xx_config, 899 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 900 .dma_data_width = 32, 901 .mru_default = 32768, 902 .sideband_wake = true, 903}; 904 905/* Keep the list sorted based on the PID. New VID should be added as the last entry */ 906static const struct pci_device_id mhi_pci_id_table[] = { 907 {PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0116), 908 .driver_data = (kernel_ulong_t) &mhi_qcom_sa8775p_info }, 909 /* Telit FN920C04 (sdx35) */ 910 {PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x011a, 0x1c5d, 0x2020), 911 .driver_data = (kernel_ulong_t) &mhi_telit_fn920c04_info }, 912 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), 913 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, 914 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c), 915 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 916 /* EM919x (sdx55), use the same vid:pid as qcom-sdx55m */ 917 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x18d7, 0x0200), 918 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info }, 919 /* EM929x (sdx65), use the same configuration as EM919x */ 920 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x18d7, 0x0301), 921 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info }, 922 /* Telit FN980 hardware revision v1 */ 923 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x1C5D, 0x2000), 924 .driver_data = (kernel_ulong_t) &mhi_telit_fn980_hw_v1_info }, 925 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), 926 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, 927 /* Telit FN990 */ 928 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2010), 929 .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info }, 930 /* Telit FE990A */ 931 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2015), 932 .driver_data = (kernel_ulong_t) &mhi_telit_fe990a_info }, 933 /* Foxconn T99W696, all variants */ 934 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, PCI_VENDOR_ID_FOXCONN, PCI_ANY_ID), 935 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w696_info }, 936 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308), 937 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, 938 /* Telit FN990B40 (sdx72) */ 939 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0309, 0x1c5d, 0x201a), 940 .driver_data = (kernel_ulong_t) &mhi_telit_fn990b40_info }, 941 /* Telit FE990B40 (sdx72) */ 942 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0309, 0x1c5d, 0x2025), 943 .driver_data = (kernel_ulong_t) &mhi_telit_fe990b40_info }, 944 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309), 945 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info }, 946 /* QDU100, x100-DU */ 947 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601), 948 .driver_data = (kernel_ulong_t) &mhi_qcom_qdu100_info }, 949 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */ 950 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 951 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ 952 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 953 /* RM520N-GL (sdx6x), eSIM */ 954 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004), 955 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, 956 /* RM520N-GL (sdx6x), Lenovo variant */ 957 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1007), 958 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, 959 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x100d), /* EM160R-GL (sdx24) */ 960 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 961 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */ 962 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 963 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */ 964 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), 965 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 966 /* DW5930e (sdx55), With eSIM, It's also T99W175 */ 967 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0), 968 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info }, 969 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */ 970 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1), 971 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info }, 972 /* T99W175 (sdx55), Based on Qualcomm new baseline */ 973 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0bf), 974 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 975 /* T99W175 (sdx55) */ 976 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0c3), 977 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 978 /* T99W368 (sdx65) */ 979 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d8), 980 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w368_info }, 981 /* T99W373 (sdx62) */ 982 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9), 983 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w373_info }, 984 /* T99W510 (sdx24), variant 1 */ 985 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f0), 986 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 987 /* T99W510 (sdx24), variant 2 */ 988 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f1), 989 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 990 /* T99W510 (sdx24), variant 3 */ 991 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f2), 992 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 993 /* DW5932e-eSIM (sdx62), With eSIM */ 994 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f5), 995 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info }, 996 /* DW5932e (sdx62), Non-eSIM */ 997 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f9), 998 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info }, 999 /* T99W640 (sdx72) */ 1000 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe118), 1001 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w640_info }, 1002 /* DW5934e(sdx72), With eSIM */ 1003 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11d), 1004 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, 1005 /* DW5934e(sdx72), Non-eSIM */ 1006 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11e), 1007 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, 1008 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe123), 1009 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w760_info }, 1010 /* MV31-W (Cinterion) */ 1011 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3), 1012 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 1013 /* MV31-W (Cinterion), based on new baseline */ 1014 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b4), 1015 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 1016 /* MV32-WA (Cinterion) */ 1017 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00ba), 1018 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 1019 /* MV32-WB (Cinterion) */ 1020 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00bb), 1021 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 1022 /* T99W175 (sdx55), HP variant */ 1023 { PCI_DEVICE(0x03f0, 0x0a6c), 1024 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 1025 /* NETPRISMA LCUR57 (SDX24) */ 1026 { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1000), 1027 .driver_data = (kernel_ulong_t) &mhi_netprisma_lcur57_info }, 1028 /* NETPRISMA FCUN69 (SDX6X) */ 1029 { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1001), 1030 .driver_data = (kernel_ulong_t) &mhi_netprisma_fcun69_info }, 1031 { } 1032}; 1033MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); 1034 1035enum mhi_pci_device_status { 1036 MHI_PCI_DEV_STARTED, 1037 MHI_PCI_DEV_SUSPENDED, 1038}; 1039 1040struct mhi_pci_device { 1041 struct mhi_controller mhi_cntrl; 1042 struct pci_saved_state *pci_state; 1043 struct work_struct recovery_work; 1044 struct timer_list health_check_timer; 1045 unsigned long status; 1046 bool reset_on_remove; 1047}; 1048 1049static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, 1050 void __iomem *addr, u32 *out) 1051{ 1052 *out = readl(addr); 1053 return 0; 1054} 1055 1056static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl, 1057 void __iomem *addr, u32 val) 1058{ 1059 writel(val, addr); 1060} 1061 1062static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, 1063 enum mhi_callback cb) 1064{ 1065 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1066 1067 /* Nothing to do for now */ 1068 switch (cb) { 1069 case MHI_CB_FATAL_ERROR: 1070 case MHI_CB_SYS_ERROR: 1071 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb); 1072 pm_runtime_forbid(&pdev->dev); 1073 break; 1074 case MHI_CB_EE_MISSION_MODE: 1075 pm_runtime_allow(&pdev->dev); 1076 break; 1077 default: 1078 break; 1079 } 1080} 1081 1082static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force) 1083{ 1084 /* no-op */ 1085} 1086 1087static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override) 1088{ 1089 /* no-op */ 1090} 1091 1092static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl) 1093{ 1094 /* no-op */ 1095} 1096 1097static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) 1098{ 1099 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1100 u16 vendor = 0; 1101 1102 if (pci_read_config_word(pci_physfn(pdev), PCI_VENDOR_ID, &vendor)) 1103 return false; 1104 1105 if (vendor == (u16) ~0 || vendor == 0) 1106 return false; 1107 1108 return true; 1109} 1110 1111static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, 1112 unsigned int bar_num, u64 dma_mask) 1113{ 1114 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1115 int err; 1116 1117 err = pcim_enable_device(pdev); 1118 if (err) { 1119 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err); 1120 return err; 1121 } 1122 1123 mhi_cntrl->regs = pcim_iomap_region(pdev, bar_num, pci_name(pdev)); 1124 if (IS_ERR(mhi_cntrl->regs)) { 1125 err = PTR_ERR(mhi_cntrl->regs); 1126 dev_err(&pdev->dev, "failed to map pci region: %d\n", err); 1127 return err; 1128 } 1129 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num); 1130 1131 err = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 1132 if (err) { 1133 dev_err(&pdev->dev, "Cannot set proper DMA mask\n"); 1134 return err; 1135 } 1136 1137 pci_set_master(pdev); 1138 1139 return 0; 1140} 1141 1142static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl, 1143 const struct mhi_controller_config *mhi_cntrl_config) 1144{ 1145 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1146 int nr_vectors, i; 1147 int *irq; 1148 1149 /* 1150 * Alloc one MSI vector for BHI + one vector per event ring, ideally... 1151 * No explicit pci_free_irq_vectors required, done by pcim_release. 1152 */ 1153 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events; 1154 1155 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSIX | PCI_IRQ_MSI); 1156 if (nr_vectors < 0) { 1157 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n", 1158 nr_vectors); 1159 return nr_vectors; 1160 } 1161 1162 if (nr_vectors < mhi_cntrl->nr_irqs) { 1163 dev_warn(&pdev->dev, "using shared MSI\n"); 1164 1165 /* Patch msi vectors, use only one (shared) */ 1166 for (i = 0; i < mhi_cntrl_config->num_events; i++) 1167 mhi_cntrl_config->event_cfg[i].irq = 0; 1168 mhi_cntrl->nr_irqs = 1; 1169 } 1170 1171 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL); 1172 if (!irq) 1173 return -ENOMEM; 1174 1175 for (i = 0; i < mhi_cntrl->nr_irqs; i++) { 1176 int vector = i >= nr_vectors ? (nr_vectors - 1) : i; 1177 1178 irq[i] = pci_irq_vector(pdev, vector); 1179 } 1180 1181 mhi_cntrl->irq = irq; 1182 1183 return 0; 1184} 1185 1186static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl) 1187{ 1188 /* The runtime_get() MHI callback means: 1189 * Do whatever is requested to leave M3. 1190 */ 1191 return pm_runtime_get(mhi_cntrl->cntrl_dev); 1192} 1193 1194static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) 1195{ 1196 /* The runtime_put() MHI callback means: 1197 * Device can be moved in M3 state. 1198 */ 1199 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev); 1200 pm_runtime_put(mhi_cntrl->cntrl_dev); 1201} 1202 1203static void mhi_pci_recovery_work(struct work_struct *work) 1204{ 1205 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device, 1206 recovery_work); 1207 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1208 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1209 int err; 1210 1211 dev_warn(&pdev->dev, "device recovery started\n"); 1212 1213 if (pdev->is_physfn) 1214 timer_delete(&mhi_pdev->health_check_timer); 1215 1216 pm_runtime_forbid(&pdev->dev); 1217 1218 /* Clean up MHI state */ 1219 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1220 mhi_power_down(mhi_cntrl, false); 1221 mhi_unprepare_after_power_down(mhi_cntrl); 1222 } 1223 1224 pci_set_power_state(pdev, PCI_D0); 1225 pci_load_saved_state(pdev, mhi_pdev->pci_state); 1226 pci_restore_state(pdev); 1227 1228 if (!mhi_pci_is_alive(mhi_cntrl)) 1229 goto err_try_reset; 1230 1231 err = mhi_prepare_for_power_up(mhi_cntrl); 1232 if (err) 1233 goto err_try_reset; 1234 1235 err = mhi_sync_power_up(mhi_cntrl); 1236 if (err) 1237 goto err_unprepare; 1238 1239 dev_dbg(&pdev->dev, "Recovery completed\n"); 1240 1241 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1242 1243 if (pdev->is_physfn) 1244 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1245 1246 return; 1247 1248err_unprepare: 1249 mhi_unprepare_after_power_down(mhi_cntrl); 1250err_try_reset: 1251 err = pci_try_reset_function(pdev); 1252 if (err) 1253 dev_err(&pdev->dev, "Recovery failed: %d\n", err); 1254} 1255 1256static void health_check(struct timer_list *t) 1257{ 1258 struct mhi_pci_device *mhi_pdev = timer_container_of(mhi_pdev, t, 1259 health_check_timer); 1260 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1261 1262 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1263 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1264 return; 1265 1266 if (!mhi_pci_is_alive(mhi_cntrl)) { 1267 dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); 1268 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1269 return; 1270 } 1271 1272 /* reschedule in two seconds */ 1273 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1274} 1275 1276static int mhi_pci_generic_edl_trigger(struct mhi_controller *mhi_cntrl) 1277{ 1278 void __iomem *base = mhi_cntrl->regs; 1279 void __iomem *edl_db; 1280 int ret; 1281 u32 val; 1282 1283 ret = mhi_device_get_sync(mhi_cntrl->mhi_dev); 1284 if (ret) { 1285 dev_err(mhi_cntrl->cntrl_dev, "Failed to wakeup the device\n"); 1286 return ret; 1287 } 1288 1289 pm_wakeup_event(&mhi_cntrl->mhi_dev->dev, 0); 1290 mhi_cntrl->runtime_get(mhi_cntrl); 1291 1292 ret = mhi_get_channel_doorbell_offset(mhi_cntrl, &val); 1293 if (ret) 1294 goto err_get_chdb; 1295 1296 edl_db = base + val + (8 * MHI_EDL_DB); 1297 1298 mhi_cntrl->write_reg(mhi_cntrl, edl_db + 4, upper_32_bits(MHI_EDL_COOKIE)); 1299 mhi_cntrl->write_reg(mhi_cntrl, edl_db, lower_32_bits(MHI_EDL_COOKIE)); 1300 1301 mhi_soc_reset(mhi_cntrl); 1302 1303err_get_chdb: 1304 mhi_cntrl->runtime_put(mhi_cntrl); 1305 mhi_device_put(mhi_cntrl->mhi_dev); 1306 1307 return ret; 1308} 1309 1310static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1311{ 1312 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; 1313 const struct mhi_controller_config *mhi_cntrl_config; 1314 struct mhi_pci_device *mhi_pdev; 1315 struct mhi_controller *mhi_cntrl; 1316 unsigned int dma_data_width; 1317 int err; 1318 1319 dev_info(&pdev->dev, "MHI PCI device found: %s\n", info->name); 1320 1321 /* mhi_pdev.mhi_cntrl must be zero-initialized */ 1322 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL); 1323 if (!mhi_pdev) 1324 return -ENOMEM; 1325 1326 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); 1327 1328 if (pdev->is_virtfn && info->vf_config) 1329 mhi_cntrl_config = info->vf_config; 1330 else 1331 mhi_cntrl_config = info->config; 1332 1333 /* Initialize health check monitor only for Physical functions */ 1334 if (pdev->is_physfn) 1335 timer_setup(&mhi_pdev->health_check_timer, health_check, 0); 1336 1337 mhi_cntrl = &mhi_pdev->mhi_cntrl; 1338 1339 dma_data_width = (pdev->is_virtfn && info->vf_dma_data_width) ? 1340 info->vf_dma_data_width : info->dma_data_width; 1341 1342 mhi_cntrl->cntrl_dev = &pdev->dev; 1343 mhi_cntrl->iova_start = 0; 1344 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(dma_data_width); 1345 mhi_cntrl->fw_image = info->fw; 1346 mhi_cntrl->edl_image = info->edl; 1347 1348 mhi_cntrl->read_reg = mhi_pci_read_reg; 1349 mhi_cntrl->write_reg = mhi_pci_write_reg; 1350 mhi_cntrl->status_cb = mhi_pci_status_cb; 1351 mhi_cntrl->runtime_get = mhi_pci_runtime_get; 1352 mhi_cntrl->runtime_put = mhi_pci_runtime_put; 1353 mhi_cntrl->mru = info->mru_default; 1354 mhi_cntrl->name = info->name; 1355 1356 if (pdev->is_physfn) 1357 mhi_pdev->reset_on_remove = info->reset_on_remove; 1358 1359 if (info->edl_trigger) 1360 mhi_cntrl->edl_trigger = mhi_pci_generic_edl_trigger; 1361 1362 if (info->sideband_wake) { 1363 mhi_cntrl->wake_get = mhi_pci_wake_get_nop; 1364 mhi_cntrl->wake_put = mhi_pci_wake_put_nop; 1365 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; 1366 } 1367 1368 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(dma_data_width)); 1369 if (err) 1370 return err; 1371 1372 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config); 1373 if (err) 1374 return err; 1375 1376 pci_set_drvdata(pdev, mhi_pdev); 1377 1378 /* Have stored pci confspace at hand for restore in sudden PCI error. 1379 * cache the state locally and discard the PCI core one. 1380 */ 1381 pci_save_state(pdev); 1382 mhi_pdev->pci_state = pci_store_saved_state(pdev); 1383 pci_load_saved_state(pdev, NULL); 1384 1385 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); 1386 if (err) 1387 return err; 1388 1389 /* MHI bus does not power up the controller by default */ 1390 err = mhi_prepare_for_power_up(mhi_cntrl); 1391 if (err) { 1392 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1393 goto err_unregister; 1394 } 1395 1396 err = mhi_sync_power_up(mhi_cntrl); 1397 if (err) { 1398 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1399 goto err_unprepare; 1400 } 1401 1402 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1403 1404 /* start health check */ 1405 if (pdev->is_physfn) 1406 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1407 1408 /* Allow runtime suspend only if both PME from D3Hot and M3 are supported */ 1409 if (pci_pme_capable(pdev, PCI_D3hot) && !(info->no_m3)) { 1410 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 1411 pm_runtime_use_autosuspend(&pdev->dev); 1412 pm_runtime_mark_last_busy(&pdev->dev); 1413 pm_runtime_put_noidle(&pdev->dev); 1414 } 1415 1416 return 0; 1417 1418err_unprepare: 1419 mhi_unprepare_after_power_down(mhi_cntrl); 1420err_unregister: 1421 mhi_unregister_controller(mhi_cntrl); 1422 1423 return err; 1424} 1425 1426static void mhi_pci_remove(struct pci_dev *pdev) 1427{ 1428 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1429 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1430 1431 pci_disable_sriov(pdev); 1432 1433 if (pdev->is_physfn) 1434 timer_delete_sync(&mhi_pdev->health_check_timer); 1435 cancel_work_sync(&mhi_pdev->recovery_work); 1436 1437 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1438 mhi_power_down(mhi_cntrl, true); 1439 mhi_unprepare_after_power_down(mhi_cntrl); 1440 } 1441 1442 /* balancing probe put_noidle */ 1443 if (pci_pme_capable(pdev, PCI_D3hot)) 1444 pm_runtime_get_noresume(&pdev->dev); 1445 1446 if (mhi_pdev->reset_on_remove) 1447 mhi_soc_reset(mhi_cntrl); 1448 1449 mhi_unregister_controller(mhi_cntrl); 1450} 1451 1452static void mhi_pci_shutdown(struct pci_dev *pdev) 1453{ 1454 mhi_pci_remove(pdev); 1455 pci_set_power_state(pdev, PCI_D3hot); 1456} 1457 1458static void mhi_pci_reset_prepare(struct pci_dev *pdev) 1459{ 1460 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1461 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1462 1463 dev_info(&pdev->dev, "reset\n"); 1464 1465 if (pdev->is_physfn) 1466 timer_delete(&mhi_pdev->health_check_timer); 1467 1468 /* Clean up MHI state */ 1469 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1470 mhi_power_down(mhi_cntrl, false); 1471 mhi_unprepare_after_power_down(mhi_cntrl); 1472 } 1473 1474 /* cause internal device reset */ 1475 mhi_soc_reset(mhi_cntrl); 1476 1477 /* Be sure device reset has been executed */ 1478 msleep(MHI_POST_RESET_DELAY_MS); 1479} 1480 1481static void mhi_pci_reset_done(struct pci_dev *pdev) 1482{ 1483 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1484 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1485 int err; 1486 1487 /* Restore initial known working PCI state */ 1488 pci_load_saved_state(pdev, mhi_pdev->pci_state); 1489 pci_restore_state(pdev); 1490 1491 /* Is device status available ? */ 1492 if (!mhi_pci_is_alive(mhi_cntrl)) { 1493 dev_err(&pdev->dev, "reset failed\n"); 1494 return; 1495 } 1496 1497 err = mhi_prepare_for_power_up(mhi_cntrl); 1498 if (err) { 1499 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1500 return; 1501 } 1502 1503 err = mhi_sync_power_up(mhi_cntrl); 1504 if (err) { 1505 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1506 mhi_unprepare_after_power_down(mhi_cntrl); 1507 return; 1508 } 1509 1510 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1511 if (pdev->is_physfn) 1512 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1513} 1514 1515static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, 1516 pci_channel_state_t state) 1517{ 1518 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1519 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1520 1521 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state); 1522 1523 if (state == pci_channel_io_perm_failure) 1524 return PCI_ERS_RESULT_DISCONNECT; 1525 1526 /* Clean up MHI state */ 1527 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1528 mhi_power_down(mhi_cntrl, false); 1529 mhi_unprepare_after_power_down(mhi_cntrl); 1530 } else { 1531 /* Nothing to do */ 1532 return PCI_ERS_RESULT_RECOVERED; 1533 } 1534 1535 pci_disable_device(pdev); 1536 1537 return PCI_ERS_RESULT_NEED_RESET; 1538} 1539 1540static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev) 1541{ 1542 if (pci_enable_device(pdev)) { 1543 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); 1544 return PCI_ERS_RESULT_DISCONNECT; 1545 } 1546 1547 return PCI_ERS_RESULT_RECOVERED; 1548} 1549 1550static void mhi_pci_io_resume(struct pci_dev *pdev) 1551{ 1552 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1553 1554 dev_err(&pdev->dev, "PCI slot reset done\n"); 1555 1556 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1557} 1558 1559static const struct pci_error_handlers mhi_pci_err_handler = { 1560 .error_detected = mhi_pci_error_detected, 1561 .slot_reset = mhi_pci_slot_reset, 1562 .resume = mhi_pci_io_resume, 1563 .reset_prepare = mhi_pci_reset_prepare, 1564 .reset_done = mhi_pci_reset_done, 1565}; 1566 1567static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev) 1568{ 1569 struct pci_dev *pdev = to_pci_dev(dev); 1570 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1571 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1572 int err; 1573 1574 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1575 return 0; 1576 1577 if (pdev->is_physfn) 1578 timer_delete(&mhi_pdev->health_check_timer); 1579 1580 cancel_work_sync(&mhi_pdev->recovery_work); 1581 1582 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1583 mhi_cntrl->ee != MHI_EE_AMSS) 1584 goto pci_suspend; /* Nothing to do at MHI level */ 1585 1586 /* Transition to M3 state */ 1587 err = mhi_pm_suspend(mhi_cntrl); 1588 if (err) { 1589 dev_err(&pdev->dev, "failed to suspend device: %d\n", err); 1590 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status); 1591 return -EBUSY; 1592 } 1593 1594pci_suspend: 1595 pci_disable_device(pdev); 1596 pci_wake_from_d3(pdev, true); 1597 1598 return 0; 1599} 1600 1601static int __maybe_unused mhi_pci_runtime_resume(struct device *dev) 1602{ 1603 struct pci_dev *pdev = to_pci_dev(dev); 1604 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1605 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1606 int err; 1607 1608 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1609 return 0; 1610 1611 err = pci_enable_device(pdev); 1612 if (err) 1613 goto err_recovery; 1614 1615 pci_set_master(pdev); 1616 pci_wake_from_d3(pdev, false); 1617 1618 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1619 mhi_cntrl->ee != MHI_EE_AMSS) 1620 return 0; /* Nothing to do at MHI level */ 1621 1622 /* Exit M3, transition to M0 state */ 1623 err = mhi_pm_resume(mhi_cntrl); 1624 if (err) { 1625 dev_err(&pdev->dev, "failed to resume device: %d\n", err); 1626 goto err_recovery; 1627 } 1628 1629 /* Resume health check */ 1630 if (pdev->is_physfn) 1631 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1632 1633 /* It can be a remote wakeup (no mhi runtime_get), update access time */ 1634 pm_runtime_mark_last_busy(dev); 1635 1636 return 0; 1637 1638err_recovery: 1639 /* Do not fail to not mess up our PCI device state, the device likely 1640 * lost power (d3cold) and we simply need to reset it from the recovery 1641 * procedure, trigger the recovery asynchronously to prevent system 1642 * suspend exit delaying. 1643 */ 1644 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1645 pm_runtime_mark_last_busy(dev); 1646 1647 return 0; 1648} 1649 1650static int __maybe_unused mhi_pci_suspend(struct device *dev) 1651{ 1652 pm_runtime_disable(dev); 1653 return mhi_pci_runtime_suspend(dev); 1654} 1655 1656static int __maybe_unused mhi_pci_resume(struct device *dev) 1657{ 1658 int ret; 1659 1660 /* Depending the platform, device may have lost power (d3cold), we need 1661 * to resume it now to check its state and recover when necessary. 1662 */ 1663 ret = mhi_pci_runtime_resume(dev); 1664 pm_runtime_enable(dev); 1665 1666 return ret; 1667} 1668 1669static int __maybe_unused mhi_pci_freeze(struct device *dev) 1670{ 1671 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1672 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1673 1674 /* We want to stop all operations, hibernation does not guarantee that 1675 * device will be in the same state as before freezing, especially if 1676 * the intermediate restore kernel reinitializes MHI device with new 1677 * context. 1678 */ 1679 flush_work(&mhi_pdev->recovery_work); 1680 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1681 mhi_power_down(mhi_cntrl, true); 1682 mhi_unprepare_after_power_down(mhi_cntrl); 1683 } 1684 1685 return 0; 1686} 1687 1688static int __maybe_unused mhi_pci_restore(struct device *dev) 1689{ 1690 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1691 1692 /* Reinitialize the device */ 1693 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1694 1695 return 0; 1696} 1697 1698static const struct dev_pm_ops mhi_pci_pm_ops = { 1699 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL) 1700#ifdef CONFIG_PM_SLEEP 1701 .suspend = mhi_pci_suspend, 1702 .resume = mhi_pci_resume, 1703 .freeze = mhi_pci_freeze, 1704 .thaw = mhi_pci_restore, 1705 .poweroff = mhi_pci_freeze, 1706 .restore = mhi_pci_restore, 1707#endif 1708}; 1709 1710static struct pci_driver mhi_pci_driver = { 1711 .name = "mhi-pci-generic", 1712 .id_table = mhi_pci_id_table, 1713 .probe = mhi_pci_probe, 1714 .remove = mhi_pci_remove, 1715 .shutdown = mhi_pci_shutdown, 1716 .err_handler = &mhi_pci_err_handler, 1717 .driver.pm = &mhi_pci_pm_ops, 1718 .sriov_configure = pci_sriov_configure_simple, 1719}; 1720module_pci_driver(mhi_pci_driver); 1721 1722MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>"); 1723MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver"); 1724MODULE_LICENSE("GPL");
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