btintel_pcie.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 *
  4 *  Bluetooth support for Intel PCIe devices
  5 *
  6 *  Copyright (C) 2024  Intel Corporation
  7 */
  8
  9/* Control and Status Register(BTINTEL_PCIE_CSR) */
 10#define BTINTEL_PCIE_CSR_BASE			(0x000)
 11#define BTINTEL_PCIE_CSR_FUNC_CTRL_REG		(BTINTEL_PCIE_CSR_BASE + 0x024)
 12#define BTINTEL_PCIE_CSR_HW_REV_REG		(BTINTEL_PCIE_CSR_BASE + 0x028)
 13#define BTINTEL_PCIE_CSR_RF_ID_REG		(BTINTEL_PCIE_CSR_BASE + 0x09C)
 14#define BTINTEL_PCIE_CSR_BOOT_STAGE_REG		(BTINTEL_PCIE_CSR_BASE + 0x108)
 15#define BTINTEL_PCIE_CSR_IPC_CONTROL_REG	(BTINTEL_PCIE_CSR_BASE + 0x10C)
 16#define BTINTEL_PCIE_CSR_IPC_STATUS_REG		(BTINTEL_PCIE_CSR_BASE + 0x110)
 17#define BTINTEL_PCIE_CSR_IPC_SLEEP_CTL_REG	(BTINTEL_PCIE_CSR_BASE + 0x114)
 18#define BTINTEL_PCIE_CSR_CI_ADDR_LSB_REG	(BTINTEL_PCIE_CSR_BASE + 0x118)
 19#define BTINTEL_PCIE_CSR_CI_ADDR_MSB_REG	(BTINTEL_PCIE_CSR_BASE + 0x11C)
 20#define BTINTEL_PCIE_CSR_IMG_RESPONSE_REG	(BTINTEL_PCIE_CSR_BASE + 0x12C)
 21#define BTINTEL_PCIE_CSR_MBOX_1_REG		(BTINTEL_PCIE_CSR_BASE + 0x170)
 22#define BTINTEL_PCIE_CSR_MBOX_2_REG		(BTINTEL_PCIE_CSR_BASE + 0x174)
 23#define BTINTEL_PCIE_CSR_MBOX_3_REG		(BTINTEL_PCIE_CSR_BASE + 0x178)
 24#define BTINTEL_PCIE_CSR_MBOX_4_REG		(BTINTEL_PCIE_CSR_BASE + 0x17C)
 25#define BTINTEL_PCIE_CSR_MBOX_STATUS_REG	(BTINTEL_PCIE_CSR_BASE + 0x180)
 26#define BTINTEL_PCIE_PRPH_DEV_ADDR_REG		(BTINTEL_PCIE_CSR_BASE + 0x440)
 27#define BTINTEL_PCIE_PRPH_DEV_RD_REG		(BTINTEL_PCIE_CSR_BASE + 0x458)
 28#define BTINTEL_PCIE_CSR_HBUS_TARG_WRPTR	(BTINTEL_PCIE_CSR_BASE + 0x460)
 29
 30/* BTINTEL_PCIE_CSR Function Control Register */
 31#define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA		(BIT(0))
 32#define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT		(BIT(6))
 33#define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT		(BIT(7))
 34#define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS	(BIT(20))
 35
 36#define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ	(BIT(21))
 37/* Stop MAC Access disconnection request */
 38#define BTINTEL_PCIE_CSR_FUNC_CTRL_STOP_MAC_ACCESS_DIS	(BIT(22))
 39#define BTINTEL_PCIE_CSR_FUNC_CTRL_XTAL_CLK_REQ		(BIT(23))
 40
 41#define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_STS	(BIT(28))
 42#define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_DISCON	(BIT(29))
 43#define BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET		(BIT(31))
 44
 45/* Value for BTINTEL_PCIE_CSR_BOOT_STAGE register */
 46#define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM		(BIT(0))
 47#define BTINTEL_PCIE_CSR_BOOT_STAGE_IML		(BIT(1))
 48#define BTINTEL_PCIE_CSR_BOOT_STAGE_OPFW		(BIT(2))
 49#define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM_LOCKDOWN	(BIT(10))
 50#define BTINTEL_PCIE_CSR_BOOT_STAGE_IML_LOCKDOWN	(BIT(11))
 51#define BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_ERR		(BIT(12))
 52#define BTINTEL_PCIE_CSR_BOOT_STAGE_ABORT_HANDLER	(BIT(13))
 53#define BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_HALTED	(BIT(14))
 54#define BTINTEL_PCIE_CSR_BOOT_STAGE_MAC_ACCESS_ON	(BIT(16))
 55#define BTINTEL_PCIE_CSR_BOOT_STAGE_ALIVE		(BIT(23))
 56#define BTINTEL_PCIE_CSR_BOOT_STAGE_D3_STATE_READY	(BIT(24))
 57
 58/* Registers for MSI-X */
 59#define BTINTEL_PCIE_CSR_MSIX_BASE		(0x2000)
 60#define BTINTEL_PCIE_CSR_MSIX_FH_INT_CAUSES	(BTINTEL_PCIE_CSR_MSIX_BASE + 0x0800)
 61#define BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK	(BTINTEL_PCIE_CSR_MSIX_BASE + 0x0804)
 62#define BTINTEL_PCIE_CSR_MSIX_HW_INT_CAUSES	(BTINTEL_PCIE_CSR_MSIX_BASE + 0x0808)
 63#define BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK	(BTINTEL_PCIE_CSR_MSIX_BASE + 0x080C)
 64#define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_ST	(BTINTEL_PCIE_CSR_MSIX_BASE + 0x0810)
 65#define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_EN	(BTINTEL_PCIE_CSR_MSIX_BASE + 0x0814)
 66#define BTINTEL_PCIE_CSR_MSIX_IVAR_BASE		(BTINTEL_PCIE_CSR_MSIX_BASE + 0x0880)
 67#define BTINTEL_PCIE_CSR_MSIX_IVAR(cause)	(BTINTEL_PCIE_CSR_MSIX_IVAR_BASE + (cause))
 68
 69/* IOSF Debug Register */
 70#define BTINTEL_PCIE_DBGC_BASE_ADDR			(0xf3800300)
 71#define BTINTEL_PCIE_DBGC_CUR_DBGBUFF_STATUS		(BTINTEL_PCIE_DBGC_BASE_ADDR + 0x1C)
 72#define BTINTEL_PCIE_DBGC_DBGBUFF_WRAP_ARND		(BTINTEL_PCIE_DBGC_BASE_ADDR + 0x2C)
 73
 74#define BTINTEL_PCIE_DBG_IDX_BIT_MASK		0x0F
 75#define BTINTEL_PCIE_DBGC_DBG_BUF_IDX(data)	(((data) >> 24) & BTINTEL_PCIE_DBG_IDX_BIT_MASK)
 76#define BTINTEL_PCIE_DBG_OFFSET_BIT_MASK	0xFFFFFF
 77
 78/* The DRAM buffer count, each buffer size, and
 79 * fragment buffer size
 80 */
 81#define BTINTEL_PCIE_DBGC_BUFFER_COUNT		16
 82#define BTINTEL_PCIE_DBGC_BUFFER_SIZE		(256 * 1024) /* 256 KB */
 83
 84#define BTINTEL_PCIE_DBGC_FRAG_VERSION		1
 85#define BTINTEL_PCIE_DBGC_FRAG_BUFFER_COUNT	BTINTEL_PCIE_DBGC_BUFFER_COUNT
 86
 87/* Magic number(4), version(4), size of payload length(4) */
 88#define BTINTEL_PCIE_DBGC_FRAG_HEADER_SIZE	12
 89
 90/* Num of alloc Dbg buff (4) + (LSB(4), MSB(4), Size(4)) for each buffer */
 91#define BTINTEL_PCIE_DBGC_FRAG_PAYLOAD_SIZE	196
 92
 93/* Causes for the FH register interrupts */
 94enum msix_fh_int_causes {
 95	BTINTEL_PCIE_MSIX_FH_INT_CAUSES_0	= BIT(0),	/* cause 0 */
 96	BTINTEL_PCIE_MSIX_FH_INT_CAUSES_1	= BIT(1),	/* cause 1 */
 97};
 98
 99/* Causes for the HW register interrupts */
100enum msix_hw_int_causes {
101	BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0	= BIT(0),	/* cause 32 */
102	BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP1	= BIT(1),	/* cause 33 */
103	BTINTEL_PCIE_MSIX_HW_INT_CAUSES_HWEXP	= BIT(3),	/* cause 35 */
104};
105
106/* PCIe device states
107 * Host-Device interface is active
108 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
109 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
110 */
111enum {
112	BTINTEL_PCIE_STATE_D0 = 0,
113	BTINTEL_PCIE_STATE_D3_HOT = 2,
114	BTINTEL_PCIE_STATE_D3_COLD = 3,
115};
116
117enum {
118	BTINTEL_PCIE_CORE_HALTED,
119	BTINTEL_PCIE_HWEXP_INPROGRESS,
120	BTINTEL_PCIE_COREDUMP_INPROGRESS,
121	BTINTEL_PCIE_RECOVERY_IN_PROGRESS,
122	BTINTEL_PCIE_SETUP_DONE
123};
124
125enum btintel_pcie_tlv_type {
126	BTINTEL_CNVI_BT,
127	BTINTEL_WRITE_PTR,
128	BTINTEL_WRAP_CTR,
129	BTINTEL_TRIGGER_REASON,
130	BTINTEL_FW_SHA,
131	BTINTEL_CNVR_TOP,
132	BTINTEL_CNVI_TOP,
133	BTINTEL_DUMP_TIME,
134	BTINTEL_FW_BUILD,
135	BTINTEL_VENDOR,
136	BTINTEL_DRIVER
137};
138
139/* causes for the MBOX interrupts */
140enum msix_mbox_int_causes {
141	BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX1 = BIT(0), /* cause MBOX1 */
142	BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX2 = BIT(1), /* cause MBOX2 */
143	BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX3 = BIT(2), /* cause MBOX3 */
144	BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX4 = BIT(3), /* cause MBOX4 */
145};
146
147#define BTINTEL_PCIE_MSIX_NON_AUTO_CLEAR_CAUSE	BIT(7)
148
149/* Minimum and Maximum number of MSI-X Vector
150 * Intel Bluetooth PCIe support only 1 vector
151 */
152#define BTINTEL_PCIE_MSIX_VEC_MAX	1
153#define BTINTEL_PCIE_MSIX_VEC_MIN	1
154
155/* Default poll time for MAC access during init */
156#define BTINTEL_DEFAULT_MAC_ACCESS_TIMEOUT_US	200000
157
158/* Default interrupt timeout in msec */
159#define BTINTEL_DEFAULT_INTR_TIMEOUT_MS	3000
160
161#define BTINTEL_PCIE_DX_TRANSITION_MAX_RETRIES	3
162
163/* The number of descriptors in TX queues */
164#define BTINTEL_PCIE_TX_DESCS_COUNT	32
165
166/* The number of descriptors in RX queues */
167#define BTINTEL_PCIE_RX_DESCS_COUNT	64
168
169/* Number of Queue for TX and RX
170 * It indicates the index of the IA(Index Array)
171 */
172enum {
173	BTINTEL_PCIE_TXQ_NUM = 0,
174	BTINTEL_PCIE_RXQ_NUM = 1,
175	BTINTEL_PCIE_NUM_QUEUES = 2,
176};
177
178/* The size of DMA buffer for TX and RX in bytes */
179#define BTINTEL_PCIE_BUFFER_SIZE	4096
180
181/* DMA allocation alignment */
182#define BTINTEL_PCIE_DMA_POOL_ALIGNMENT	256
183
184#define BTINTEL_PCIE_TX_WAIT_TIMEOUT_MS		500
185
186/* Doorbell vector for TFD */
187#define BTINTEL_PCIE_TX_DB_VEC	0
188
189/* Doorbell vector for FRBD */
190#define BTINTEL_PCIE_RX_DB_VEC	513
191
192/* RBD buffer size mapping */
193#define BTINTEL_PCIE_RBD_SIZE_4K	0x04
194
195/*
196 * Struct for Context Information (v2)
197 *
198 * All members are write-only for host and read-only for device.
199 *
200 * @version: Version of context information
201 * @size: Size of context information
202 * @config: Config with which host wants peripheral to execute
203 *	Subset of capability register published by device
204 * @addr_tr_hia: Address of TR Head Index Array
205 * @addr_tr_tia: Address of TR Tail Index Array
206 * @addr_cr_hia: Address of CR Head Index Array
207 * @addr_cr_tia: Address of CR Tail Index Array
208 * @num_tr_ia: Number of entries in TR Index Arrays
209 * @num_cr_ia: Number of entries in CR Index Arrays
210 * @rbd_siz: RBD Size { 0x4=4K }
211 * @addr_tfdq: Address of TFD Queue(tx)
212 * @addr_urbdq0: Address of URBD Queue(tx)
213 * @num_tfdq: Number of TFD in TFD Queue(tx)
214 * @num_urbdq0: Number of URBD in URBD Queue(tx)
215 * @tfdq_db_vec: Queue number of TFD
216 * @urbdq0_db_vec: Queue number of URBD
217 * @addr_frbdq: Address of FRBD Queue(rx)
218 * @addr_urbdq1: Address of URBD Queue(rx)
219 * @num_frbdq: Number of FRBD in FRBD Queue(rx)
220 * @frbdq_db_vec: Queue number of FRBD
221 * @num_urbdq1: Number of URBD in URBD Queue(rx)
222 * @urbdq_db_vec: Queue number of URBDQ1
223 * @tr_msi_vec: Transfer Ring MSI-X Vector
224 * @cr_msi_vec: Completion Ring MSI-X Vector
225 * @dbgc_addr: DBGC first fragment address
226 * @dbgc_size: DBGC buffer size
227 * @early_enable: Enarly debug enable
228 * @dbg_output_mode: Debug output mode
229 *	Bit[4] DBGC O/P { 0=SRAM, 1=DRAM(not relevant for NPK) }
230 *	Bit[5] DBGC I/P { 0=BDBG, 1=DBGI }
231 *	Bits[6:7] DBGI O/P(relevant if bit[5] = 1)
232 *	 0=BT DBGC, 1=WiFi DBGC, 2=NPK }
233 * @dbg_preset: Debug preset
234 * @ext_addr: Address of context information extension
235 * @ext_size: Size of context information part
236 *
237 * Total 38 DWords
238 */
239struct ctx_info {
240	u16	version;
241	u16	size;
242	u32	config;
243	u32	reserved_dw02;
244	u32	reserved_dw03;
245	u64	addr_tr_hia;
246	u64	addr_tr_tia;
247	u64	addr_cr_hia;
248	u64	addr_cr_tia;
249	u16	num_tr_ia;
250	u16	num_cr_ia;
251	u32	rbd_size:4,
252		reserved_dw13:28;
253	u64	addr_tfdq;
254	u64	addr_urbdq0;
255	u16	num_tfdq;
256	u16	num_urbdq0;
257	u16	tfdq_db_vec;
258	u16	urbdq0_db_vec;
259	u64	addr_frbdq;
260	u64	addr_urbdq1;
261	u16	num_frbdq;
262	u16	frbdq_db_vec;
263	u16	num_urbdq1;
264	u16	urbdq_db_vec;
265	u16	tr_msi_vec;
266	u16	cr_msi_vec;
267	u32	reserved_dw27;
268	u64	dbgc_addr;
269	u32	dbgc_size;
270	u32	early_enable:1,
271		reserved_dw31:3,
272		dbg_output_mode:4,
273		dbg_preset:8,
274		reserved2_dw31:16;
275	u64	ext_addr;
276	u32	ext_size;
277	u32	test_param;
278	u32	reserved_dw36;
279	u32	reserved_dw37;
280} __packed;
281
282/* Transfer Descriptor for TX
283 * @type: Not in use. Set to 0x0
284 * @size: Size of data in the buffer
285 * @addr: DMA Address of buffer
286 */
287struct tfd {
288	u8	type;
289	u16	size;
290	u8	reserved;
291	u64	addr;
292	u32	reserved1;
293} __packed;
294
295/* URB Descriptor for TX
296 * @tfd_index: Index of TFD in TFDQ + 1
297 * @num_txq: Queue index of TFD Queue
298 * @cmpl_count: Completion count. Always 0x01
299 * @immediate_cmpl: Immediate completion flag: Always 0x01
300 */
301struct urbd0 {
302	u32	tfd_index:16,
303		num_txq:8,
304		cmpl_count:4,
305		reserved:3,
306		immediate_cmpl:1;
307} __packed;
308
309/* FRB Descriptor for RX
310 * @tag: RX buffer tag (index of RX buffer queue)
311 * @addr: Address of buffer
312 */
313struct frbd {
314	u32	tag:16,
315		reserved:16;
316	u32	reserved2;
317	u64	addr;
318} __packed;
319
320/* URB Descriptor for RX
321 * @frbd_tag: Tag from FRBD
322 * @status: Status
323 */
324struct urbd1 {
325	u32	frbd_tag:16,
326		status:1,
327		reserved:14,
328		fixed:1;
329} __packed;
330
331/* RFH header in RX packet
332 * @packet_len: Length of the data in the buffer
333 * @rxq: RX Queue number
334 * @cmd_id: Command ID. Not in Use
335 */
336struct rfh_hdr {
337	u64	packet_len:16,
338		rxq:6,
339		reserved:10,
340		cmd_id:16,
341		reserved1:16;
342} __packed;
343
344/* Internal data buffer
345 * @data: pointer to the data buffer
346 * @p_addr: physical address of data buffer
347 */
348struct data_buf {
349	u8		*data;
350	dma_addr_t	data_p_addr;
351};
352
353/* Index Array */
354struct ia {
355	dma_addr_t	tr_hia_p_addr;
356	u16		*tr_hia;
357	dma_addr_t	tr_tia_p_addr;
358	u16		*tr_tia;
359	dma_addr_t	cr_hia_p_addr;
360	u16		*cr_hia;
361	dma_addr_t	cr_tia_p_addr;
362	u16		*cr_tia;
363};
364
365/* Structure for TX Queue
366 * @count: Number of descriptors
367 * @tfds: Array of TFD
368 * @urbd0s: Array of URBD0
369 * @buf: Array of data_buf structure
370 */
371struct txq {
372	u16		count;
373
374	dma_addr_t	tfds_p_addr;
375	struct tfd	*tfds;
376
377	dma_addr_t	urbd0s_p_addr;
378	struct urbd0	*urbd0s;
379
380	dma_addr_t	buf_p_addr;
381	void		*buf_v_addr;
382	struct data_buf	*bufs;
383};
384
385/* Structure for RX Queue
386 * @count: Number of descriptors
387 * @frbds: Array of FRBD
388 * @urbd1s: Array of URBD1
389 * @buf: Array of data_buf structure
390 */
391struct rxq {
392	u16		count;
393
394	dma_addr_t	frbds_p_addr;
395	struct frbd	*frbds;
396
397	dma_addr_t	urbd1s_p_addr;
398	struct urbd1	*urbd1s;
399
400	dma_addr_t	buf_p_addr;
401	void		*buf_v_addr;
402	struct data_buf	*bufs;
403};
404
405/* Structure for DRAM Buffer
406 * @count: Number of descriptors
407 * @buf: Array of data_buf structure
408 */
409struct btintel_pcie_dbgc {
410	u16		count;
411
412	void		*frag_v_addr;
413	dma_addr_t	frag_p_addr;
414	u16		frag_size;
415
416	dma_addr_t	buf_p_addr;
417	void		*buf_v_addr;
418	struct data_buf *bufs;
419};
420
421struct btintel_pcie_dump_header {
422	const char	*driver_name;
423	u32		cnvi_top;
424	u32		cnvr_top;
425	u16		fw_timestamp;
426	u8		fw_build_type;
427	u32		fw_build_num;
428	u32		fw_git_sha1;
429	u32		cnvi_bt;
430	u32		write_ptr;
431	u32		wrap_ctr;
432	u16		trigger_reason;
433	int		state;
434};
435
436/* struct btintel_pcie_data
437 * @pdev: pci device
438 * @hdev: hdev device
439 * @flags: driver state
440 * @irq_lock: spinlock for MSI-X
441 * @hci_rx_lock: spinlock for HCI RX flow
442 * @base_addr: pci base address (from BAR)
443 * @msix_entries: array of MSI-X entries
444 * @msix_enabled: true if MSI-X is enabled;
445 * @alloc_vecs: number of interrupt vectors allocated
446 * @def_irq: default irq for all causes
447 * @fh_init_mask: initial unmasked rxq causes
448 * @hw_init_mask: initial unmaksed hw causes
449 * @boot_stage_cache: cached value of boot stage register
450 * @img_resp_cache: cached value of image response register
451 * @cnvi: CNVi register value
452 * @cnvr: CNVr register value
453 * @gp0_received: condition for gp0 interrupt
454 * @gp0_wait_q: wait_q for gp0 interrupt
455 * @tx_wait_done: condition for tx interrupt
456 * @tx_wait_q: wait_q for tx interrupt
457 * @workqueue: workqueue for RX work
458 * @rx_skb_q: SKB queue for RX packet
459 * @rx_work: RX work struct to process the RX packet in @rx_skb_q
460 * @dma_pool: DMA pool for descriptors, index array and ci
461 * @dma_p_addr: DMA address for pool
462 * @dma_v_addr: address of pool
463 * @ci_p_addr: DMA address for CI struct
464 * @ci: CI struct
465 * @ia: Index Array struct
466 * @txq: TX Queue struct
467 * @rxq: RX Queue struct
468 * @alive_intr_ctxt: Alive interrupt context
469 * @pm_sx_event: PM event on which system got suspended
470 */
471struct btintel_pcie_data {
472	struct pci_dev	*pdev;
473	struct hci_dev	*hdev;
474
475	unsigned long	flags;
476	/* lock used in MSI-X interrupt */
477	spinlock_t	irq_lock;
478	/* lock to serialize rx events */
479	spinlock_t	hci_rx_lock;
480
481	void __iomem	*base_addr;
482
483	struct msix_entry	msix_entries[BTINTEL_PCIE_MSIX_VEC_MAX];
484	bool	msix_enabled;
485	u32	alloc_vecs;
486	u32	def_irq;
487
488	u32	fh_init_mask;
489	u32	hw_init_mask;
490
491	u32	boot_stage_cache;
492	u32	img_resp_cache;
493
494	u32	cnvi;
495	u32	cnvr;
496
497	bool	gp0_received;
498	wait_queue_head_t	gp0_wait_q;
499
500	bool	tx_wait_done;
501	wait_queue_head_t	tx_wait_q;
502
503	struct workqueue_struct	*workqueue;
504	struct sk_buff_head	rx_skb_q;
505	struct work_struct	rx_work;
506
507	struct dma_pool	*dma_pool;
508	dma_addr_t	dma_p_addr;
509	void		*dma_v_addr;
510
511	dma_addr_t	ci_p_addr;
512	struct ctx_info	*ci;
513	struct ia	ia;
514	struct txq	txq;
515	struct rxq	rxq;
516	u32	alive_intr_ctxt;
517	struct btintel_pcie_dbgc	dbgc;
518	struct btintel_pcie_dump_header dmp_hdr;
519	u8	pm_sx_event;
520};
521
522static inline u32 btintel_pcie_rd_reg32(struct btintel_pcie_data *data,
523					u32 offset)
524{
525	return ioread32(data->base_addr + offset);
526}
527
528static inline void btintel_pcie_wr_reg8(struct btintel_pcie_data *data,
529					u32 offset, u8 val)
530{
531	iowrite8(val, data->base_addr + offset);
532}
533
534static inline void btintel_pcie_wr_reg32(struct btintel_pcie_data *data,
535					 u32 offset, u32 val)
536{
537	iowrite32(val, data->base_addr + offset);
538}
539
540static inline void btintel_pcie_set_reg_bits(struct btintel_pcie_data *data,
541					     u32 offset, u32 bits)
542{
543	u32 r;
544
545	r = ioread32(data->base_addr + offset);
546	r |= bits;
547	iowrite32(r, data->base_addr + offset);
548}
549
550static inline void btintel_pcie_clr_reg_bits(struct btintel_pcie_data *data,
551					     u32 offset, u32 bits)
552{
553	u32 r;
554
555	r = ioread32(data->base_addr + offset);
556	r &= ~bits;
557	iowrite32(r, data->base_addr + offset);
558}
559
560static inline u32 btintel_pcie_rd_dev_mem(struct btintel_pcie_data *data,
561					  u32 addr)
562{
563	btintel_pcie_wr_reg32(data, BTINTEL_PCIE_PRPH_DEV_ADDR_REG, addr);
564	return btintel_pcie_rd_reg32(data, BTINTEL_PCIE_PRPH_DEV_RD_REG);
565}
566