pata_it821x.c

  1/*
  2 * pata_it821x.c 	- IT821x PATA for new ATA layer
  3 *			  (C) 2005 Red Hat Inc
  4 *			  Alan Cox <alan@lxorguk.ukuu.org.uk>
  5 *			  (C) 2007 Bartlomiej Zolnierkiewicz
  6 *
  7 * based upon
  8 *
  9 * it821x.c
 10 *
 11 * linux/drivers/ide/pci/it821x.c		Version 0.09	December 2004
 12 *
 13 * Copyright (C) 2004		Red Hat
 14 *
 15 *  May be copied or modified under the terms of the GNU General Public License
 16 *  Based in part on the ITE vendor provided SCSI driver.
 17 *
 18 *  Documentation available from IT8212F_V04.pdf
 19 * 	http://www.ite.com.tw/EN/products_more.aspx?CategoryID=3&ID=5,91
 20 *  Some other documents are NDA.
 21 *
 22 *  The ITE8212 isn't exactly a standard IDE controller. It has two
 23 *  modes. In pass through mode then it is an IDE controller. In its smart
 24 *  mode its actually quite a capable hardware raid controller disguised
 25 *  as an IDE controller. Smart mode only understands DMA read/write and
 26 *  identify, none of the fancier commands apply. The IT8211 is identical
 27 *  in other respects but lacks the raid mode.
 28 *
 29 *  Errata:
 30 *  o	Rev 0x10 also requires master/slave hold the same DMA timings and
 31 *	cannot do ATAPI MWDMA.
 32 *  o	The identify data for raid volumes lacks CHS info (technically ok)
 33 *	but also fails to set the LBA28 and other bits. We fix these in
 34 *	the IDE probe quirk code.
 35 *  o	If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
 36 *	raid then the controller firmware dies
 37 *  o	Smart mode without RAID doesn't clear all the necessary identify
 38 *	bits to reduce the command set to the one used
 39 *
 40 *  This has a few impacts on the driver
 41 *  - In pass through mode we do all the work you would expect
 42 *  - In smart mode the clocking set up is done by the controller generally
 43 *    but we must watch the other limits and filter.
 44 *  - There are a few extra vendor commands that actually talk to the
 45 *    controller but only work PIO with no IRQ.
 46 *
 47 *  Vendor areas of the identify block in smart mode are used for the
 48 *  timing and policy set up. Each HDD in raid mode also has a serial
 49 *  block on the disk. The hardware extra commands are get/set chip status,
 50 *  rebuild, get rebuild status.
 51 *
 52 *  In Linux the driver supports pass through mode as if the device was
 53 *  just another IDE controller. If the smart mode is running then
 54 *  volumes are managed by the controller firmware and each IDE "disk"
 55 *  is a raid volume. Even more cute - the controller can do automated
 56 *  hotplug and rebuild.
 57 *
 58 *  The pass through controller itself is a little demented. It has a
 59 *  flaw that it has a single set of PIO/MWDMA timings per channel so
 60 *  non UDMA devices restrict each others performance. It also has a
 61 *  single clock source per channel so mixed UDMA100/133 performance
 62 *  isn't perfect and we have to pick a clock. Thankfully none of this
 63 *  matters in smart mode. ATAPI DMA is not currently supported.
 64 *
 65 *  It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
 66 *
 67 *  TODO
 68 *	-	ATAPI and other speed filtering
 69 *	-	RAID configuration ioctls
 70 */
 71
 72#include <linux/kernel.h>
 73#include <linux/module.h>
 74#include <linux/pci.h>
 75#include <linux/blkdev.h>
 76#include <linux/delay.h>
 77#include <linux/slab.h>
 78#include <linux/string.h>
 79#include <scsi/scsi_host.h>
 80#include <linux/libata.h>
 81
 82
 83#define DRV_NAME "pata_it821x"
 84#define DRV_VERSION "0.4.2"
 85
 86struct it821x_dev
 87{
 88	unsigned int smart:1,		/* Are we in smart raid mode */
 89		timing10:1;		/* Rev 0x10 */
 90	u8	clock_mode;		/* 0, ATA_50 or ATA_66 */
 91	u8	want[2][2];		/* Mode/Pri log for master slave */
 92	/* We need these for switching the clock when DMA goes on/off
 93	   The high byte is the 66Mhz timing */
 94	u16	pio[2];			/* Cached PIO values */
 95	u16	mwdma[2];		/* Cached MWDMA values */
 96	u16	udma[2];		/* Cached UDMA values (per drive) */
 97	u16	last_device;		/* Master or slave loaded ? */
 98};
 99
100#define ATA_66		0
101#define ATA_50		1
102#define ATA_ANY		2
103
104#define UDMA_OFF	0
105#define MWDMA_OFF	0
106
107/*
108 *	We allow users to force the card into non raid mode without
109 *	flashing the alternative BIOS. This is also necessary right now
110 *	for embedded platforms that cannot run a PC BIOS but are using this
111 *	device.
112 */
113
114static int it8212_noraid;
115
116/**
117 *	it821x_program	-	program the PIO/MWDMA registers
118 *	@ap: ATA port
119 *	@adev: Device to program
120 *	@timing: Timing value (66Mhz in top 8bits, 50 in the low 8)
121 *
122 *	Program the PIO/MWDMA timing for this channel according to the
123 *	current clock. These share the same register so are managed by
124 *	the DMA start/stop sequence as with the old driver.
125 */
126
127static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing)
128{
129	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
130	struct it821x_dev *itdev = ap->private_data;
131	int channel = ap->port_no;
132	u8 conf;
133
134	/* Program PIO/MWDMA timing bits */
135	if (itdev->clock_mode == ATA_66)
136		conf = timing >> 8;
137	else
138		conf = timing & 0xFF;
139	pci_write_config_byte(pdev, 0x54 + 4 * channel, conf);
140}
141
142
143/**
144 *	it821x_program_udma	-	program the UDMA registers
145 *	@ap: ATA port
146 *	@adev: ATA device to update
147 *	@timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz
148 *
149 *	Program the UDMA timing for this drive according to the
150 *	current clock. Handles the dual clocks and also knows about
151 *	the errata on the 0x10 revision. The UDMA errata is partly handled
152 *	here and partly in start_dma.
153 */
154
155static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing)
156{
157	struct it821x_dev *itdev = ap->private_data;
158	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
159	int channel = ap->port_no;
160	int unit = adev->devno;
161	u8 conf;
162
163	/* Program UDMA timing bits */
164	if (itdev->clock_mode == ATA_66)
165		conf = timing >> 8;
166	else
167		conf = timing & 0xFF;
168	if (itdev->timing10 == 0)
169		pci_write_config_byte(pdev, 0x56 + 4 * channel + unit, conf);
170	else {
171		/* Early revision must be programmed for both together */
172		pci_write_config_byte(pdev, 0x56 + 4 * channel, conf);
173		pci_write_config_byte(pdev, 0x56 + 4 * channel + 1, conf);
174	}
175}
176
177/**
178 *	it821x_clock_strategy
179 *	@ap: ATA interface
180 *	@adev: ATA device being updated
181 *
182 *	Select between the 50 and 66Mhz base clocks to get the best
183 *	results for this interface.
184 */
185
186static void it821x_clock_strategy(struct ata_port *ap, struct ata_device *adev)
187{
188	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
189	struct it821x_dev *itdev = ap->private_data;
190	u8 unit = adev->devno;
191	struct ata_device *pair = ata_dev_pair(adev);
192
193	int clock, altclock;
194	u8 v;
195	int sel = 0;
196
197	/* Look for the most wanted clocking */
198	if (itdev->want[0][0] > itdev->want[1][0]) {
199		clock = itdev->want[0][1];
200		altclock = itdev->want[1][1];
201	} else {
202		clock = itdev->want[1][1];
203		altclock = itdev->want[0][1];
204	}
205
206	/* Master doesn't care does the slave ? */
207	if (clock == ATA_ANY)
208		clock = altclock;
209
210	/* Nobody cares - keep the same clock */
211	if (clock == ATA_ANY)
212		return;
213	/* No change */
214	if (clock == itdev->clock_mode)
215		return;
216
217	/* Load this into the controller */
218	if (clock == ATA_66)
219		itdev->clock_mode = ATA_66;
220	else {
221		itdev->clock_mode = ATA_50;
222		sel = 1;
223	}
224	pci_read_config_byte(pdev, 0x50, &v);
225	v &= ~(1 << (1 + ap->port_no));
226	v |= sel << (1 + ap->port_no);
227	pci_write_config_byte(pdev, 0x50, v);
228
229	/*
230	 *	Reprogram the UDMA/PIO of the pair drive for the switch
231	 *	MWDMA will be dealt with by the dma switcher
232	 */
233	if (pair && itdev->udma[1-unit] != UDMA_OFF) {
234		it821x_program_udma(ap, pair, itdev->udma[1-unit]);
235		it821x_program(ap, pair, itdev->pio[1-unit]);
236	}
237	/*
238	 *	Reprogram the UDMA/PIO of our drive for the switch.
239	 *	MWDMA will be dealt with by the dma switcher
240	 */
241	if (itdev->udma[unit] != UDMA_OFF) {
242		it821x_program_udma(ap, adev, itdev->udma[unit]);
243		it821x_program(ap, adev, itdev->pio[unit]);
244	}
245}
246
247/**
248 *	it821x_passthru_set_piomode	-	set PIO mode data
249 *	@ap: ATA interface
250 *	@adev: ATA device
251 *
252 *	Configure for PIO mode. This is complicated as the register is
253 *	shared by PIO and MWDMA and for both channels.
254 */
255
256static void it821x_passthru_set_piomode(struct ata_port *ap, struct ata_device *adev)
257{
258	/* Spec says 89 ref driver uses 88 */
259	static const u16 pio[]	= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
260	static const u8 pio_want[]    = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
261
262	struct it821x_dev *itdev = ap->private_data;
263	int unit = adev->devno;
264	int mode_wanted = adev->pio_mode - XFER_PIO_0;
265
266	/* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
267	itdev->want[unit][1] = pio_want[mode_wanted];
268	itdev->want[unit][0] = 1;	/* PIO is lowest priority */
269	itdev->pio[unit] = pio[mode_wanted];
270	it821x_clock_strategy(ap, adev);
271	it821x_program(ap, adev, itdev->pio[unit]);
272}
273
274/**
275 *	it821x_passthru_set_dmamode	-	set initial DMA mode data
276 *	@ap: ATA interface
277 *	@adev: ATA device
278 *
279 *	Set up the DMA modes. The actions taken depend heavily on the mode
280 *	to use. If UDMA is used as is hopefully the usual case then the
281 *	timing register is private and we need only consider the clock. If
282 *	we are using MWDMA then we have to manage the setting ourself as
283 *	we switch devices and mode.
284 */
285
286static void it821x_passthru_set_dmamode(struct ata_port *ap, struct ata_device *adev)
287{
288	static const u16 dma[]	= 	{ 0x8866, 0x3222, 0x3121 };
289	static const u8 mwdma_want[] =  { ATA_ANY, ATA_66, ATA_ANY };
290	static const u16 udma[]	= 	{ 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
291	static const u8 udma_want[] =   { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
292
293	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
294	struct it821x_dev *itdev = ap->private_data;
295	int channel = ap->port_no;
296	int unit = adev->devno;
297	u8 conf;
298
299	if (adev->dma_mode >= XFER_UDMA_0) {
300		int mode_wanted = adev->dma_mode - XFER_UDMA_0;
301
302		itdev->want[unit][1] = udma_want[mode_wanted];
303		itdev->want[unit][0] = 3;	/* UDMA is high priority */
304		itdev->mwdma[unit] = MWDMA_OFF;
305		itdev->udma[unit] = udma[mode_wanted];
306		if (mode_wanted >= 5)
307			itdev->udma[unit] |= 0x8080;	/* UDMA 5/6 select on */
308
309		/* UDMA on. Again revision 0x10 must do the pair */
310		pci_read_config_byte(pdev, 0x50, &conf);
311		if (itdev->timing10)
312			conf &= channel ? 0x9F: 0xE7;
313		else
314			conf &= ~ (1 << (3 + 2 * channel + unit));
315		pci_write_config_byte(pdev, 0x50, conf);
316		it821x_clock_strategy(ap, adev);
317		it821x_program_udma(ap, adev, itdev->udma[unit]);
318	} else {
319		int mode_wanted = adev->dma_mode - XFER_MW_DMA_0;
320
321		itdev->want[unit][1] = mwdma_want[mode_wanted];
322		itdev->want[unit][0] = 2;	/* MWDMA is low priority */
323		itdev->mwdma[unit] = dma[mode_wanted];
324		itdev->udma[unit] = UDMA_OFF;
325
326		/* UDMA bits off - Revision 0x10 do them in pairs */
327		pci_read_config_byte(pdev, 0x50, &conf);
328		if (itdev->timing10)
329			conf |= channel ? 0x60: 0x18;
330		else
331			conf |= 1 << (3 + 2 * channel + unit);
332		pci_write_config_byte(pdev, 0x50, conf);
333		it821x_clock_strategy(ap, adev);
334	}
335}
336
337/**
338 *	it821x_passthru_bmdma_start	-	DMA start callback
339 *	@qc: Command in progress
340 *
341 *	Usually drivers set the DMA timing at the point the set_dmamode call
342 *	is made. IT821x however requires we load new timings on the
343 *	transitions in some cases.
344 */
345
346static void it821x_passthru_bmdma_start(struct ata_queued_cmd *qc)
347{
348	struct ata_port *ap = qc->ap;
349	struct ata_device *adev = qc->dev;
350	struct it821x_dev *itdev = ap->private_data;
351	int unit = adev->devno;
352
353	if (itdev->mwdma[unit] != MWDMA_OFF)
354		it821x_program(ap, adev, itdev->mwdma[unit]);
355	else if (itdev->udma[unit] != UDMA_OFF && itdev->timing10)
356		it821x_program_udma(ap, adev, itdev->udma[unit]);
357	ata_bmdma_start(qc);
358}
359
360/**
361 *	it821x_passthru_bmdma_stop	-	DMA stop callback
362 *	@qc: ATA command
363 *
364 *	We loaded new timings in dma_start, as a result we need to restore
365 *	the PIO timings in dma_stop so that the next command issue gets the
366 *	right clock values.
367 */
368
369static void it821x_passthru_bmdma_stop(struct ata_queued_cmd *qc)
370{
371	struct ata_port *ap = qc->ap;
372	struct ata_device *adev = qc->dev;
373	struct it821x_dev *itdev = ap->private_data;
374	int unit = adev->devno;
375
376	ata_bmdma_stop(qc);
377	if (itdev->mwdma[unit] != MWDMA_OFF)
378		it821x_program(ap, adev, itdev->pio[unit]);
379}
380
381
382/**
383 *	it821x_passthru_dev_select	-	Select master/slave
384 *	@ap: ATA port
385 *	@device: Device number (not pointer)
386 *
387 *	Device selection hook. If necessary perform clock switching
388 */
389
390static void it821x_passthru_dev_select(struct ata_port *ap,
391				       unsigned int device)
392{
393	struct it821x_dev *itdev = ap->private_data;
394	if (itdev && device != itdev->last_device) {
395		struct ata_device *adev = &ap->link.device[device];
396		it821x_program(ap, adev, itdev->pio[adev->devno]);
397		itdev->last_device = device;
398	}
399	ata_sff_dev_select(ap, device);
400}
401
402/**
403 *	it821x_smart_qc_issue		-	wrap qc issue prot
404 *	@qc: command
405 *
406 *	Wrap the command issue sequence for the IT821x. We need to
407 *	perform out own device selection timing loads before the
408 *	usual happenings kick off
409 */
410
411static unsigned int it821x_smart_qc_issue(struct ata_queued_cmd *qc)
412{
413	switch(qc->tf.command)
414	{
415		/* Commands the firmware supports */
416		case ATA_CMD_READ:
417		case ATA_CMD_READ_EXT:
418		case ATA_CMD_WRITE:
419		case ATA_CMD_WRITE_EXT:
420		case ATA_CMD_PIO_READ:
421		case ATA_CMD_PIO_READ_EXT:
422		case ATA_CMD_PIO_WRITE:
423		case ATA_CMD_PIO_WRITE_EXT:
424		case ATA_CMD_READ_MULTI:
425		case ATA_CMD_READ_MULTI_EXT:
426		case ATA_CMD_WRITE_MULTI:
427		case ATA_CMD_WRITE_MULTI_EXT:
428		case ATA_CMD_ID_ATA:
429		case ATA_CMD_INIT_DEV_PARAMS:
430		case 0xFC:	/* Internal 'report rebuild state' */
431		/* Arguably should just no-op this one */
432		case ATA_CMD_SET_FEATURES:
433			return ata_bmdma_qc_issue(qc);
434	}
435	ata_dev_dbg(qc->dev, "it821x: can't process command 0x%02X\n",
436		    qc->tf.command);
437	return AC_ERR_DEV;
438}
439
440/**
441 *	it821x_passthru_qc_issue	-	wrap qc issue prot
442 *	@qc: command
443 *
444 *	Wrap the command issue sequence for the IT821x. We need to
445 *	perform out own device selection timing loads before the
446 *	usual happenings kick off
447 */
448
449static unsigned int it821x_passthru_qc_issue(struct ata_queued_cmd *qc)
450{
451	it821x_passthru_dev_select(qc->ap, qc->dev->devno);
452	return ata_bmdma_qc_issue(qc);
453}
454
455/**
456 *	it821x_smart_set_mode	-	mode setting
457 *	@link: interface to set up
458 *	@unused: device that failed (error only)
459 *
460 *	Use a non standard set_mode function. We don't want to be tuned.
461 *	The BIOS configured everything. Our job is not to fiddle. We
462 *	read the dma enabled bits from the PCI configuration of the device
463 *	and respect them.
464 */
465
466static int it821x_smart_set_mode(struct ata_link *link, struct ata_device **unused)
467{
468	struct ata_device *dev;
469
470	ata_for_each_dev(dev, link, ENABLED) {
471		/* We don't really care */
472		dev->pio_mode = XFER_PIO_0;
473		dev->dma_mode = XFER_MW_DMA_0;
474		/* We do need the right mode information for DMA or PIO
475		   and this comes from the current configuration flags */
476		if (ata_id_has_dma(dev->id)) {
477			ata_dev_info(dev, "configured for DMA\n");
478			dev->xfer_mode = XFER_MW_DMA_0;
479			dev->xfer_shift = ATA_SHIFT_MWDMA;
480			dev->flags &= ~ATA_DFLAG_PIO;
481		} else {
482			ata_dev_info(dev, "configured for PIO\n");
483			dev->xfer_mode = XFER_PIO_0;
484			dev->xfer_shift = ATA_SHIFT_PIO;
485			dev->flags |= ATA_DFLAG_PIO;
486		}
487	}
488	return 0;
489}
490
491/**
492 *	it821x_dev_config	-	Called each device identify
493 *	@adev: Device that has just been identified
494 *
495 *	Perform the initial setup needed for each device that is chip
496 *	special. In our case we need to lock the sector count to avoid
497 *	blowing the brains out of the firmware with large LBA48 requests
498 *
499 */
500
501static void it821x_dev_config(struct ata_device *adev)
502{
503	unsigned char model_num[ATA_ID_PROD_LEN + 1];
504
505	ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
506
507	if (adev->max_sectors > 255)
508		adev->max_sectors = 255;
509
510	if (strstr(model_num, "Integrated Technology Express")) {
511		/* RAID mode */
512		if (adev->id[129] == 1)
513			ata_dev_info(adev, "%sRAID%d volume\n",
514				     adev->id[147] ? "Bootable " : "",
515				     adev->id[129]);
516		else
517			ata_dev_info(adev, "%sRAID%d volume (%dK stripe)\n",
518				     adev->id[147] ? "Bootable " : "",
519				     adev->id[129], adev->id[146]);
520	}
521	/* This is a controller firmware triggered funny, don't
522	   report the drive faulty! */
523	adev->quirks &= ~ATA_QUIRK_DIAGNOSTIC;
524	/* No HPA in 'smart' mode */
525	adev->quirks |= ATA_QUIRK_BROKEN_HPA;
526}
527
528/**
529 *	it821x_read_id	-	Hack identify data up
530 *	@adev: device to read
531 *	@tf: proposed taskfile
532 *	@id: buffer for returned ident data
533 *
534 *	Query the devices on this firmware driven port and slightly
535 *	mash the identify data to stop us and common tools trying to
536 *	use features not firmware supported. The firmware itself does
537 *	some masking (eg SMART) but not enough.
538 */
539
540static unsigned int it821x_read_id(struct ata_device *adev,
541				   struct ata_taskfile *tf, __le16 *id)
542{
543	unsigned int err_mask;
544	unsigned char model_num[ATA_ID_PROD_LEN + 1];
545
546	err_mask = ata_do_dev_read_id(adev, tf, id);
547	if (err_mask)
548		return err_mask;
549	ata_id_c_string((u16 *)id, model_num, ATA_ID_PROD, sizeof(model_num));
550
551	id[83] &= cpu_to_le16(~(1 << 12)); /* Cache flush is firmware handled */
552	id[84] &= cpu_to_le16(~(1 << 6));  /* No FUA */
553	id[85] &= cpu_to_le16(~(1 << 10)); /* No HPA */
554	id[76] = 0;			   /* No NCQ/AN etc */
555
556	if (strstr(model_num, "Integrated Technology Express")) {
557		/* Set feature bits the firmware neglects */
558		id[49] |= cpu_to_le16(0x0300);	/* LBA, DMA */
559		id[83] &= cpu_to_le16(0x7FFF);
560		id[83] |= cpu_to_le16(0x4400);	/* Word 83 is valid and LBA48 */
561		id[86] |= cpu_to_le16(0x0400);	/* LBA48 on */
562		id[ATA_ID_MAJOR_VER] |= cpu_to_le16(0x1F);
563		/* Clear the serial number because it's different each boot
564		   which breaks validation on resume */
565		memset(&id[ATA_ID_SERNO], 0x20, ATA_ID_SERNO_LEN);
566	}
567	return err_mask;
568}
569
570/**
571 *	it821x_check_atapi_dma	-	ATAPI DMA handler
572 *	@qc: Command we are about to issue
573 *
574 *	Decide if this ATAPI command can be issued by DMA on this
575 *	controller. Return 0 if it can be.
576 */
577
578static int it821x_check_atapi_dma(struct ata_queued_cmd *qc)
579{
580	struct ata_port *ap = qc->ap;
581	struct it821x_dev *itdev = ap->private_data;
582
583	/* Only use dma for transfers to/from the media. */
584	if (ata_qc_raw_nbytes(qc) < 2048)
585		return -EOPNOTSUPP;
586
587	/* No ATAPI DMA in smart mode */
588	if (itdev->smart)
589		return -EOPNOTSUPP;
590	/* No ATAPI DMA on rev 10 */
591	if (itdev->timing10)
592		return -EOPNOTSUPP;
593	/* Cool */
594	return 0;
595}
596
597/**
598 *	it821x_display_disk	-	display disk setup
599 *	@ap: ATA port
600 *	@n: Device number
601 *	@buf: Buffer block from firmware
602 *
603 *	Produce a nice informative display of the device setup as provided
604 *	by the firmware.
605 */
606
607static void it821x_display_disk(struct ata_port *ap, int n, u8 *buf)
608{
609	unsigned char id[41];
610	int mode = 0;
611	const char *mtype = "";
612	char mbuf[8];
613	const char *cbl = "(40 wire cable)";
614
615	static const char *types[5] = {
616		"RAID0", "RAID1", "RAID 0+1", "JBOD", "DISK"
617	};
618
619	if (buf[52] > 4)	/* No Disk */
620		return;
621
622	ata_id_c_string((u16 *)buf, id, 0, 41);
623
624	if (buf[51]) {
625		mode = ffs(buf[51]);
626		mtype = "UDMA";
627	} else if (buf[49]) {
628		mode = ffs(buf[49]);
629		mtype = "MWDMA";
630	}
631
632	if (buf[76])
633		cbl = "";
634
635	if (mode)
636		snprintf(mbuf, sizeof(mbuf), "%5s%d", mtype, mode - 1);
637	else
638		strscpy(mbuf, "PIO");
639	if (buf[52] == 4)
640		ata_port_info(ap, "%d: %-6s %-8s          %s %s\n",
641				n, mbuf, types[buf[52]], id, cbl);
642	else
643		ata_port_info(ap, "%d: %-6s %-8s Volume: %1d %s %s\n",
644				n, mbuf, types[buf[52]], buf[53], id, cbl);
645	if (buf[125] < 100)
646		ata_port_info(ap, "%d: Rebuilding: %d%%\n", n, buf[125]);
647}
648
649/**
650 *	it821x_firmware_command		-	issue firmware command
651 *	@ap: IT821x port to interrogate
652 *	@cmd: command
653 *	@len: length
654 *
655 *	Issue firmware commands expecting data back from the controller. We
656 *	use this to issue commands that do not go via the normal paths. Other
657 *	commands such as 0xFC can be issued normally.
658 */
659
660static u8 *it821x_firmware_command(struct ata_port *ap, u8 cmd, int len)
661{
662	u8 status;
663	int n = 0;
664	u16 *buf = kmalloc(len, GFP_KERNEL);
665
666	if (!buf)
667		return NULL;
668
669	/* This isn't quite a normal ATA command as we are talking to the
670	   firmware not the drives */
671	ap->ctl |= ATA_NIEN;
672	iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
673	ata_wait_idle(ap);
674	iowrite8(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
675	iowrite8(cmd, ap->ioaddr.command_addr);
676	udelay(1);
677	/* This should be almost immediate but a little paranoia goes a long
678	   way. */
679	while(n++ < 10) {
680		status = ioread8(ap->ioaddr.status_addr);
681		if (status & ATA_ERR) {
682			kfree(buf);
683			ata_port_err(ap, "%s: rejected\n", __func__);
684			return NULL;
685		}
686		if (status & ATA_DRQ) {
687			ioread16_rep(ap->ioaddr.data_addr, buf, len/2);
688			return (u8 *)buf;
689		}
690		usleep_range(500, 1000);
691	}
692	kfree(buf);
693	ata_port_err(ap, "%s: timeout\n", __func__);
694	return NULL;
695}
696
697/**
698 *	it821x_probe_firmware	-	firmware reporting/setup
699 *	@ap: IT821x port being probed
700 *
701 *	Probe the firmware of the controller by issuing firmware command
702 *	0xFA and analysing the returned data.
703 */
704
705static void it821x_probe_firmware(struct ata_port *ap)
706{
707	u8 *buf;
708	int i;
709
710	/* This is a bit ugly as we can't just issue a task file to a device
711	   as this is controller magic */
712
713	buf = it821x_firmware_command(ap, 0xFA, 512);
714
715	if (buf != NULL) {
716		ata_port_info(ap, "pata_it821x: Firmware %02X/%02X/%02X%02X\n",
717				buf[505],
718				buf[506],
719				buf[507],
720				buf[508]);
721		for (i = 0; i < 4; i++)
722			it821x_display_disk(ap, i, buf + 128 * i);
723		kfree(buf);
724	}
725}
726
727
728
729/**
730 *	it821x_port_start	-	port setup
731 *	@ap: ATA port being set up
732 *
733 *	The it821x needs to maintain private data structures and also to
734 *	use the standard PCI interface which lacks support for this
735 *	functionality. We instead set up the private data on the port
736 *	start hook, and tear it down on port stop
737 */
738
739static int it821x_port_start(struct ata_port *ap)
740{
741	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
742	struct it821x_dev *itdev;
743	u8 conf;
744
745	int ret = ata_bmdma_port_start(ap);
746	if (ret < 0)
747		return ret;
748
749	itdev = devm_kzalloc(&pdev->dev, sizeof(struct it821x_dev), GFP_KERNEL);
750	if (itdev == NULL)
751		return -ENOMEM;
752	ap->private_data = itdev;
753
754	pci_read_config_byte(pdev, 0x50, &conf);
755
756	if (conf & 1) {
757		itdev->smart = 1;
758		/* Long I/O's although allowed in LBA48 space cause the
759		   onboard firmware to enter the twighlight zone */
760		/* No ATAPI DMA in this mode either */
761		if (ap->port_no == 0)
762			it821x_probe_firmware(ap);
763	}
764	/* Pull the current clocks from 0x50 */
765	if (conf & (1 << (1 + ap->port_no)))
766		itdev->clock_mode = ATA_50;
767	else
768		itdev->clock_mode = ATA_66;
769
770	itdev->want[0][1] = ATA_ANY;
771	itdev->want[1][1] = ATA_ANY;
772	itdev->last_device = -1;
773
774	if (pdev->revision == 0x10) {
775		itdev->timing10 = 1;
776		/* Need to disable ATAPI DMA for this case */
777		if (!itdev->smart)
778			dev_warn(&pdev->dev,
779				 "Revision 0x10, workarounds activated.\n");
780	}
781
782	return 0;
783}
784
785/**
786 *	it821x_rdc_cable	-	Cable detect for RDC1010
787 *	@ap: port we are checking
788 *
789 *	Return the RDC1010 cable type. Unlike the IT821x we know how to do
790 *	this and can do host side cable detect
791 */
792
793static int it821x_rdc_cable(struct ata_port *ap)
794{
795	u16 r40;
796	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
797
798	pci_read_config_word(pdev, 0x40, &r40);
799	if (r40 & (1 << (2 + ap->port_no)))
800		return ATA_CBL_PATA40;
801	return ATA_CBL_PATA80;
802}
803
804static const struct scsi_host_template it821x_sht = {
805	ATA_BMDMA_SHT(DRV_NAME),
806};
807
808static struct ata_port_operations it821x_smart_port_ops = {
809	.inherits	= &ata_bmdma_port_ops,
810
811	.check_atapi_dma= it821x_check_atapi_dma,
812	.qc_issue	= it821x_smart_qc_issue,
813
814	.cable_detect	= ata_cable_80wire,
815	.set_mode	= it821x_smart_set_mode,
816	.dev_config	= it821x_dev_config,
817	.read_id	= it821x_read_id,
818
819	.port_start	= it821x_port_start,
820};
821
822static struct ata_port_operations it821x_passthru_port_ops = {
823	.inherits	= &ata_bmdma_port_ops,
824
825	.check_atapi_dma= it821x_check_atapi_dma,
826	.sff_dev_select	= it821x_passthru_dev_select,
827	.bmdma_start 	= it821x_passthru_bmdma_start,
828	.bmdma_stop	= it821x_passthru_bmdma_stop,
829	.qc_issue	= it821x_passthru_qc_issue,
830
831	.cable_detect	= ata_cable_unknown,
832	.set_piomode	= it821x_passthru_set_piomode,
833	.set_dmamode	= it821x_passthru_set_dmamode,
834
835	.port_start	= it821x_port_start,
836};
837
838static struct ata_port_operations it821x_rdc_port_ops = {
839	.inherits	= &ata_bmdma_port_ops,
840
841	.check_atapi_dma= it821x_check_atapi_dma,
842	.sff_dev_select	= it821x_passthru_dev_select,
843	.bmdma_start 	= it821x_passthru_bmdma_start,
844	.bmdma_stop	= it821x_passthru_bmdma_stop,
845	.qc_issue	= it821x_passthru_qc_issue,
846
847	.cable_detect	= it821x_rdc_cable,
848	.set_piomode	= it821x_passthru_set_piomode,
849	.set_dmamode	= it821x_passthru_set_dmamode,
850
851	.port_start	= it821x_port_start,
852};
853
854static void it821x_disable_raid(struct pci_dev *pdev)
855{
856	/* Neither the RDC nor the IT8211 */
857	if (pdev->vendor != PCI_VENDOR_ID_ITE ||
858			pdev->device != PCI_DEVICE_ID_ITE_8212)
859			return;
860
861	/* Reset local CPU, and set BIOS not ready */
862	pci_write_config_byte(pdev, 0x5E, 0x01);
863
864	/* Set to bypass mode, and reset PCI bus */
865	pci_write_config_byte(pdev, 0x50, 0x00);
866	pci_write_config_word(pdev, PCI_COMMAND,
867			      PCI_COMMAND_PARITY | PCI_COMMAND_IO |
868			      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
869	pci_write_config_word(pdev, 0x40, 0xA0F3);
870
871	pci_write_config_dword(pdev,0x4C, 0x02040204);
872	pci_write_config_byte(pdev, 0x42, 0x36);
873	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
874}
875
876
877static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
878{
879	u8 conf;
880
881	static const struct ata_port_info info_smart = {
882		.flags = ATA_FLAG_SLAVE_POSS,
883		.pio_mask = ATA_PIO4,
884		.mwdma_mask = ATA_MWDMA2,
885		.udma_mask = ATA_UDMA6,
886		.port_ops = &it821x_smart_port_ops
887	};
888	static const struct ata_port_info info_passthru = {
889		.flags = ATA_FLAG_SLAVE_POSS,
890		.pio_mask = ATA_PIO4,
891		.mwdma_mask = ATA_MWDMA2,
892		.udma_mask = ATA_UDMA6,
893		.port_ops = &it821x_passthru_port_ops
894	};
895	static const struct ata_port_info info_rdc = {
896		.flags = ATA_FLAG_SLAVE_POSS,
897		.pio_mask = ATA_PIO4,
898		.mwdma_mask = ATA_MWDMA2,
899		.udma_mask = ATA_UDMA6,
900		.port_ops = &it821x_rdc_port_ops
901	};
902	static const struct ata_port_info info_rdc_11 = {
903		.flags = ATA_FLAG_SLAVE_POSS,
904		.pio_mask = ATA_PIO4,
905		.mwdma_mask = ATA_MWDMA2,
906		/* No UDMA */
907		.port_ops = &it821x_rdc_port_ops
908	};
909
910	const struct ata_port_info *ppi[] = { NULL, NULL };
911	static const char *mode[2] = { "pass through", "smart" };
912	int rc;
913
914	rc = pcim_enable_device(pdev);
915	if (rc)
916		return rc;
917
918	if (pdev->vendor == PCI_VENDOR_ID_RDC) {
919		/* Deal with Vortex86SX */
920		if (pdev->revision == 0x11)
921			ppi[0] = &info_rdc_11;
922		else
923			ppi[0] = &info_rdc;
924	} else {
925		/* Force the card into bypass mode if so requested */
926		if (it8212_noraid) {
927			dev_info(&pdev->dev, "forcing bypass mode.\n");
928			it821x_disable_raid(pdev);
929		}
930		pci_read_config_byte(pdev, 0x50, &conf);
931		conf &= 1;
932
933		dev_info(&pdev->dev, "controller in %s mode.\n", mode[conf]);
934
935		if (conf == 0)
936			ppi[0] = &info_passthru;
937		else
938			ppi[0] = &info_smart;
939	}
940	return ata_pci_bmdma_init_one(pdev, ppi, &it821x_sht, NULL, 0);
941}
942
943#ifdef CONFIG_PM_SLEEP
944static int it821x_reinit_one(struct pci_dev *pdev)
945{
946	struct ata_host *host = pci_get_drvdata(pdev);
947	int rc;
948
949	rc = ata_pci_device_do_resume(pdev);
950	if (rc)
951		return rc;
952	/* Resume - turn raid back off if need be */
953	if (it8212_noraid)
954		it821x_disable_raid(pdev);
955	ata_host_resume(host);
956	return rc;
957}
958#endif
959
960static const struct pci_device_id it821x[] = {
961	{ PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), },
962	{ PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), },
963	{ PCI_VDEVICE(RDC, PCI_DEVICE_ID_RDC_D1010), },
964
965	{ },
966};
967
968static struct pci_driver it821x_pci_driver = {
969	.name 		= DRV_NAME,
970	.id_table	= it821x,
971	.probe 		= it821x_init_one,
972	.remove		= ata_pci_remove_one,
973#ifdef CONFIG_PM_SLEEP
974	.suspend	= ata_pci_device_suspend,
975	.resume		= it821x_reinit_one,
976#endif
977};
978
979module_pci_driver(it821x_pci_driver);
980
981MODULE_AUTHOR("Alan Cox");
982MODULE_DESCRIPTION("low-level driver for the IT8211/IT8212 IDE RAID controller");
983MODULE_LICENSE("GPL");
984MODULE_DEVICE_TABLE(pci, it821x);
985MODULE_VERSION(DRV_VERSION);
986
987module_param_named(noraid, it8212_noraid, int, S_IRUGO);
988MODULE_PARM_DESC(noraid, "Force card into bypass mode");