pata_ep93xx.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * EP93XX PATA controller driver.
   4 *
   5 * Copyright (c) 2012, Metasoft s.c.
   6 *	Rafal Prylowski <prylowski@metasoft.pl>
   7 *
   8 * Based on pata_scc.c, pata_icside.c and on earlier version of EP93XX
   9 * PATA driver by Lennert Buytenhek and Alessandro Zummo.
  10 * Read/Write timings, resource management and other improvements
  11 * from driver by Joao Ramos and Bartlomiej Zolnierkiewicz.
  12 * DMA engine support based on spi-ep93xx.c by Mika Westerberg.
  13 *
  14 * Original copyrights:
  15 *
  16 * Support for Cirrus Logic's EP93xx (EP9312, EP9315) CPUs
  17 * PATA host controller driver.
  18 *
  19 * Copyright (c) 2009, Bartlomiej Zolnierkiewicz
  20 *
  21 * Heavily based on the ep93xx-ide.c driver:
  22 *
  23 * Copyright (c) 2009, Joao Ramos <joao.ramos@inov.pt>
  24 *		      INESC Inovacao (INOV)
  25 *
  26 * EP93XX PATA controller driver.
  27 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
  28 *
  29 * An ATA driver for the Cirrus Logic EP93xx PATA controller.
  30 *
  31 * Based on an earlier version by Alessandro Zummo, which is:
  32 *   Copyright (C) 2006 Tower Technologies
  33 */
  34
  35#include <linux/err.h>
  36#include <linux/kernel.h>
  37#include <linux/module.h>
  38#include <linux/blkdev.h>
  39#include <scsi/scsi_host.h>
  40#include <linux/ata.h>
  41#include <linux/libata.h>
  42#include <linux/platform_device.h>
  43#include <linux/sys_soc.h>
  44#include <linux/delay.h>
  45#include <linux/dmaengine.h>
  46#include <linux/ktime.h>
  47#include <linux/mod_devicetable.h>
  48
  49#include <linux/soc/cirrus/ep93xx.h>
  50
  51#define DRV_NAME	"ep93xx-ide"
  52#define DRV_VERSION	"1.0"
  53
  54enum {
  55	/* IDE Control Register */
  56	IDECTRL				= 0x00,
  57	IDECTRL_CS0N			= (1 << 0),
  58	IDECTRL_CS1N			= (1 << 1),
  59	IDECTRL_DIORN			= (1 << 5),
  60	IDECTRL_DIOWN			= (1 << 6),
  61	IDECTRL_INTRQ			= (1 << 9),
  62	IDECTRL_IORDY			= (1 << 10),
  63	/*
  64	 * the device IDE register to be accessed is selected through
  65	 * IDECTRL register's specific bitfields 'DA', 'CS1N' and 'CS0N':
  66	 *   b4   b3   b2    b1     b0
  67	 *   A2   A1   A0   CS1N   CS0N
  68	 * the values filled in this structure allows the value to be directly
  69	 * ORed to the IDECTRL register, hence giving directly the A[2:0] and
  70	 * CS1N/CS0N values for each IDE register.
  71	 * The values correspond to the transformation:
  72	 *   ((real IDE address) << 2) | CS1N value << 1 | CS0N value
  73	 */
  74	IDECTRL_ADDR_CMD		= 0 + 2, /* CS1 */
  75	IDECTRL_ADDR_DATA		= (ATA_REG_DATA << 2) + 2,
  76	IDECTRL_ADDR_ERROR		= (ATA_REG_ERR << 2) + 2,
  77	IDECTRL_ADDR_FEATURE		= (ATA_REG_FEATURE << 2) + 2,
  78	IDECTRL_ADDR_NSECT		= (ATA_REG_NSECT << 2) + 2,
  79	IDECTRL_ADDR_LBAL		= (ATA_REG_LBAL << 2) + 2,
  80	IDECTRL_ADDR_LBAM		= (ATA_REG_LBAM << 2) + 2,
  81	IDECTRL_ADDR_LBAH		= (ATA_REG_LBAH << 2) + 2,
  82	IDECTRL_ADDR_DEVICE		= (ATA_REG_DEVICE << 2) + 2,
  83	IDECTRL_ADDR_STATUS		= (ATA_REG_STATUS << 2) + 2,
  84	IDECTRL_ADDR_COMMAND		= (ATA_REG_CMD << 2) + 2,
  85	IDECTRL_ADDR_ALTSTATUS		= (0x06 << 2) + 1, /* CS0 */
  86	IDECTRL_ADDR_CTL		= (0x06 << 2) + 1, /* CS0 */
  87
  88	/* IDE Configuration Register */
  89	IDECFG				= 0x04,
  90	IDECFG_IDEEN			= (1 << 0),
  91	IDECFG_PIO			= (1 << 1),
  92	IDECFG_MDMA			= (1 << 2),
  93	IDECFG_UDMA			= (1 << 3),
  94	IDECFG_MODE_SHIFT		= 4,
  95	IDECFG_MODE_MASK		= (0xf << 4),
  96	IDECFG_WST_SHIFT		= 8,
  97	IDECFG_WST_MASK			= (0x3 << 8),
  98
  99	/* MDMA Operation Register */
 100	IDEMDMAOP			= 0x08,
 101
 102	/* UDMA Operation Register */
 103	IDEUDMAOP			= 0x0c,
 104	IDEUDMAOP_UEN			= (1 << 0),
 105	IDEUDMAOP_RWOP			= (1 << 1),
 106
 107	/* PIO/MDMA/UDMA Data Registers */
 108	IDEDATAOUT			= 0x10,
 109	IDEDATAIN			= 0x14,
 110	IDEMDMADATAOUT			= 0x18,
 111	IDEMDMADATAIN			= 0x1c,
 112	IDEUDMADATAOUT			= 0x20,
 113	IDEUDMADATAIN			= 0x24,
 114
 115	/* UDMA Status Register */
 116	IDEUDMASTS			= 0x28,
 117	IDEUDMASTS_DMAIDE		= (1 << 16),
 118	IDEUDMASTS_INTIDE		= (1 << 17),
 119	IDEUDMASTS_SBUSY		= (1 << 18),
 120	IDEUDMASTS_NDO			= (1 << 24),
 121	IDEUDMASTS_NDI			= (1 << 25),
 122	IDEUDMASTS_N4X			= (1 << 26),
 123
 124	/* UDMA Debug Status Register */
 125	IDEUDMADEBUG			= 0x2c,
 126};
 127
 128struct ep93xx_pata_data {
 129	struct platform_device *pdev;
 130	void __iomem *ide_base;
 131	struct ata_timing t;
 132	bool iordy;
 133
 134	unsigned long udma_in_phys;
 135	unsigned long udma_out_phys;
 136
 137	struct dma_chan *dma_rx_channel;
 138	struct dma_chan *dma_tx_channel;
 139};
 140
 141static void ep93xx_pata_clear_regs(void __iomem *base)
 142{
 143	writel(IDECTRL_CS0N | IDECTRL_CS1N | IDECTRL_DIORN |
 144		IDECTRL_DIOWN, base + IDECTRL);
 145
 146	writel(0, base + IDECFG);
 147	writel(0, base + IDEMDMAOP);
 148	writel(0, base + IDEUDMAOP);
 149	writel(0, base + IDEDATAOUT);
 150	writel(0, base + IDEDATAIN);
 151	writel(0, base + IDEMDMADATAOUT);
 152	writel(0, base + IDEMDMADATAIN);
 153	writel(0, base + IDEUDMADATAOUT);
 154	writel(0, base + IDEUDMADATAIN);
 155	writel(0, base + IDEUDMADEBUG);
 156}
 157
 158static bool ep93xx_pata_check_iordy(void __iomem *base)
 159{
 160	return !!(readl(base + IDECTRL) & IDECTRL_IORDY);
 161}
 162
 163/*
 164 * According to EP93xx User's Guide, WST field of IDECFG specifies number
 165 * of HCLK cycles to hold the data bus after a PIO write operation.
 166 * It should be programmed to guarantee following delays:
 167 *
 168 * PIO Mode   [ns]
 169 * 0          30
 170 * 1          20
 171 * 2          15
 172 * 3          10
 173 * 4          5
 174 *
 175 * Maximum possible value for HCLK is 100MHz.
 176 */
 177static int ep93xx_pata_get_wst(int pio_mode)
 178{
 179	int val;
 180
 181	if (pio_mode == 0)
 182		val = 3;
 183	else if (pio_mode < 3)
 184		val = 2;
 185	else
 186		val = 1;
 187
 188	return val << IDECFG_WST_SHIFT;
 189}
 190
 191static void ep93xx_pata_enable_pio(void __iomem *base, int pio_mode)
 192{
 193	writel(IDECFG_IDEEN | IDECFG_PIO |
 194		ep93xx_pata_get_wst(pio_mode) |
 195		(pio_mode << IDECFG_MODE_SHIFT), base + IDECFG);
 196}
 197
 198/*
 199 * Based on delay loop found in mach-pxa/mp900.c.
 200 *
 201 * Single iteration should take 5 cpu cycles. This is 25ns assuming the
 202 * fastest ep93xx cpu speed (200MHz) and is better optimized for PIO4 timings
 203 * than eg. 20ns.
 204 */
 205static void ep93xx_pata_delay(unsigned long count)
 206{
 207	__asm__ volatile (
 208		"0:\n"
 209		"mov r0, r0\n"
 210		"subs %0, %1, #1\n"
 211		"bge 0b\n"
 212		: "=r" (count)
 213		: "0" (count)
 214	);
 215}
 216
 217static unsigned long ep93xx_pata_wait_for_iordy(void __iomem *base,
 218						unsigned long t2)
 219{
 220	/*
 221	 * According to ATA specification, IORDY pin can be first sampled
 222	 * tA = 35ns after activation of DIOR-/DIOW-. Maximum IORDY pulse
 223	 * width is tB = 1250ns.
 224	 *
 225	 * We are already t2 delay loop iterations after activation of
 226	 * DIOR-/DIOW-, so we set timeout to (1250 + 35) / 25 - t2 additional
 227	 * delay loop iterations.
 228	 */
 229	unsigned long start = (1250 + 35) / 25 - t2;
 230	unsigned long counter = start;
 231
 232	while (!ep93xx_pata_check_iordy(base) && counter--)
 233		ep93xx_pata_delay(1);
 234	return start - counter;
 235}
 236
 237/* common part at start of ep93xx_pata_read/write() */
 238static void ep93xx_pata_rw_begin(void __iomem *base, unsigned long addr,
 239				 unsigned long t1)
 240{
 241	writel(IDECTRL_DIOWN | IDECTRL_DIORN | addr, base + IDECTRL);
 242	ep93xx_pata_delay(t1);
 243}
 244
 245/* common part at end of ep93xx_pata_read/write() */
 246static void ep93xx_pata_rw_end(void __iomem *base, unsigned long addr,
 247			       bool iordy, unsigned long t0, unsigned long t2,
 248			       unsigned long t2i)
 249{
 250	ep93xx_pata_delay(t2);
 251	/* lengthen t2 if needed */
 252	if (iordy)
 253		t2 += ep93xx_pata_wait_for_iordy(base, t2);
 254	writel(IDECTRL_DIOWN | IDECTRL_DIORN | addr, base + IDECTRL);
 255	if (t0 > t2 && t0 - t2 > t2i)
 256		ep93xx_pata_delay(t0 - t2);
 257	else
 258		ep93xx_pata_delay(t2i);
 259}
 260
 261static u16 ep93xx_pata_read(struct ep93xx_pata_data *drv_data,
 262			    unsigned long addr,
 263			    bool reg)
 264{
 265	void __iomem *base = drv_data->ide_base;
 266	const struct ata_timing *t = &drv_data->t;
 267	unsigned long t0 = reg ? t->cyc8b : t->cycle;
 268	unsigned long t2 = reg ? t->act8b : t->active;
 269	unsigned long t2i = reg ? t->rec8b : t->recover;
 270
 271	ep93xx_pata_rw_begin(base, addr, t->setup);
 272	writel(IDECTRL_DIOWN | addr, base + IDECTRL);
 273	/*
 274	 * The IDEDATAIN register is loaded from the DD pins at the positive
 275	 * edge of the DIORN signal. (EP93xx UG p27-14)
 276	 */
 277	ep93xx_pata_rw_end(base, addr, drv_data->iordy, t0, t2, t2i);
 278	return readl(base + IDEDATAIN);
 279}
 280
 281/* IDE register read */
 282static u16 ep93xx_pata_read_reg(struct ep93xx_pata_data *drv_data,
 283				unsigned long addr)
 284{
 285	return ep93xx_pata_read(drv_data, addr, true);
 286}
 287
 288/* PIO data read */
 289static u16 ep93xx_pata_read_data(struct ep93xx_pata_data *drv_data,
 290				 unsigned long addr)
 291{
 292	return ep93xx_pata_read(drv_data, addr, false);
 293}
 294
 295static void ep93xx_pata_write(struct ep93xx_pata_data *drv_data,
 296			      u16 value, unsigned long addr,
 297			      bool reg)
 298{
 299	void __iomem *base = drv_data->ide_base;
 300	const struct ata_timing *t = &drv_data->t;
 301	unsigned long t0 = reg ? t->cyc8b : t->cycle;
 302	unsigned long t2 = reg ? t->act8b : t->active;
 303	unsigned long t2i = reg ? t->rec8b : t->recover;
 304
 305	ep93xx_pata_rw_begin(base, addr, t->setup);
 306	/*
 307	 * Value from IDEDATAOUT register is driven onto the DD pins when
 308	 * DIOWN is low. (EP93xx UG p27-13)
 309	 */
 310	writel(value, base + IDEDATAOUT);
 311	writel(IDECTRL_DIORN | addr, base + IDECTRL);
 312	ep93xx_pata_rw_end(base, addr, drv_data->iordy, t0, t2, t2i);
 313}
 314
 315/* IDE register write */
 316static void ep93xx_pata_write_reg(struct ep93xx_pata_data *drv_data,
 317				  u16 value, unsigned long addr)
 318{
 319	ep93xx_pata_write(drv_data, value, addr, true);
 320}
 321
 322/* PIO data write */
 323static void ep93xx_pata_write_data(struct ep93xx_pata_data *drv_data,
 324				   u16 value, unsigned long addr)
 325{
 326	ep93xx_pata_write(drv_data, value, addr, false);
 327}
 328
 329static void ep93xx_pata_set_piomode(struct ata_port *ap,
 330				    struct ata_device *adev)
 331{
 332	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 333	struct ata_device *pair = ata_dev_pair(adev);
 334	/*
 335	 * Calculate timings for the delay loop, assuming ep93xx cpu speed
 336	 * is 200MHz (maximum possible for ep93xx). If actual cpu speed is
 337	 * slower, we will wait a bit longer in each delay.
 338	 * Additional division of cpu speed by 5, because single iteration
 339	 * of our delay loop takes 5 cpu cycles (25ns).
 340	 */
 341	unsigned long T = 1000000 / (200 / 5);
 342
 343	ata_timing_compute(adev, adev->pio_mode, &drv_data->t, T, 0);
 344	if (pair && pair->pio_mode) {
 345		struct ata_timing t;
 346		ata_timing_compute(pair, pair->pio_mode, &t, T, 0);
 347		ata_timing_merge(&t, &drv_data->t, &drv_data->t,
 348			ATA_TIMING_SETUP | ATA_TIMING_8BIT);
 349	}
 350	drv_data->iordy = ata_pio_need_iordy(adev);
 351
 352	ep93xx_pata_enable_pio(drv_data->ide_base,
 353			       adev->pio_mode - XFER_PIO_0);
 354}
 355
 356/* Note: original code is ata_sff_check_status */
 357static u8 ep93xx_pata_check_status(struct ata_port *ap)
 358{
 359	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 360
 361	return ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_STATUS);
 362}
 363
 364static u8 ep93xx_pata_check_altstatus(struct ata_port *ap)
 365{
 366	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 367
 368	return ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_ALTSTATUS);
 369}
 370
 371/* Note: original code is ata_sff_tf_load */
 372static void ep93xx_pata_tf_load(struct ata_port *ap,
 373				const struct ata_taskfile *tf)
 374{
 375	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 376	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
 377
 378	if (tf->ctl != ap->last_ctl) {
 379		ep93xx_pata_write_reg(drv_data, tf->ctl, IDECTRL_ADDR_CTL);
 380		ap->last_ctl = tf->ctl;
 381		ata_wait_idle(ap);
 382	}
 383
 384	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
 385		ep93xx_pata_write_reg(drv_data, tf->hob_feature,
 386			IDECTRL_ADDR_FEATURE);
 387		ep93xx_pata_write_reg(drv_data, tf->hob_nsect,
 388			IDECTRL_ADDR_NSECT);
 389		ep93xx_pata_write_reg(drv_data, tf->hob_lbal,
 390			IDECTRL_ADDR_LBAL);
 391		ep93xx_pata_write_reg(drv_data, tf->hob_lbam,
 392			IDECTRL_ADDR_LBAM);
 393		ep93xx_pata_write_reg(drv_data, tf->hob_lbah,
 394			IDECTRL_ADDR_LBAH);
 395	}
 396
 397	if (is_addr) {
 398		ep93xx_pata_write_reg(drv_data, tf->feature,
 399			IDECTRL_ADDR_FEATURE);
 400		ep93xx_pata_write_reg(drv_data, tf->nsect, IDECTRL_ADDR_NSECT);
 401		ep93xx_pata_write_reg(drv_data, tf->lbal, IDECTRL_ADDR_LBAL);
 402		ep93xx_pata_write_reg(drv_data, tf->lbam, IDECTRL_ADDR_LBAM);
 403		ep93xx_pata_write_reg(drv_data, tf->lbah, IDECTRL_ADDR_LBAH);
 404	}
 405
 406	if (tf->flags & ATA_TFLAG_DEVICE)
 407		ep93xx_pata_write_reg(drv_data, tf->device,
 408			IDECTRL_ADDR_DEVICE);
 409
 410	ata_wait_idle(ap);
 411}
 412
 413/* Note: original code is ata_sff_tf_read */
 414static void ep93xx_pata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 415{
 416	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 417
 418	tf->status = ep93xx_pata_check_status(ap);
 419	tf->error = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_FEATURE);
 420	tf->nsect = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_NSECT);
 421	tf->lbal = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAL);
 422	tf->lbam = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAM);
 423	tf->lbah = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAH);
 424	tf->device = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_DEVICE);
 425
 426	if (tf->flags & ATA_TFLAG_LBA48) {
 427		ep93xx_pata_write_reg(drv_data, tf->ctl | ATA_HOB,
 428			IDECTRL_ADDR_CTL);
 429		tf->hob_feature = ep93xx_pata_read_reg(drv_data,
 430			IDECTRL_ADDR_FEATURE);
 431		tf->hob_nsect = ep93xx_pata_read_reg(drv_data,
 432			IDECTRL_ADDR_NSECT);
 433		tf->hob_lbal = ep93xx_pata_read_reg(drv_data,
 434			IDECTRL_ADDR_LBAL);
 435		tf->hob_lbam = ep93xx_pata_read_reg(drv_data,
 436			IDECTRL_ADDR_LBAM);
 437		tf->hob_lbah = ep93xx_pata_read_reg(drv_data,
 438			IDECTRL_ADDR_LBAH);
 439		ep93xx_pata_write_reg(drv_data, tf->ctl, IDECTRL_ADDR_CTL);
 440		ap->last_ctl = tf->ctl;
 441	}
 442}
 443
 444/* Note: original code is ata_sff_exec_command */
 445static void ep93xx_pata_exec_command(struct ata_port *ap,
 446				     const struct ata_taskfile *tf)
 447{
 448	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 449
 450	ep93xx_pata_write_reg(drv_data, tf->command,
 451			  IDECTRL_ADDR_COMMAND);
 452	ata_sff_pause(ap);
 453}
 454
 455/* Note: original code is ata_sff_dev_select */
 456static void ep93xx_pata_dev_select(struct ata_port *ap, unsigned int device)
 457{
 458	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 459	u8 tmp = ATA_DEVICE_OBS;
 460
 461	if (device != 0)
 462		tmp |= ATA_DEV1;
 463
 464	ep93xx_pata_write_reg(drv_data, tmp, IDECTRL_ADDR_DEVICE);
 465	ata_sff_pause(ap);	/* needed; also flushes, for mmio */
 466}
 467
 468/* Note: original code is ata_sff_set_devctl */
 469static void ep93xx_pata_set_devctl(struct ata_port *ap, u8 ctl)
 470{
 471	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 472
 473	ep93xx_pata_write_reg(drv_data, ctl, IDECTRL_ADDR_CTL);
 474}
 475
 476/* Note: original code is ata_sff_data_xfer */
 477static unsigned int ep93xx_pata_data_xfer(struct ata_queued_cmd *qc,
 478					  unsigned char *buf,
 479					  unsigned int buflen, int rw)
 480{
 481	struct ata_port *ap = qc->dev->link->ap;
 482	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 483	u16 *data = (u16 *)buf;
 484	unsigned int words = buflen >> 1;
 485
 486	/* Transfer multiple of 2 bytes */
 487	while (words--)
 488		if (rw == READ)
 489			*data++ = cpu_to_le16(
 490				ep93xx_pata_read_data(
 491					drv_data, IDECTRL_ADDR_DATA));
 492		else
 493			ep93xx_pata_write_data(drv_data, le16_to_cpu(*data++),
 494				IDECTRL_ADDR_DATA);
 495
 496	/* Transfer trailing 1 byte, if any. */
 497	if (unlikely(buflen & 0x01)) {
 498		unsigned char pad[2] = { };
 499
 500		buf += buflen - 1;
 501
 502		if (rw == READ) {
 503			*pad = cpu_to_le16(
 504				ep93xx_pata_read_data(
 505					drv_data, IDECTRL_ADDR_DATA));
 506			*buf = pad[0];
 507		} else {
 508			pad[0] = *buf;
 509			ep93xx_pata_write_data(drv_data, le16_to_cpu(*pad),
 510					  IDECTRL_ADDR_DATA);
 511		}
 512		words++;
 513	}
 514
 515	return words << 1;
 516}
 517
 518/* Note: original code is ata_devchk */
 519static bool ep93xx_pata_device_is_present(struct ata_port *ap,
 520					  unsigned int device)
 521{
 522	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 523	u8 nsect, lbal;
 524
 525	ap->ops->sff_dev_select(ap, device);
 526
 527	ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_NSECT);
 528	ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_LBAL);
 529
 530	ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_NSECT);
 531	ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_LBAL);
 532
 533	ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_NSECT);
 534	ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_LBAL);
 535
 536	nsect = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_NSECT);
 537	lbal = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAL);
 538
 539	if ((nsect == 0x55) && (lbal == 0xaa))
 540		return true;
 541
 542	return false;
 543}
 544
 545/* Note: original code is ata_sff_wait_after_reset */
 546static int ep93xx_pata_wait_after_reset(struct ata_link *link,
 547					unsigned int devmask,
 548					unsigned long deadline)
 549{
 550	struct ata_port *ap = link->ap;
 551	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 552	unsigned int dev0 = devmask & (1 << 0);
 553	unsigned int dev1 = devmask & (1 << 1);
 554	int rc, ret = 0;
 555
 556	ata_msleep(ap, ATA_WAIT_AFTER_RESET);
 557
 558	/* always check readiness of the master device */
 559	rc = ata_sff_wait_ready(link, deadline);
 560	/*
 561	 * -ENODEV means the odd clown forgot the D7 pulldown resistor
 562	 * and TF status is 0xff, bail out on it too.
 563	 */
 564	if (rc)
 565		return rc;
 566
 567	/*
 568	 * if device 1 was found in ata_devchk, wait for register
 569	 * access briefly, then wait for BSY to clear.
 570	 */
 571	if (dev1) {
 572		int i;
 573
 574		ap->ops->sff_dev_select(ap, 1);
 575
 576		/*
 577		 * Wait for register access.  Some ATAPI devices fail
 578		 * to set nsect/lbal after reset, so don't waste too
 579		 * much time on it.  We're gonna wait for !BSY anyway.
 580		 */
 581		for (i = 0; i < 2; i++) {
 582			u8 nsect, lbal;
 583
 584			nsect = ep93xx_pata_read_reg(drv_data,
 585				IDECTRL_ADDR_NSECT);
 586			lbal = ep93xx_pata_read_reg(drv_data,
 587				IDECTRL_ADDR_LBAL);
 588			if (nsect == 1 && lbal == 1)
 589				break;
 590			msleep(50);	/* give drive a breather */
 591		}
 592
 593		rc = ata_sff_wait_ready(link, deadline);
 594		if (rc) {
 595			if (rc != -ENODEV)
 596				return rc;
 597			ret = rc;
 598		}
 599	}
 600	/* is all this really necessary? */
 601	ap->ops->sff_dev_select(ap, 0);
 602	if (dev1)
 603		ap->ops->sff_dev_select(ap, 1);
 604	if (dev0)
 605		ap->ops->sff_dev_select(ap, 0);
 606
 607	return ret;
 608}
 609
 610/* Note: original code is ata_bus_softreset */
 611static int ep93xx_pata_bus_softreset(struct ata_port *ap, unsigned int devmask,
 612				     unsigned long deadline)
 613{
 614	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 615
 616	ep93xx_pata_write_reg(drv_data, ap->ctl, IDECTRL_ADDR_CTL);
 617	udelay(20);		/* FIXME: flush */
 618	ep93xx_pata_write_reg(drv_data, ap->ctl | ATA_SRST, IDECTRL_ADDR_CTL);
 619	udelay(20);		/* FIXME: flush */
 620	ep93xx_pata_write_reg(drv_data, ap->ctl, IDECTRL_ADDR_CTL);
 621	ap->last_ctl = ap->ctl;
 622
 623	return ep93xx_pata_wait_after_reset(&ap->link, devmask, deadline);
 624}
 625
 626static void ep93xx_pata_release_dma(struct ep93xx_pata_data *drv_data)
 627{
 628	if (drv_data->dma_rx_channel) {
 629		dma_release_channel(drv_data->dma_rx_channel);
 630		drv_data->dma_rx_channel = NULL;
 631	}
 632	if (drv_data->dma_tx_channel) {
 633		dma_release_channel(drv_data->dma_tx_channel);
 634		drv_data->dma_tx_channel = NULL;
 635	}
 636}
 637
 638static int ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data)
 639{
 640	struct platform_device *pdev = drv_data->pdev;
 641	struct device *dev = &pdev->dev;
 642	dma_cap_mask_t mask;
 643	struct dma_slave_config conf;
 644	int ret;
 645
 646	dma_cap_zero(mask);
 647	dma_cap_set(DMA_SLAVE, mask);
 648
 649	/*
 650	 * Request two channels for IDE. Another possibility would be
 651	 * to request only one channel, and reprogram it's direction at
 652	 * start of new transfer.
 653	 */
 654	drv_data->dma_rx_channel = dma_request_chan(dev, "rx");
 655	if (IS_ERR(drv_data->dma_rx_channel))
 656		return dev_err_probe(dev, PTR_ERR(drv_data->dma_rx_channel),
 657				     "rx DMA setup failed\n");
 658
 659	drv_data->dma_tx_channel = dma_request_chan(&pdev->dev, "tx");
 660	if (IS_ERR(drv_data->dma_tx_channel)) {
 661		ret = dev_err_probe(dev, PTR_ERR(drv_data->dma_tx_channel),
 662				    "tx DMA setup failed\n");
 663		goto fail_release_rx;
 664	}
 665
 666	/* Configure receive channel direction and source address */
 667	memset(&conf, 0, sizeof(conf));
 668	conf.direction = DMA_DEV_TO_MEM;
 669	conf.src_addr = drv_data->udma_in_phys;
 670	conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 671	ret = dmaengine_slave_config(drv_data->dma_rx_channel, &conf);
 672	if (ret) {
 673		dev_err_probe(dev, ret, "failed to configure rx dma channel");
 674		goto fail_release_dma;
 675	}
 676
 677	/* Configure transmit channel direction and destination address */
 678	memset(&conf, 0, sizeof(conf));
 679	conf.direction = DMA_MEM_TO_DEV;
 680	conf.dst_addr = drv_data->udma_out_phys;
 681	conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 682	ret = dmaengine_slave_config(drv_data->dma_tx_channel, &conf);
 683	if (ret) {
 684		dev_err_probe(dev, ret, "failed to configure tx dma channel");
 685		goto fail_release_dma;
 686	}
 687
 688	return 0;
 689
 690fail_release_rx:
 691	dma_release_channel(drv_data->dma_rx_channel);
 692fail_release_dma:
 693	ep93xx_pata_release_dma(drv_data);
 694
 695	return ret;
 696}
 697
 698static void ep93xx_pata_dma_start(struct ata_queued_cmd *qc)
 699{
 700	struct dma_async_tx_descriptor *txd;
 701	struct ep93xx_pata_data *drv_data = qc->ap->host->private_data;
 702	void __iomem *base = drv_data->ide_base;
 703	struct ata_device *adev = qc->dev;
 704	u32 v = qc->dma_dir == DMA_TO_DEVICE ? IDEUDMAOP_RWOP : 0;
 705	struct dma_chan *channel = qc->dma_dir == DMA_TO_DEVICE
 706		? drv_data->dma_tx_channel : drv_data->dma_rx_channel;
 707
 708	txd = dmaengine_prep_slave_sg(channel, qc->sg, qc->n_elem, qc->dma_dir,
 709		DMA_CTRL_ACK);
 710	if (!txd) {
 711		dev_err(qc->ap->dev, "failed to prepare slave for sg dma\n");
 712		return;
 713	}
 714	txd->callback = NULL;
 715	txd->callback_param = NULL;
 716
 717	if (dmaengine_submit(txd) < 0) {
 718		dev_err(qc->ap->dev, "failed to submit dma transfer\n");
 719		return;
 720	}
 721	dma_async_issue_pending(channel);
 722
 723	/*
 724	 * When enabling UDMA operation, IDEUDMAOP register needs to be
 725	 * programmed in three step sequence:
 726	 * 1) set or clear the RWOP bit,
 727	 * 2) perform dummy read of the register,
 728	 * 3) set the UEN bit.
 729	 */
 730	writel(v, base + IDEUDMAOP);
 731	readl(base + IDEUDMAOP);
 732	writel(v | IDEUDMAOP_UEN, base + IDEUDMAOP);
 733
 734	writel(IDECFG_IDEEN | IDECFG_UDMA |
 735		((adev->xfer_mode - XFER_UDMA_0) << IDECFG_MODE_SHIFT),
 736		base + IDECFG);
 737}
 738
 739static void ep93xx_pata_dma_stop(struct ata_queued_cmd *qc)
 740{
 741	struct ep93xx_pata_data *drv_data = qc->ap->host->private_data;
 742	void __iomem *base = drv_data->ide_base;
 743
 744	/* terminate all dma transfers, if not yet finished */
 745	dmaengine_terminate_all(drv_data->dma_rx_channel);
 746	dmaengine_terminate_all(drv_data->dma_tx_channel);
 747
 748	/*
 749	 * To properly stop IDE-DMA, IDEUDMAOP register must to be cleared
 750	 * and IDECTRL register must be set to default value.
 751	 */
 752	writel(0, base + IDEUDMAOP);
 753	writel(readl(base + IDECTRL) | IDECTRL_DIOWN | IDECTRL_DIORN |
 754		IDECTRL_CS0N | IDECTRL_CS1N, base + IDECTRL);
 755
 756	ep93xx_pata_enable_pio(drv_data->ide_base,
 757		qc->dev->pio_mode - XFER_PIO_0);
 758
 759	ata_sff_dma_pause(qc->ap);
 760}
 761
 762static void ep93xx_pata_dma_setup(struct ata_queued_cmd *qc)
 763{
 764	qc->ap->ops->sff_exec_command(qc->ap, &qc->tf);
 765}
 766
 767static u8 ep93xx_pata_dma_status(struct ata_port *ap)
 768{
 769	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 770	u32 val = readl(drv_data->ide_base + IDEUDMASTS);
 771
 772	/*
 773	 * UDMA Status Register bits:
 774	 *
 775	 * DMAIDE - DMA request signal from UDMA state machine,
 776	 * INTIDE - INT line generated by UDMA because of errors in the
 777	 *          state machine,
 778	 * SBUSY - UDMA state machine busy, not in idle state,
 779	 * NDO   - error for data-out not completed,
 780	 * NDI   - error for data-in not completed,
 781	 * N4X   - error for data transferred not multiplies of four
 782	 *         32-bit words.
 783	 * (EP93xx UG p27-17)
 784	 */
 785	if (val & IDEUDMASTS_NDO || val & IDEUDMASTS_NDI ||
 786	    val & IDEUDMASTS_N4X || val & IDEUDMASTS_INTIDE)
 787		return ATA_DMA_ERR;
 788
 789	/* read INTRQ (INT[3]) pin input state */
 790	if (readl(drv_data->ide_base + IDECTRL) & IDECTRL_INTRQ)
 791		return ATA_DMA_INTR;
 792
 793	if (val & IDEUDMASTS_SBUSY || val & IDEUDMASTS_DMAIDE)
 794		return ATA_DMA_ACTIVE;
 795
 796	return 0;
 797}
 798
 799/* Note: original code is ata_sff_softreset */
 800static int ep93xx_pata_softreset(struct ata_link *al, unsigned int *classes,
 801				 unsigned long deadline)
 802{
 803	struct ata_port *ap = al->ap;
 804	unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
 805	unsigned int devmask = 0;
 806	int rc;
 807	u8 err;
 808
 809	/* determine if device 0/1 are present */
 810	if (ep93xx_pata_device_is_present(ap, 0))
 811		devmask |= (1 << 0);
 812	if (slave_possible && ep93xx_pata_device_is_present(ap, 1))
 813		devmask |= (1 << 1);
 814
 815	/* select device 0 again */
 816	ap->ops->sff_dev_select(al->ap, 0);
 817
 818	/* issue bus reset */
 819	rc = ep93xx_pata_bus_softreset(ap, devmask, deadline);
 820	/* if link is ocuppied, -ENODEV too is an error */
 821	if (rc && (rc != -ENODEV || sata_scr_valid(al))) {
 822		ata_link_err(al, "SRST failed (errno=%d)\n", rc);
 823		return rc;
 824	}
 825
 826	/* determine by signature whether we have ATA or ATAPI devices */
 827	classes[0] = ata_sff_dev_classify(&al->device[0], devmask & (1 << 0),
 828					  &err);
 829	if (slave_possible && err != 0x81)
 830		classes[1] = ata_sff_dev_classify(&al->device[1],
 831						  devmask & (1 << 1), &err);
 832
 833	return 0;
 834}
 835
 836/* Note: original code is ata_sff_drain_fifo */
 837static void ep93xx_pata_drain_fifo(struct ata_queued_cmd *qc)
 838{
 839	int count;
 840	struct ata_port *ap;
 841	struct ep93xx_pata_data *drv_data;
 842
 843	/* We only need to flush incoming data when a command was running */
 844	if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
 845		return;
 846
 847	ap = qc->ap;
 848	drv_data = ap->host->private_data;
 849	/* Drain up to 64K of data before we give up this recovery method */
 850	for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
 851		     && count < 65536; count += 2)
 852		ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_DATA);
 853
 854	if (count)
 855		ata_port_dbg(ap, "drained %d bytes to clear DRQ.\n", count);
 856
 857}
 858
 859static int ep93xx_pata_port_start(struct ata_port *ap)
 860{
 861	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 862
 863	/*
 864	 * Set timings to safe values at startup (= number of ns from ATA
 865	 * specification), we'll switch to properly calculated values later.
 866	 */
 867	drv_data->t = *ata_timing_find_mode(XFER_PIO_0);
 868	return 0;
 869}
 870
 871static const struct scsi_host_template ep93xx_pata_sht = {
 872	ATA_BASE_SHT(DRV_NAME),
 873	/* ep93xx dma implementation limit */
 874	.sg_tablesize		= 32,
 875	/* ep93xx dma can't transfer 65536 bytes at once */
 876	.dma_boundary		= 0x7fff,
 877};
 878
 879static struct ata_port_operations ep93xx_pata_port_ops = {
 880	.inherits		= &ata_bmdma_port_ops,
 881
 882	.reset.softreset	= ep93xx_pata_softreset,
 883	.reset.hardreset	= ATA_OP_NULL,
 884
 885	.sff_dev_select		= ep93xx_pata_dev_select,
 886	.sff_set_devctl		= ep93xx_pata_set_devctl,
 887	.sff_check_status	= ep93xx_pata_check_status,
 888	.sff_check_altstatus	= ep93xx_pata_check_altstatus,
 889	.sff_tf_load		= ep93xx_pata_tf_load,
 890	.sff_tf_read		= ep93xx_pata_tf_read,
 891	.sff_exec_command	= ep93xx_pata_exec_command,
 892	.sff_data_xfer		= ep93xx_pata_data_xfer,
 893	.sff_drain_fifo		= ep93xx_pata_drain_fifo,
 894	.sff_irq_clear		= ATA_OP_NULL,
 895
 896	.set_piomode		= ep93xx_pata_set_piomode,
 897
 898	.bmdma_setup		= ep93xx_pata_dma_setup,
 899	.bmdma_start		= ep93xx_pata_dma_start,
 900	.bmdma_stop		= ep93xx_pata_dma_stop,
 901	.bmdma_status		= ep93xx_pata_dma_status,
 902
 903	.cable_detect		= ata_cable_unknown,
 904	.port_start		= ep93xx_pata_port_start,
 905};
 906
 907static const struct soc_device_attribute ep93xx_soc_table[] = {
 908	{ .revision = "E1", .data = (void *)ATA_UDMA3 },
 909	{ .revision = "E2", .data = (void *)ATA_UDMA4 },
 910	{ /* sentinel */ }
 911};
 912
 913static int ep93xx_pata_probe(struct platform_device *pdev)
 914{
 915	struct ep93xx_pata_data *drv_data;
 916	struct ata_host *host;
 917	struct ata_port *ap;
 918	int irq;
 919	struct resource *mem_res;
 920	void __iomem *ide_base;
 921	int err;
 922
 923	/* INT[3] (IRQ_EP93XX_EXT3) line connected as pull down */
 924	irq = platform_get_irq(pdev, 0);
 925	if (irq < 0)
 926		return irq;
 927
 928	ide_base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
 929	if (IS_ERR(ide_base))
 930		return PTR_ERR(ide_base);
 931
 932	drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
 933	if (!drv_data)
 934		return -ENOMEM;
 935
 936	drv_data->pdev = pdev;
 937	drv_data->ide_base = ide_base;
 938	drv_data->udma_in_phys = mem_res->start + IDEUDMADATAIN;
 939	drv_data->udma_out_phys = mem_res->start + IDEUDMADATAOUT;
 940	err = ep93xx_pata_dma_init(drv_data);
 941	if (err)
 942		return err;
 943
 944	/* allocate host */
 945	host = ata_host_alloc(&pdev->dev, 1);
 946	if (!host) {
 947		err = -ENOMEM;
 948		goto err_rel_dma;
 949	}
 950
 951	ep93xx_pata_clear_regs(ide_base);
 952
 953	host->private_data = drv_data;
 954
 955	ap = host->ports[0];
 956	ap->dev = &pdev->dev;
 957	ap->ops = &ep93xx_pata_port_ops;
 958	ap->flags |= ATA_FLAG_SLAVE_POSS;
 959	ap->pio_mask = ATA_PIO4;
 960
 961	/*
 962	 * Maximum UDMA modes:
 963	 * EP931x rev.E0 - UDMA2
 964	 * EP931x rev.E1 - UDMA3
 965	 * EP931x rev.E2 - UDMA4
 966	 *
 967	 * MWDMA support was removed from EP931x rev.E2,
 968	 * so this driver supports only UDMA modes.
 969	 */
 970	if (drv_data->dma_rx_channel && drv_data->dma_tx_channel) {
 971		const struct soc_device_attribute *match;
 972
 973		match = soc_device_match(ep93xx_soc_table);
 974		if (match)
 975			ap->udma_mask = (unsigned int) match->data;
 976		else
 977			ap->udma_mask = ATA_UDMA2;
 978	}
 979
 980	/* defaults, pio 0 */
 981	ep93xx_pata_enable_pio(ide_base, 0);
 982
 983	dev_info(&pdev->dev, "version " DRV_VERSION "\n");
 984
 985	/* activate host */
 986	err = ata_host_activate(host, irq, ata_bmdma_interrupt, 0,
 987		&ep93xx_pata_sht);
 988	if (err == 0)
 989		return 0;
 990
 991err_rel_dma:
 992	ep93xx_pata_release_dma(drv_data);
 993	return err;
 994}
 995
 996static void ep93xx_pata_remove(struct platform_device *pdev)
 997{
 998	struct ata_host *host = platform_get_drvdata(pdev);
 999	struct ep93xx_pata_data *drv_data = host->private_data;
1000
1001	ata_host_detach(host);
1002	ep93xx_pata_release_dma(drv_data);
1003	ep93xx_pata_clear_regs(drv_data->ide_base);
1004}
1005
1006static const struct of_device_id ep93xx_pata_of_ids[] = {
1007	{ .compatible = "cirrus,ep9312-pata" },
1008	{ /* sentinel */ }
1009};
1010MODULE_DEVICE_TABLE(of, ep93xx_pata_of_ids);
1011
1012static struct platform_driver ep93xx_pata_platform_driver = {
1013	.driver = {
1014		.name = DRV_NAME,
1015		.of_match_table = ep93xx_pata_of_ids,
1016	},
1017	.probe = ep93xx_pata_probe,
1018	.remove = ep93xx_pata_remove,
1019};
1020
1021module_platform_driver(ep93xx_pata_platform_driver);
1022
1023MODULE_AUTHOR("Alessandro Zummo, Lennert Buytenhek, Joao Ramos, "
1024		"Bartlomiej Zolnierkiewicz, Rafal Prylowski");
1025MODULE_DESCRIPTION("low-level driver for cirrus ep93xx IDE controller");
1026MODULE_LICENSE("GPL");
1027MODULE_VERSION(DRV_VERSION);
1028MODULE_ALIAS("platform:pata_ep93xx");