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ahci.c
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linux-6.19.14/drivers/ata/ahci.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * ahci.c - AHCI SATA support 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19#include <linux/kernel.h> 20#include <linux/module.h> 21#include <linux/pci.h> 22#include <linux/blkdev.h> 23#include <linux/delay.h> 24#include <linux/interrupt.h> 25#include <linux/dma-mapping.h> 26#include <linux/device.h> 27#include <linux/dmi.h> 28#include <linux/gfp.h> 29#include <scsi/scsi_host.h> 30#include <scsi/scsi_cmnd.h> 31#include <linux/libata.h> 32#include <linux/ahci-remap.h> 33#include <linux/io-64-nonatomic-lo-hi.h> 34#include "ahci.h" 35 36#define DRV_NAME "ahci" 37#define DRV_VERSION "3.0" 38 39enum { 40 AHCI_PCI_BAR_STA2X11 = 0, 41 AHCI_PCI_BAR_CAVIUM = 0, 42 AHCI_PCI_BAR_LOONGSON = 0, 43 AHCI_PCI_BAR_ENMOTUS = 2, 44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4, 45 AHCI_PCI_BAR_STANDARD = 5, 46}; 47 48enum board_ids { 49 /* board IDs by feature in alphabetical order */ 50 board_ahci, 51 board_ahci_43bit_dma, 52 board_ahci_ign_iferr, 53 board_ahci_no_debounce_delay, 54 board_ahci_no_msi, 55 /* 56 * board_ahci_pcs_quirk is for legacy Intel platforms. 57 * Modern Intel platforms should use board_ahci instead. 58 * (Some modern Intel platforms might have been added with 59 * board_ahci_pcs_quirk, however, we cannot change them to board_ahci 60 * without testing that the platform actually works without the quirk.) 61 */ 62 board_ahci_pcs_quirk, 63 board_ahci_pcs_quirk_no_devslp, 64 board_ahci_pcs_quirk_no_sntf, 65 board_ahci_yes_fbs, 66 board_ahci_yes_fbs_atapi_dma, 67 68 /* board IDs for specific chipsets in alphabetical order */ 69 board_ahci_al, 70 board_ahci_avn, 71 board_ahci_jmb585, 72 board_ahci_mcp65, 73 board_ahci_mcp77, 74 board_ahci_mcp89, 75 board_ahci_mv, 76 board_ahci_sb600, 77 board_ahci_sb700, /* for SB700 and SB800 */ 78 board_ahci_vt8251, 79 80 /* aliases */ 81 board_ahci_mcp_linux = board_ahci_mcp65, 82 board_ahci_mcp67 = board_ahci_mcp65, 83 board_ahci_mcp73 = board_ahci_mcp65, 84 board_ahci_mcp79 = board_ahci_mcp77, 85}; 86 87static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 88static void ahci_remove_one(struct pci_dev *dev); 89static void ahci_shutdown_one(struct pci_dev *dev); 90static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv); 91static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 92 unsigned long deadline); 93static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 94 unsigned long deadline); 95static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 96static bool is_mcp89_apple(struct pci_dev *pdev); 97static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 98 unsigned long deadline); 99#ifdef CONFIG_PM 100static int ahci_pci_device_runtime_suspend(struct device *dev); 101static int ahci_pci_device_runtime_resume(struct device *dev); 102#ifdef CONFIG_PM_SLEEP 103static int ahci_pci_device_suspend(struct device *dev); 104static int ahci_pci_device_resume(struct device *dev); 105#endif 106#endif /* CONFIG_PM */ 107 108static const struct scsi_host_template ahci_sht = { 109 AHCI_SHT("ahci"), 110}; 111 112static struct ata_port_operations ahci_vt8251_ops = { 113 .inherits = &ahci_ops, 114 .reset.hardreset = ahci_vt8251_hardreset, 115}; 116 117static struct ata_port_operations ahci_p5wdh_ops = { 118 .inherits = &ahci_ops, 119 .reset.hardreset = ahci_p5wdh_hardreset, 120}; 121 122static struct ata_port_operations ahci_avn_ops = { 123 .inherits = &ahci_ops, 124 .reset.hardreset = ahci_avn_hardreset, 125}; 126 127static const struct ata_port_info ahci_port_info[] = { 128 /* by features */ 129 [board_ahci] = { 130 .flags = AHCI_FLAG_COMMON, 131 .pio_mask = ATA_PIO4, 132 .udma_mask = ATA_UDMA6, 133 .port_ops = &ahci_ops, 134 }, 135 [board_ahci_43bit_dma] = { 136 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY), 137 .flags = AHCI_FLAG_COMMON, 138 .pio_mask = ATA_PIO4, 139 .udma_mask = ATA_UDMA6, 140 .port_ops = &ahci_ops, 141 }, 142 [board_ahci_ign_iferr] = { 143 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 144 .flags = AHCI_FLAG_COMMON, 145 .pio_mask = ATA_PIO4, 146 .udma_mask = ATA_UDMA6, 147 .port_ops = &ahci_ops, 148 }, 149 [board_ahci_no_debounce_delay] = { 150 .flags = AHCI_FLAG_COMMON, 151 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY, 152 .pio_mask = ATA_PIO4, 153 .udma_mask = ATA_UDMA6, 154 .port_ops = &ahci_ops, 155 }, 156 [board_ahci_no_msi] = { 157 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 158 .flags = AHCI_FLAG_COMMON, 159 .pio_mask = ATA_PIO4, 160 .udma_mask = ATA_UDMA6, 161 .port_ops = &ahci_ops, 162 }, 163 [board_ahci_pcs_quirk] = { 164 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK), 165 .flags = AHCI_FLAG_COMMON, 166 .pio_mask = ATA_PIO4, 167 .udma_mask = ATA_UDMA6, 168 .port_ops = &ahci_ops, 169 }, 170 [board_ahci_pcs_quirk_no_devslp] = { 171 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK | 172 AHCI_HFLAG_NO_DEVSLP), 173 .flags = AHCI_FLAG_COMMON, 174 .pio_mask = ATA_PIO4, 175 .udma_mask = ATA_UDMA6, 176 .port_ops = &ahci_ops, 177 }, 178 [board_ahci_pcs_quirk_no_sntf] = { 179 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK | 180 AHCI_HFLAG_NO_SNTF), 181 .flags = AHCI_FLAG_COMMON, 182 .pio_mask = ATA_PIO4, 183 .udma_mask = ATA_UDMA6, 184 .port_ops = &ahci_ops, 185 }, 186 [board_ahci_yes_fbs] = { 187 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 188 .flags = AHCI_FLAG_COMMON, 189 .pio_mask = ATA_PIO4, 190 .udma_mask = ATA_UDMA6, 191 .port_ops = &ahci_ops, 192 }, 193 [board_ahci_yes_fbs_atapi_dma] = { 194 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS | 195 AHCI_HFLAG_ATAPI_DMA_QUIRK), 196 .flags = AHCI_FLAG_COMMON, 197 .pio_mask = ATA_PIO4, 198 .udma_mask = ATA_UDMA6, 199 .port_ops = &ahci_ops, 200 }, 201 /* by chipsets */ 202 [board_ahci_al] = { 203 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI), 204 .flags = AHCI_FLAG_COMMON, 205 .pio_mask = ATA_PIO4, 206 .udma_mask = ATA_UDMA6, 207 .port_ops = &ahci_ops, 208 }, 209 [board_ahci_avn] = { 210 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK), 211 .flags = AHCI_FLAG_COMMON, 212 .pio_mask = ATA_PIO4, 213 .udma_mask = ATA_UDMA6, 214 .port_ops = &ahci_avn_ops, 215 }, 216 /* JMicron JMB582/585: 64-bit DMA is broken, force 32-bit */ 217 [board_ahci_jmb585] = { 218 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR | 219 AHCI_HFLAG_32BIT_ONLY), 220 .flags = AHCI_FLAG_COMMON, 221 .pio_mask = ATA_PIO4, 222 .udma_mask = ATA_UDMA6, 223 .port_ops = &ahci_ops, 224 }, 225 [board_ahci_mcp65] = { 226 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 227 AHCI_HFLAG_YES_NCQ), 228 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 229 .pio_mask = ATA_PIO4, 230 .udma_mask = ATA_UDMA6, 231 .port_ops = &ahci_ops, 232 }, 233 [board_ahci_mcp77] = { 234 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 235 .flags = AHCI_FLAG_COMMON, 236 .pio_mask = ATA_PIO4, 237 .udma_mask = ATA_UDMA6, 238 .port_ops = &ahci_ops, 239 }, 240 [board_ahci_mcp89] = { 241 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 242 .flags = AHCI_FLAG_COMMON, 243 .pio_mask = ATA_PIO4, 244 .udma_mask = ATA_UDMA6, 245 .port_ops = &ahci_ops, 246 }, 247 [board_ahci_mv] = { 248 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 249 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 250 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 251 .pio_mask = ATA_PIO4, 252 .udma_mask = ATA_UDMA6, 253 .port_ops = &ahci_ops, 254 }, 255 [board_ahci_sb600] = { 256 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 257 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 258 AHCI_HFLAG_32BIT_ONLY), 259 .flags = AHCI_FLAG_COMMON, 260 .pio_mask = ATA_PIO4, 261 .udma_mask = ATA_UDMA6, 262 .port_ops = &ahci_pmp_retry_srst_ops, 263 }, 264 [board_ahci_sb700] = { /* for SB700 and SB800 */ 265 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 266 .flags = AHCI_FLAG_COMMON, 267 .pio_mask = ATA_PIO4, 268 .udma_mask = ATA_UDMA6, 269 .port_ops = &ahci_pmp_retry_srst_ops, 270 }, 271 [board_ahci_vt8251] = { 272 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 273 .flags = AHCI_FLAG_COMMON, 274 .pio_mask = ATA_PIO4, 275 .udma_mask = ATA_UDMA6, 276 .port_ops = &ahci_vt8251_ops, 277 }, 278}; 279 280static const struct pci_device_id ahci_pci_tbl[] = { 281 /* Intel */ 282 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci_pcs_quirk }, /* Comet Lake PCH-H RAID */ 283 { PCI_VDEVICE(INTEL, 0x2652), board_ahci_pcs_quirk }, /* ICH6 */ 284 { PCI_VDEVICE(INTEL, 0x2653), board_ahci_pcs_quirk }, /* ICH6M */ 285 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci_pcs_quirk }, /* ICH7 */ 286 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci_pcs_quirk }, /* ICH7M */ 287 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci_pcs_quirk }, /* ICH7R */ 288 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 289 { PCI_VDEVICE(INTEL, 0x2681), board_ahci_pcs_quirk }, /* ESB2 */ 290 { PCI_VDEVICE(INTEL, 0x2682), board_ahci_pcs_quirk }, /* ESB2 */ 291 { PCI_VDEVICE(INTEL, 0x2683), board_ahci_pcs_quirk }, /* ESB2 */ 292 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci_pcs_quirk }, /* ICH7-M DH */ 293 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pcs_quirk }, /* ICH8 */ 294 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pcs_quirk_no_sntf }, /* ICH8/Lewisburg RAID*/ 295 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pcs_quirk }, /* ICH8 */ 296 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pcs_quirk }, /* ICH8M */ 297 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pcs_quirk }, /* ICH8M */ 298 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pcs_quirk }, /* ICH9 */ 299 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pcs_quirk }, /* ICH9 */ 300 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pcs_quirk }, /* ICH9 */ 301 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pcs_quirk }, /* ICH9 */ 302 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pcs_quirk }, /* ICH9 */ 303 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pcs_quirk }, /* ICH9M */ 304 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pcs_quirk }, /* ICH9M */ 305 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pcs_quirk }, /* ICH9M */ 306 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pcs_quirk }, /* ICH9M */ 307 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pcs_quirk }, /* ICH9M */ 308 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pcs_quirk }, /* ICH9 */ 309 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pcs_quirk }, /* ICH9M */ 310 { PCI_VDEVICE(INTEL, 0x502a), board_ahci_pcs_quirk }, /* Tolapai */ 311 { PCI_VDEVICE(INTEL, 0x502b), board_ahci_pcs_quirk }, /* Tolapai */ 312 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci_pcs_quirk }, /* ICH10 */ 313 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci_pcs_quirk }, /* ICH10 */ 314 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci_pcs_quirk }, /* ICH10 */ 315 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci_pcs_quirk }, /* PCH AHCI */ 316 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci_pcs_quirk }, /* PCH AHCI */ 317 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci_pcs_quirk }, /* PCH RAID */ 318 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci_pcs_quirk }, /* PCH RAID */ 319 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_pcs_quirk }, /* PCH M AHCI */ 320 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci_pcs_quirk }, /* PCH RAID */ 321 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_pcs_quirk }, /* PCH M RAID */ 322 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci_pcs_quirk }, /* PCH AHCI */ 323 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */ 324 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */ 325 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */ 326 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */ 327 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */ 328 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */ 329 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */ 330 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */ 331 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */ 332 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */ 333 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */ 334 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */ 335 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */ 336 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */ 337 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */ 338 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */ 339 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */ 340 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */ 341 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */ 342 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */ 343 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci_pcs_quirk }, /* CPT AHCI */ 344 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_pcs_quirk }, /* CPT M AHCI */ 345 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci_pcs_quirk }, /* CPT RAID */ 346 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_pcs_quirk }, /* CPT M RAID */ 347 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci_pcs_quirk }, /* CPT RAID */ 348 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci_pcs_quirk }, /* CPT RAID */ 349 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci_pcs_quirk }, /* PBG AHCI */ 350 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci_pcs_quirk }, /* PBG RAID */ 351 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci_pcs_quirk }, /* PBG RAID */ 352 { PCI_VDEVICE(INTEL, 0x2323), board_ahci_pcs_quirk }, /* DH89xxCC AHCI */ 353 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci_pcs_quirk }, /* Panther Point AHCI */ 354 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_pcs_quirk }, /* Panther M AHCI */ 355 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci_pcs_quirk }, /* Panther Point RAID */ 356 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci_pcs_quirk }, /* Panther Point RAID */ 357 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci_pcs_quirk }, /* Panther Point RAID */ 358 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_pcs_quirk }, /* Panther M RAID */ 359 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci_pcs_quirk }, /* Panther Point RAID */ 360 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci_pcs_quirk }, /* Lynx Point AHCI */ 361 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_pcs_quirk }, /* Lynx M AHCI */ 362 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci_pcs_quirk }, /* Lynx Point RAID */ 363 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_pcs_quirk }, /* Lynx M RAID */ 364 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci_pcs_quirk }, /* Lynx Point RAID */ 365 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_pcs_quirk }, /* Lynx M RAID */ 366 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci_pcs_quirk }, /* Lynx Point RAID */ 367 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_pcs_quirk }, /* Lynx M RAID */ 368 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_pcs_quirk }, /* Lynx LP AHCI */ 369 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_pcs_quirk }, /* Lynx LP AHCI */ 370 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 371 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 372 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 373 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 374 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 375 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 376 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_pcs_quirk }, /* Cannon Lake PCH-LP AHCI */ 377 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci_pcs_quirk }, /* Avoton AHCI */ 378 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci_pcs_quirk }, /* Avoton AHCI */ 379 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci_pcs_quirk }, /* Avoton RAID */ 380 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci_pcs_quirk }, /* Avoton RAID */ 381 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci_pcs_quirk }, /* Avoton RAID */ 382 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci_pcs_quirk }, /* Avoton RAID */ 383 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci_pcs_quirk }, /* Avoton RAID */ 384 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci_pcs_quirk }, /* Avoton RAID */ 385 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 386 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 387 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 388 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 389 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 390 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 391 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 392 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 393 { PCI_VDEVICE(INTEL, 0x2823), board_ahci_pcs_quirk }, /* Wellsburg/Lewisburg AHCI*/ 394 { PCI_VDEVICE(INTEL, 0x2826), board_ahci_pcs_quirk }, /* *burg SATA0 'RAID' */ 395 { PCI_VDEVICE(INTEL, 0x2827), board_ahci_pcs_quirk }, /* *burg SATA1 'RAID' */ 396 { PCI_VDEVICE(INTEL, 0x282f), board_ahci_pcs_quirk }, /* *burg SATA2 'RAID' */ 397 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */ 398 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */ 399 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */ 400 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */ 401 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci_pcs_quirk }, /* Wellsburg AHCI */ 402 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 403 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 404 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 405 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci_pcs_quirk }, /* Wellsburg AHCI */ 406 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 407 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 408 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 409 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci_pcs_quirk }, /* Coleto Creek AHCI */ 410 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_pcs_quirk }, /* Wildcat LP AHCI */ 411 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_pcs_quirk }, /* Wildcat LP RAID */ 412 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_pcs_quirk }, /* Wildcat LP RAID */ 413 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_pcs_quirk }, /* Wildcat LP RAID */ 414 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci_pcs_quirk }, /* 9 Series AHCI */ 415 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_pcs_quirk }, /* 9 Series M AHCI */ 416 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci_pcs_quirk }, /* 9 Series RAID */ 417 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_pcs_quirk }, /* 9 Series M RAID */ 418 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci_pcs_quirk }, /* 9 Series RAID */ 419 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_pcs_quirk }, /* 9 Series M RAID */ 420 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci_pcs_quirk }, /* 9 Series RAID */ 421 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_pcs_quirk }, /* 9 Series M RAID */ 422 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_pcs_quirk }, /* Sunrise LP AHCI */ 423 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_pcs_quirk }, /* Sunrise LP RAID */ 424 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_pcs_quirk }, /* Sunrise LP RAID */ 425 { PCI_VDEVICE(INTEL, 0xa102), board_ahci_pcs_quirk }, /* Sunrise Point-H AHCI */ 426 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_pcs_quirk }, /* Sunrise M AHCI */ 427 { PCI_VDEVICE(INTEL, 0xa105), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */ 428 { PCI_VDEVICE(INTEL, 0xa106), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */ 429 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_pcs_quirk }, /* Sunrise M RAID */ 430 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */ 431 { PCI_VDEVICE(INTEL, 0xa182), board_ahci_pcs_quirk }, /* Lewisburg AHCI*/ 432 { PCI_VDEVICE(INTEL, 0xa186), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 433 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 434 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 435 { PCI_VDEVICE(INTEL, 0xa202), board_ahci_pcs_quirk }, /* Lewisburg AHCI*/ 436 { PCI_VDEVICE(INTEL, 0xa206), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 437 { PCI_VDEVICE(INTEL, 0xa252), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 438 { PCI_VDEVICE(INTEL, 0xa256), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 439 { PCI_VDEVICE(INTEL, 0xa356), board_ahci_pcs_quirk }, /* Cannon Lake PCH-H RAID */ 440 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci_pcs_quirk }, /* Comet Lake-H RAID */ 441 { PCI_VDEVICE(INTEL, 0xa386), board_ahci_pcs_quirk }, /* Comet Lake PCH-V RAID */ 442 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_pcs_quirk }, /* Bay Trail AHCI */ 443 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_pcs_quirk_no_devslp }, /* Bay Trail AHCI */ 444 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_pcs_quirk }, /* Cherry Tr. AHCI */ 445 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_pcs_quirk }, /* ApolloLake AHCI */ 446 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_pcs_quirk }, /* Ice Lake LP AHCI */ 447 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_pcs_quirk }, /* Comet Lake PCH-U AHCI */ 448 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_pcs_quirk }, /* Comet Lake PCH RAID */ 449 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */ 450 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_pcs_quirk }, /* Elkhart Lake AHCI */ 451 452 /* JMicron JMB582/585: force 32-bit DMA (broken 64-bit implementation) */ 453 { PCI_VDEVICE(JMICRON, 0x0582), board_ahci_jmb585 }, 454 { PCI_VDEVICE(JMICRON, 0x0585), board_ahci_jmb585 }, 455 456 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 457 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 458 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 459 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 460 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 461 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 462 /* May need to update quirk_jmicron_async_suspend() for additions */ 463 464 /* ATI */ 465 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 466 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 467 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 468 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 469 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 470 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 471 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 472 473 /* Amazon's Annapurna Labs support */ 474 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031), 475 .class = PCI_CLASS_STORAGE_SATA_AHCI, 476 .class_mask = 0xffffff, 477 board_ahci_al }, 478 /* AMD */ 479 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 480 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */ 481 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 482 { PCI_VDEVICE(AMD, 0x7901), board_ahci }, /* AMD Green Sardine */ 483 /* AMD is using RAID class only for ahci controllers */ 484 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 485 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 486 487 /* Dell S140/S150 */ 488 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID, 489 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci_pcs_quirk }, 490 491 /* VIA */ 492 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 493 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 494 495 /* NVIDIA */ 496 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 497 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 498 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 499 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 500 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 501 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 502 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 503 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 504 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 505 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 506 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 507 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 508 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 509 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 510 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 511 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 512 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 513 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 514 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 515 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 516 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 517 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 518 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 519 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 520 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 521 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 522 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 523 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 524 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 525 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 526 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 527 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 528 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 529 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 530 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 531 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 532 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 533 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 534 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 535 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 536 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 537 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 538 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 539 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 540 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 541 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 542 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 543 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 544 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 545 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 546 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 547 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 548 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 549 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 550 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 551 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 552 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 553 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 554 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 555 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 556 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 557 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 558 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 559 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 560 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 561 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 562 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 563 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 564 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 565 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 566 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 567 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 568 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 569 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 570 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 571 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 572 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 573 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 574 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 575 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 576 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 577 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 578 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 579 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 580 581 /* SiS */ 582 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 583 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 584 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 585 586 /* ST Microelectronics */ 587 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 588 589 /* Marvell */ 590 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 591 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 592 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 593 .class = PCI_CLASS_STORAGE_SATA_AHCI, 594 .class_mask = 0xffffff, 595 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 596 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 597 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 598 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 599 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 600 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 601 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 602 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 603 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 604 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 605 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 606 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 607 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 608 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 609 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 610 .driver_data = board_ahci_yes_fbs }, 611 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 612 .driver_data = board_ahci_yes_fbs }, 613 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 614 .driver_data = board_ahci_yes_fbs }, 615 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9215), 616 .driver_data = board_ahci_yes_fbs_atapi_dma }, 617 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 618 .driver_data = board_ahci_yes_fbs }, 619 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235), 620 .driver_data = board_ahci_no_debounce_delay }, 621 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ 622 .driver_data = board_ahci_yes_fbs }, 623 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ 624 .driver_data = board_ahci_yes_fbs }, 625 626 /* Promise */ 627 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 628 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 629 630 /* ASMedia */ 631 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma }, /* ASM1060 */ 632 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci_43bit_dma }, /* ASM1060 */ 633 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */ 634 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */ 635 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma }, /* ASM1061R */ 636 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci_43bit_dma }, /* ASM1062R */ 637 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma }, /* ASM1062+JMB575 */ 638 { PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */ 639 { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */ 640 { PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */ 641 { PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */ 642 { PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci }, /* ASM1166 */ 643 644 /* 645 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 646 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 647 */ 648 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_no_msi }, 649 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_no_msi }, 650 651 /* Enmotus */ 652 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 653 654 /* Loongson */ 655 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci }, 656 657 /* Generic, PCI class code for AHCI */ 658 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 659 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 660 661 { } /* terminate list */ 662}; 663 664static const struct dev_pm_ops ahci_pci_pm_ops = { 665 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) 666 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, 667 ahci_pci_device_runtime_resume, NULL) 668}; 669 670static struct pci_driver ahci_pci_driver = { 671 .name = DRV_NAME, 672 .id_table = ahci_pci_tbl, 673 .probe = ahci_init_one, 674 .remove = ahci_remove_one, 675 .shutdown = ahci_shutdown_one, 676 .driver = { 677 .pm = &ahci_pci_pm_ops, 678 }, 679}; 680 681#if IS_ENABLED(CONFIG_PATA_MARVELL) 682static int marvell_enable; 683#else 684static int marvell_enable = 1; 685#endif 686module_param(marvell_enable, int, 0644); 687MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 688 689static int mobile_lpm_policy = -1; 690module_param(mobile_lpm_policy, int, 0644); 691MODULE_PARM_DESC(mobile_lpm_policy, 692 "Default LPM policy. Despite its name, this parameter applies " 693 "to all chipsets, including desktop and server chipsets"); 694 695static char *ahci_mask_port_map; 696module_param_named(mask_port_map, ahci_mask_port_map, charp, 0444); 697MODULE_PARM_DESC(mask_port_map, 698 "32-bits port map masks to ignore controllers ports. " 699 "Valid values are: " 700 "\"<mask>\" to apply the same mask to all AHCI controller " 701 "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to " 702 "specify different masks for the controllers specified, " 703 "where <pci_dev> is the PCI ID of an AHCI controller in the " 704 "form \"domain:bus:dev.func\""); 705 706static char *ahci_mask_port_ext; 707module_param_named(mask_port_ext, ahci_mask_port_ext, charp, 0444); 708MODULE_PARM_DESC(mask_port_ext, 709 "32-bits mask to ignore the external/hotplug capability of ports. " 710 "Valid values are: " 711 "\"<mask>\" to apply the same mask to all AHCI controller " 712 "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to " 713 "specify different masks for the controllers specified, " 714 "where <pci_dev> is the PCI ID of an AHCI controller in the " 715 "form \"domain:bus:dev.func\""); 716 717static u32 ahci_port_mask(struct device *dev, char *mask_s) 718{ 719 unsigned int mask; 720 721 if (kstrtouint(mask_s, 0, &mask)) { 722 dev_err(dev, "Invalid port map mask\n"); 723 return 0; 724 } 725 726 return mask; 727} 728 729static u32 ahci_get_port_mask(struct device *dev, char *mask_p) 730{ 731 char *param, *end, *str, *mask_s; 732 char *name; 733 u32 mask = 0; 734 735 if (!mask_p || !strlen(mask_p)) 736 return 0; 737 738 str = kstrdup(mask_p, GFP_KERNEL); 739 if (!str) 740 return 0; 741 742 /* Handle single mask case */ 743 if (!strchr(str, '=')) { 744 mask = ahci_port_mask(dev, str); 745 goto free; 746 } 747 748 /* 749 * Mask list case: parse the parameter to get the mask only if 750 * the device name matches. 751 */ 752 param = str; 753 end = param + strlen(param); 754 while (param && param < end && *param) { 755 name = param; 756 param = strchr(name, '='); 757 if (!param) 758 break; 759 760 *param = '\0'; 761 param++; 762 if (param >= end) 763 break; 764 765 if (strcmp(dev_name(dev), name) != 0) { 766 param = strchr(param, ','); 767 if (param) 768 param++; 769 continue; 770 } 771 772 mask_s = param; 773 param = strchr(mask_s, ','); 774 if (param) { 775 *param = '\0'; 776 param++; 777 } 778 779 mask = ahci_port_mask(dev, mask_s); 780 } 781 782free: 783 kfree(str); 784 785 return mask; 786} 787 788static void ahci_pci_save_initial_config(struct pci_dev *pdev, 789 struct ahci_host_priv *hpriv) 790{ 791 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 792 dev_info(&pdev->dev, "JMB361 has only one port\n"); 793 hpriv->saved_port_map = 1; 794 } 795 796 /* 797 * Temporary Marvell 6145 hack: PATA port presence 798 * is asserted through the standard AHCI port 799 * presence register, as bit 4 (counting from 0) 800 */ 801 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 802 if (pdev->device == 0x6121) 803 hpriv->mask_port_map = 0x3; 804 else 805 hpriv->mask_port_map = 0xf; 806 dev_info(&pdev->dev, 807 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 808 } 809 810 /* Handle port map masks passed as module parameter. */ 811 hpriv->mask_port_map = 812 ahci_get_port_mask(&pdev->dev, ahci_mask_port_map); 813 hpriv->mask_port_ext = 814 ahci_get_port_mask(&pdev->dev, ahci_mask_port_ext); 815 816 ahci_save_initial_config(&pdev->dev, hpriv); 817} 818 819static int ahci_pci_reset_controller(struct ata_host *host) 820{ 821 struct pci_dev *pdev = to_pci_dev(host->dev); 822 struct ahci_host_priv *hpriv = host->private_data; 823 int rc; 824 825 rc = ahci_reset_controller(host); 826 if (rc) 827 return rc; 828 829 /* 830 * If platform firmware failed to enable ports, try to enable 831 * them here. 832 */ 833 ahci_intel_pcs_quirk(pdev, hpriv); 834 835 return 0; 836} 837 838static void ahci_pci_init_controller(struct ata_host *host) 839{ 840 struct ahci_host_priv *hpriv = host->private_data; 841 struct pci_dev *pdev = to_pci_dev(host->dev); 842 void __iomem *port_mmio; 843 u32 tmp; 844 int mv; 845 846 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 847 if (pdev->device == 0x6121) 848 mv = 2; 849 else 850 mv = 4; 851 port_mmio = __ahci_port_base(hpriv, mv); 852 853 writel(0, port_mmio + PORT_IRQ_MASK); 854 855 /* clear port IRQ */ 856 tmp = readl(port_mmio + PORT_IRQ_STAT); 857 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp); 858 if (tmp) 859 writel(tmp, port_mmio + PORT_IRQ_STAT); 860 } 861 862 ahci_init_controller(host); 863} 864 865static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 866 unsigned long deadline) 867{ 868 struct ata_port *ap = link->ap; 869 struct ahci_host_priv *hpriv = ap->host->private_data; 870 bool online; 871 int rc; 872 873 hpriv->stop_engine(ap); 874 875 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 876 deadline, &online, NULL); 877 878 hpriv->start_engine(ap); 879 880 /* vt8251 doesn't clear BSY on signature FIS reception, 881 * request follow-up softreset. 882 */ 883 return online ? -EAGAIN : rc; 884} 885 886static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 887 unsigned long deadline) 888{ 889 struct ata_port *ap = link->ap; 890 struct ahci_port_priv *pp = ap->private_data; 891 struct ahci_host_priv *hpriv = ap->host->private_data; 892 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 893 struct ata_taskfile tf; 894 bool online; 895 int rc; 896 897 hpriv->stop_engine(ap); 898 899 /* clear D2H reception area to properly wait for D2H FIS */ 900 ata_tf_init(link->device, &tf); 901 tf.status = ATA_BUSY; 902 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 903 904 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 905 deadline, &online, NULL); 906 907 hpriv->start_engine(ap); 908 909 /* The pseudo configuration device on SIMG4726 attached to 910 * ASUS P5W-DH Deluxe doesn't send signature FIS after 911 * hardreset if no device is attached to the first downstream 912 * port && the pseudo device locks up on SRST w/ PMP==0. To 913 * work around this, wait for !BSY only briefly. If BSY isn't 914 * cleared, perform CLO and proceed to IDENTIFY (achieved by 915 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 916 * 917 * Wait for two seconds. Devices attached to downstream port 918 * which can't process the following IDENTIFY after this will 919 * have to be reset again. For most cases, this should 920 * suffice while making probing snappish enough. 921 */ 922 if (online) { 923 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 924 ahci_check_ready); 925 if (rc) 926 ahci_kick_engine(ap); 927 } 928 return rc; 929} 930 931/* 932 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 933 * 934 * It has been observed with some SSDs that the timing of events in the 935 * link synchronization phase can leave the port in a state that can not 936 * be recovered by a SATA-hard-reset alone. The failing signature is 937 * SStatus.DET stuck at 1 ("Device presence detected but Phy 938 * communication not established"). It was found that unloading and 939 * reloading the driver when this problem occurs allows the drive 940 * connection to be recovered (DET advanced to 0x3). The critical 941 * component of reloading the driver is that the port state machines are 942 * reset by bouncing "port enable" in the AHCI PCS configuration 943 * register. So, reproduce that effect by bouncing a port whenever we 944 * see DET==1 after a reset. 945 */ 946static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 947 unsigned long deadline) 948{ 949 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context); 950 struct ata_port *ap = link->ap; 951 struct ahci_port_priv *pp = ap->private_data; 952 struct ahci_host_priv *hpriv = ap->host->private_data; 953 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 954 unsigned long tmo = deadline - jiffies; 955 struct ata_taskfile tf; 956 bool online; 957 int rc, i; 958 959 hpriv->stop_engine(ap); 960 961 for (i = 0; i < 2; i++) { 962 u16 val; 963 u32 sstatus; 964 int port = ap->port_no; 965 struct ata_host *host = ap->host; 966 struct pci_dev *pdev = to_pci_dev(host->dev); 967 968 /* clear D2H reception area to properly wait for D2H FIS */ 969 ata_tf_init(link->device, &tf); 970 tf.status = ATA_BUSY; 971 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 972 973 rc = sata_link_hardreset(link, timing, deadline, &online, 974 ahci_check_ready); 975 976 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 977 (sstatus & 0xf) != 1) 978 break; 979 980 ata_link_info(link, "avn bounce port%d\n", port); 981 982 pci_read_config_word(pdev, 0x92, &val); 983 val &= ~(1 << port); 984 pci_write_config_word(pdev, 0x92, val); 985 ata_msleep(ap, 1000); 986 val |= 1 << port; 987 pci_write_config_word(pdev, 0x92, val); 988 deadline += tmo; 989 } 990 991 hpriv->start_engine(ap); 992 993 if (online) 994 *class = ahci_dev_classify(ap); 995 996 return rc; 997} 998 999 1000#ifdef CONFIG_PM 1001static void ahci_pci_disable_interrupts(struct ata_host *host) 1002{ 1003 struct ahci_host_priv *hpriv = host->private_data; 1004 void __iomem *mmio = hpriv->mmio; 1005 u32 ctl; 1006 1007 /* AHCI spec rev1.1 section 8.3.3: 1008 * Software must disable interrupts prior to requesting a 1009 * transition of the HBA to D3 state. 1010 */ 1011 ctl = readl(mmio + HOST_CTL); 1012 ctl &= ~HOST_IRQ_EN; 1013 writel(ctl, mmio + HOST_CTL); 1014 readl(mmio + HOST_CTL); /* flush */ 1015} 1016 1017static int ahci_pci_device_runtime_suspend(struct device *dev) 1018{ 1019 struct pci_dev *pdev = to_pci_dev(dev); 1020 struct ata_host *host = pci_get_drvdata(pdev); 1021 1022 ahci_pci_disable_interrupts(host); 1023 return 0; 1024} 1025 1026static int ahci_pci_device_runtime_resume(struct device *dev) 1027{ 1028 struct pci_dev *pdev = to_pci_dev(dev); 1029 struct ata_host *host = pci_get_drvdata(pdev); 1030 int rc; 1031 1032 rc = ahci_pci_reset_controller(host); 1033 if (rc) 1034 return rc; 1035 ahci_pci_init_controller(host); 1036 return 0; 1037} 1038 1039#ifdef CONFIG_PM_SLEEP 1040static int ahci_pci_device_suspend(struct device *dev) 1041{ 1042 struct pci_dev *pdev = to_pci_dev(dev); 1043 struct ata_host *host = pci_get_drvdata(pdev); 1044 struct ahci_host_priv *hpriv = host->private_data; 1045 1046 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 1047 dev_err(&pdev->dev, 1048 "BIOS update required for suspend/resume\n"); 1049 return -EIO; 1050 } 1051 1052 ahci_pci_disable_interrupts(host); 1053 ata_host_suspend(host, PMSG_SUSPEND); 1054 return 0; 1055} 1056 1057static int ahci_pci_device_resume(struct device *dev) 1058{ 1059 struct pci_dev *pdev = to_pci_dev(dev); 1060 struct ata_host *host = pci_get_drvdata(pdev); 1061 int rc; 1062 1063 /* Apple BIOS helpfully mangles the registers on resume */ 1064 if (is_mcp89_apple(pdev)) 1065 ahci_mcp89_apple_enable(pdev); 1066 1067 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 1068 rc = ahci_pci_reset_controller(host); 1069 if (rc) 1070 return rc; 1071 1072 ahci_pci_init_controller(host); 1073 } 1074 1075 ata_host_resume(host); 1076 1077 return 0; 1078} 1079#endif 1080 1081#endif /* CONFIG_PM */ 1082 1083static int ahci_configure_dma_masks(struct pci_dev *pdev, 1084 struct ahci_host_priv *hpriv) 1085{ 1086 int dma_bits; 1087 int rc; 1088 1089 if (hpriv->cap & HOST_CAP_64) { 1090 dma_bits = 64; 1091 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY) 1092 dma_bits = 43; 1093 } else { 1094 dma_bits = 32; 1095 } 1096 1097 /* 1098 * If the device fixup already set the dma_mask to some non-standard 1099 * value, don't extend it here. This happens on STA2X11, for example. 1100 * 1101 * XXX: manipulating the DMA mask from platform code is completely 1102 * bogus, platform code should use dev->bus_dma_limit instead.. 1103 */ 1104 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 1105 return 0; 1106 1107 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits)); 1108 if (rc) 1109 dev_err(&pdev->dev, "DMA enable failed\n"); 1110 return rc; 1111} 1112 1113static void ahci_pci_print_info(struct ata_host *host) 1114{ 1115 struct pci_dev *pdev = to_pci_dev(host->dev); 1116 u16 cc; 1117 const char *scc_s; 1118 1119 pci_read_config_word(pdev, 0x0a, &cc); 1120 if (cc == PCI_CLASS_STORAGE_IDE) 1121 scc_s = "IDE"; 1122 else if (cc == PCI_CLASS_STORAGE_SATA) 1123 scc_s = "SATA"; 1124 else if (cc == PCI_CLASS_STORAGE_RAID) 1125 scc_s = "RAID"; 1126 else 1127 scc_s = "unknown"; 1128 1129 ahci_print_info(host, scc_s); 1130} 1131 1132/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 1133 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 1134 * support PMP and the 4726 either directly exports the device 1135 * attached to the first downstream port or acts as a hardware storage 1136 * controller and emulate a single ATA device (can be RAID 0/1 or some 1137 * other configuration). 1138 * 1139 * When there's no device attached to the first downstream port of the 1140 * 4726, "Config Disk" appears, which is a pseudo ATA device to 1141 * configure the 4726. However, ATA emulation of the device is very 1142 * lame. It doesn't send signature D2H Reg FIS after the initial 1143 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 1144 * 1145 * The following function works around the problem by always using 1146 * hardreset on the port and not depending on receiving signature FIS 1147 * afterward. If signature FIS isn't received soon, ATA class is 1148 * assumed without follow-up softreset. 1149 */ 1150static void ahci_p5wdh_workaround(struct ata_host *host) 1151{ 1152 static const struct dmi_system_id sysids[] = { 1153 { 1154 .ident = "P5W DH Deluxe", 1155 .matches = { 1156 DMI_MATCH(DMI_SYS_VENDOR, 1157 "ASUSTEK COMPUTER INC"), 1158 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 1159 }, 1160 }, 1161 { } 1162 }; 1163 struct pci_dev *pdev = to_pci_dev(host->dev); 1164 1165 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 1166 dmi_check_system(sysids)) { 1167 struct ata_port *ap = host->ports[1]; 1168 1169 dev_info(&pdev->dev, 1170 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 1171 1172 ap->ops = &ahci_p5wdh_ops; 1173 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 1174 } 1175} 1176 1177/* 1178 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 1179 * booting in BIOS compatibility mode. We restore the registers but not ID. 1180 */ 1181static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 1182{ 1183 u32 val; 1184 1185 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 1186 1187 pci_read_config_dword(pdev, 0xf8, &val); 1188 val |= 1 << 0x1b; 1189 /* the following changes the device ID, but appears not to affect function */ 1190 /* val = (val & ~0xf0000000) | 0x80000000; */ 1191 pci_write_config_dword(pdev, 0xf8, val); 1192 1193 pci_read_config_dword(pdev, 0x54c, &val); 1194 val |= 1 << 0xc; 1195 pci_write_config_dword(pdev, 0x54c, val); 1196 1197 pci_read_config_dword(pdev, 0x4a4, &val); 1198 val &= 0xff; 1199 val |= 0x01060100; 1200 pci_write_config_dword(pdev, 0x4a4, val); 1201 1202 pci_read_config_dword(pdev, 0x54c, &val); 1203 val &= ~(1 << 0xc); 1204 pci_write_config_dword(pdev, 0x54c, val); 1205 1206 pci_read_config_dword(pdev, 0xf8, &val); 1207 val &= ~(1 << 0x1b); 1208 pci_write_config_dword(pdev, 0xf8, val); 1209} 1210 1211static bool is_mcp89_apple(struct pci_dev *pdev) 1212{ 1213 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1214 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1215 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1216 pdev->subsystem_device == 0xcb89; 1217} 1218 1219/* only some SB600 ahci controllers can do 64bit DMA */ 1220static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1221{ 1222 static const struct dmi_system_id sysids[] = { 1223 /* 1224 * The oldest version known to be broken is 0901 and 1225 * working is 1501 which was released on 2007-10-26. 1226 * Enable 64bit DMA on 1501 and anything newer. 1227 * 1228 * Please read bko#9412 for more info. 1229 */ 1230 { 1231 .ident = "ASUS M2A-VM", 1232 .matches = { 1233 DMI_MATCH(DMI_BOARD_VENDOR, 1234 "ASUSTeK Computer INC."), 1235 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1236 }, 1237 .driver_data = "20071026", /* yyyymmdd */ 1238 }, 1239 /* 1240 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1241 * support 64bit DMA. 1242 * 1243 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1244 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1245 * This spelling mistake was fixed in BIOS version 1.5, so 1246 * 1.5 and later have the Manufacturer as 1247 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1248 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1249 * 1250 * BIOS versions earlier than 1.9 had a Board Product Name 1251 * DMI field of "MS-7376". This was changed to be 1252 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1253 * match on DMI_BOARD_NAME of "MS-7376". 1254 */ 1255 { 1256 .ident = "MSI K9A2 Platinum", 1257 .matches = { 1258 DMI_MATCH(DMI_BOARD_VENDOR, 1259 "MICRO-STAR INTER"), 1260 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1261 }, 1262 }, 1263 /* 1264 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1265 * 64bit DMA. 1266 * 1267 * This board also had the typo mentioned above in the 1268 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1269 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1270 */ 1271 { 1272 .ident = "MSI K9AGM2", 1273 .matches = { 1274 DMI_MATCH(DMI_BOARD_VENDOR, 1275 "MICRO-STAR INTER"), 1276 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1277 }, 1278 }, 1279 /* 1280 * All BIOS versions for the Asus M3A support 64bit DMA. 1281 * (all release versions from 0301 to 1206 were tested) 1282 */ 1283 { 1284 .ident = "ASUS M3A", 1285 .matches = { 1286 DMI_MATCH(DMI_BOARD_VENDOR, 1287 "ASUSTeK Computer INC."), 1288 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1289 }, 1290 }, 1291 { } 1292 }; 1293 const struct dmi_system_id *match; 1294 int year, month, date; 1295 char buf[9]; 1296 1297 match = dmi_first_match(sysids); 1298 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1299 !match) 1300 return false; 1301 1302 if (!match->driver_data) 1303 goto enable_64bit; 1304 1305 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1306 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1307 1308 if (strcmp(buf, match->driver_data) >= 0) 1309 goto enable_64bit; 1310 else { 1311 dev_warn(&pdev->dev, 1312 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1313 match->ident); 1314 return false; 1315 } 1316 1317enable_64bit: 1318 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1319 return true; 1320} 1321 1322static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1323{ 1324 static const struct dmi_system_id broken_systems[] = { 1325 { 1326 .ident = "HP Compaq nx6310", 1327 .matches = { 1328 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1329 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1330 }, 1331 /* PCI slot number of the controller */ 1332 .driver_data = (void *)0x1FUL, 1333 }, 1334 { 1335 .ident = "HP Compaq 6720s", 1336 .matches = { 1337 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1338 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1339 }, 1340 /* PCI slot number of the controller */ 1341 .driver_data = (void *)0x1FUL, 1342 }, 1343 1344 { } /* terminate list */ 1345 }; 1346 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1347 1348 if (dmi) { 1349 unsigned long slot = (unsigned long)dmi->driver_data; 1350 /* apply the quirk only to on-board controllers */ 1351 return slot == PCI_SLOT(pdev->devfn); 1352 } 1353 1354 return false; 1355} 1356 1357static bool ahci_broken_suspend(struct pci_dev *pdev) 1358{ 1359 static const struct dmi_system_id sysids[] = { 1360 /* 1361 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1362 * to the harddisk doesn't become online after 1363 * resuming from STR. Warn and fail suspend. 1364 * 1365 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1366 * 1367 * Use dates instead of versions to match as HP is 1368 * apparently recycling both product and version 1369 * strings. 1370 * 1371 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1372 */ 1373 { 1374 .ident = "dv4", 1375 .matches = { 1376 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1377 DMI_MATCH(DMI_PRODUCT_NAME, 1378 "HP Pavilion dv4 Notebook PC"), 1379 }, 1380 .driver_data = "20090105", /* F.30 */ 1381 }, 1382 { 1383 .ident = "dv5", 1384 .matches = { 1385 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1386 DMI_MATCH(DMI_PRODUCT_NAME, 1387 "HP Pavilion dv5 Notebook PC"), 1388 }, 1389 .driver_data = "20090506", /* F.16 */ 1390 }, 1391 { 1392 .ident = "dv6", 1393 .matches = { 1394 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1395 DMI_MATCH(DMI_PRODUCT_NAME, 1396 "HP Pavilion dv6 Notebook PC"), 1397 }, 1398 .driver_data = "20090423", /* F.21 */ 1399 }, 1400 { 1401 .ident = "HDX18", 1402 .matches = { 1403 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1404 DMI_MATCH(DMI_PRODUCT_NAME, 1405 "HP HDX18 Notebook PC"), 1406 }, 1407 .driver_data = "20090430", /* F.23 */ 1408 }, 1409 /* 1410 * Acer eMachines G725 has the same problem. BIOS 1411 * V1.03 is known to be broken. V3.04 is known to 1412 * work. Between, there are V1.06, V2.06 and V3.03 1413 * that we don't have much idea about. For now, 1414 * assume that anything older than V3.04 is broken. 1415 * 1416 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1417 */ 1418 { 1419 .ident = "G725", 1420 .matches = { 1421 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1422 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1423 }, 1424 .driver_data = "20091216", /* V3.04 */ 1425 }, 1426 { } /* terminate list */ 1427 }; 1428 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1429 int year, month, date; 1430 char buf[9]; 1431 1432 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1433 return false; 1434 1435 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1436 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1437 1438 return strcmp(buf, dmi->driver_data) < 0; 1439} 1440 1441static bool ahci_broken_lpm(struct pci_dev *pdev) 1442{ 1443 /* 1444 * Platforms with LPM problems. 1445 * If driver_data is NULL, there is no existing BIOS version with 1446 * functioning LPM. 1447 * If driver_data is non-NULL, then driver_data contains the DMI BIOS 1448 * build date of the first BIOS version with functioning LPM (i.e. older 1449 * BIOS versions have broken LPM). 1450 */ 1451 static const struct dmi_system_id sysids[] = { 1452 { 1453 .matches = { 1454 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1455 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), 1456 }, 1457 .driver_data = "20180406", /* 1.31 */ 1458 }, 1459 { 1460 .matches = { 1461 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1462 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), 1463 }, 1464 .driver_data = "20180420", /* 1.28 */ 1465 }, 1466 { 1467 .matches = { 1468 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1469 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), 1470 }, 1471 .driver_data = "20180315", /* 1.33 */ 1472 }, 1473 { 1474 .matches = { 1475 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1476 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), 1477 }, 1478 .driver_data = "20180409", /* 2.35 */ 1479 }, 1480 { 1481 .matches = { 1482 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 1483 DMI_MATCH(DMI_PRODUCT_NAME, "ASUSPRO D840MB_M840SA"), 1484 }, 1485 /* 320 is broken, there is no known good version. */ 1486 }, 1487 { 1488 /* 1489 * AMD 500 Series Chipset SATA Controller [1022:43eb] 1490 * on this motherboard timeouts on ports 5 and 6 when 1491 * LPM is enabled, at least with WDC WD20EFAX-68FB5N0 1492 * hard drives. LPM with the same drive works fine on 1493 * all other ports on the same controller. 1494 */ 1495 .matches = { 1496 DMI_MATCH(DMI_BOARD_VENDOR, 1497 "ASUSTeK COMPUTER INC."), 1498 DMI_MATCH(DMI_BOARD_NAME, 1499 "ROG STRIX B550-F GAMING (WI-FI)"), 1500 }, 1501 /* 3621 is broken, there is no known good version. */ 1502 }, 1503 { } /* terminate list */ 1504 }; 1505 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1506 int year, month, date; 1507 char buf[9]; 1508 1509 if (!dmi) 1510 return false; 1511 1512 if (!dmi->driver_data) 1513 return true; 1514 1515 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1516 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1517 1518 return strcmp(buf, dmi->driver_data) < 0; 1519} 1520 1521static bool ahci_broken_online(struct pci_dev *pdev) 1522{ 1523#define ENCODE_BUSDEVFN(bus, slot, func) \ 1524 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1525 static const struct dmi_system_id sysids[] = { 1526 /* 1527 * There are several gigabyte boards which use 1528 * SIMG5723s configured as hardware RAID. Certain 1529 * 5723 firmware revisions shipped there keep the link 1530 * online but fail to answer properly to SRST or 1531 * IDENTIFY when no device is attached downstream 1532 * causing libata to retry quite a few times leading 1533 * to excessive detection delay. 1534 * 1535 * As these firmwares respond to the second reset try 1536 * with invalid device signature, considering unknown 1537 * sig as offline works around the problem acceptably. 1538 */ 1539 { 1540 .ident = "EP45-DQ6", 1541 .matches = { 1542 DMI_MATCH(DMI_BOARD_VENDOR, 1543 "Gigabyte Technology Co., Ltd."), 1544 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1545 }, 1546 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1547 }, 1548 { 1549 .ident = "EP45-DS5", 1550 .matches = { 1551 DMI_MATCH(DMI_BOARD_VENDOR, 1552 "Gigabyte Technology Co., Ltd."), 1553 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1554 }, 1555 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1556 }, 1557 { } /* terminate list */ 1558 }; 1559#undef ENCODE_BUSDEVFN 1560 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1561 unsigned int val; 1562 1563 if (!dmi) 1564 return false; 1565 1566 val = (unsigned long)dmi->driver_data; 1567 1568 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1569} 1570 1571#ifdef CONFIG_ATA_ACPI 1572static void ahci_gtf_filter_workaround(struct ata_host *host) 1573{ 1574 static const struct dmi_system_id sysids[] = { 1575 /* 1576 * Aspire 3810T issues a bunch of SATA enable commands 1577 * via _GTF including an invalid one and one which is 1578 * rejected by the device. Among the successful ones 1579 * is FPDMA non-zero offset enable which when enabled 1580 * only on the drive side leads to NCQ command 1581 * failures. Filter it out. 1582 */ 1583 { 1584 .ident = "Aspire 3810T", 1585 .matches = { 1586 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1587 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1588 }, 1589 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1590 }, 1591 { } 1592 }; 1593 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1594 unsigned int filter; 1595 int i; 1596 1597 if (!dmi) 1598 return; 1599 1600 filter = (unsigned long)dmi->driver_data; 1601 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1602 filter, dmi->ident); 1603 1604 for (i = 0; i < host->n_ports; i++) { 1605 struct ata_port *ap = host->ports[i]; 1606 struct ata_link *link; 1607 struct ata_device *dev; 1608 1609 ata_for_each_link(link, ap, EDGE) 1610 ata_for_each_dev(dev, link, ALL) 1611 dev->gtf_filter |= filter; 1612 } 1613} 1614#else 1615static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1616{} 1617#endif 1618 1619/* 1620 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected 1621 * as DUMMY, or detected but eventually get a "link down" and never get up 1622 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the 1623 * port_map may hold a value of 0x00. 1624 * 1625 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports 1626 * and can significantly reduce the occurrence of the problem. 1627 * 1628 * https://bugzilla.kernel.org/show_bug.cgi?id=189471 1629 */ 1630static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, 1631 struct pci_dev *pdev) 1632{ 1633 static const struct dmi_system_id sysids[] = { 1634 { 1635 .ident = "Acer Switch Alpha 12", 1636 .matches = { 1637 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1638 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") 1639 }, 1640 }, 1641 { } 1642 }; 1643 1644 if (dmi_check_system(sysids)) { 1645 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); 1646 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { 1647 hpriv->port_map = 0x7; 1648 hpriv->cap = 0xC734FF02; 1649 } 1650 } 1651} 1652 1653#ifdef CONFIG_ARM64 1654/* 1655 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. 1656 * Workaround is to make sure all pending IRQs are served before leaving 1657 * handler. 1658 */ 1659static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) 1660{ 1661 struct ata_host *host = dev_instance; 1662 struct ahci_host_priv *hpriv; 1663 unsigned int rc = 0; 1664 void __iomem *mmio; 1665 u32 irq_stat, irq_masked; 1666 unsigned int handled = 1; 1667 1668 hpriv = host->private_data; 1669 mmio = hpriv->mmio; 1670 irq_stat = readl(mmio + HOST_IRQ_STAT); 1671 if (!irq_stat) 1672 return IRQ_NONE; 1673 1674 do { 1675 irq_masked = irq_stat & hpriv->port_map; 1676 spin_lock(&host->lock); 1677 rc = ahci_handle_port_intr(host, irq_masked); 1678 if (!rc) 1679 handled = 0; 1680 writel(irq_stat, mmio + HOST_IRQ_STAT); 1681 irq_stat = readl(mmio + HOST_IRQ_STAT); 1682 spin_unlock(&host->lock); 1683 } while (irq_stat); 1684 1685 return IRQ_RETVAL(handled); 1686} 1687#endif 1688 1689static void ahci_remap_check(struct pci_dev *pdev, int bar, 1690 struct ahci_host_priv *hpriv) 1691{ 1692 int i; 1693 u32 cap; 1694 1695 /* 1696 * Check if this device might have remapped nvme devices. 1697 */ 1698 if (pdev->vendor != PCI_VENDOR_ID_INTEL || 1699 pci_resource_len(pdev, bar) < SZ_512K || 1700 bar != AHCI_PCI_BAR_STANDARD || 1701 !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) 1702 return; 1703 1704 cap = readq(hpriv->mmio + AHCI_REMAP_CAP); 1705 for (i = 0; i < AHCI_MAX_REMAP; i++) { 1706 if ((cap & (1 << i)) == 0) 1707 continue; 1708 if (readl(hpriv->mmio + ahci_remap_dcc(i)) 1709 != PCI_CLASS_STORAGE_EXPRESS) 1710 continue; 1711 1712 /* We've found a remapped device */ 1713 hpriv->remapped_nvme++; 1714 } 1715 1716 if (!hpriv->remapped_nvme) 1717 return; 1718 1719 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n", 1720 hpriv->remapped_nvme); 1721 dev_warn(&pdev->dev, 1722 "Switch your BIOS from RAID to AHCI mode to use them.\n"); 1723 1724 /* 1725 * Don't rely on the msi-x capability in the remap case, 1726 * share the legacy interrupt across ahci and remapped devices. 1727 */ 1728 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1729} 1730 1731static int ahci_get_irq_vector(struct ata_host *host, int port) 1732{ 1733 return pci_irq_vector(to_pci_dev(host->dev), port); 1734} 1735 1736static void ahci_init_irq(struct pci_dev *pdev, unsigned int n_ports, 1737 struct ahci_host_priv *hpriv) 1738{ 1739 int nvec; 1740 1741 if (hpriv->flags & AHCI_HFLAG_NO_MSI) { 1742 pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_INTX); 1743 return; 1744 } 1745 1746 /* 1747 * If number of MSIs is less than number of ports then Sharing Last 1748 * Message mode could be enforced. In this case assume that advantage 1749 * of multiple MSIs is negated and use single MSI mode instead. 1750 */ 1751 if (n_ports > 1) { 1752 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, 1753 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1754 if (nvec > 0) { 1755 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { 1756 hpriv->get_irq_vector = ahci_get_irq_vector; 1757 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1758 return; 1759 } 1760 1761 /* 1762 * Fallback to single MSI mode if the controller 1763 * enforced MRSM mode. 1764 */ 1765 printk(KERN_INFO 1766 "ahci: MRSM is on, fallback to single MSI\n"); 1767 pci_free_irq_vectors(pdev); 1768 } 1769 } 1770 1771 /* 1772 * If the host is not capable of supporting per-port vectors, fall 1773 * back to single MSI before finally attempting single MSI-X or 1774 * a legacy INTx. 1775 */ 1776 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1777 if (nvec == 1) 1778 return; 1779 pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX | PCI_IRQ_INTX); 1780} 1781 1782static void ahci_mark_external_port(struct ata_port *ap) 1783{ 1784 struct ahci_host_priv *hpriv = ap->host->private_data; 1785 void __iomem *port_mmio = ahci_port_base(ap); 1786 u32 tmp; 1787 1788 /* 1789 * Mark external ports (hotplug-capable, eSATA), unless we were asked to 1790 * ignore this feature. 1791 */ 1792 tmp = readl(port_mmio + PORT_CMD); 1793 if (((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) || 1794 (tmp & PORT_CMD_HPCP)) { 1795 if (hpriv->mask_port_ext & (1U << ap->port_no)) { 1796 ata_port_info(ap, 1797 "Ignoring external/hotplug capability\n"); 1798 return; 1799 } 1800 ap->pflags |= ATA_PFLAG_EXTERNAL; 1801 } 1802} 1803 1804static void ahci_update_initial_lpm_policy(struct ata_port *ap) 1805{ 1806 struct ahci_host_priv *hpriv = ap->host->private_data; 1807 int policy = CONFIG_SATA_MOBILE_LPM_POLICY; 1808 1809 /* 1810 * AHCI contains a known incompatibility between LPM and hot-plug 1811 * removal events, see 7.3.1 Hot Plug Removal Detection and Power 1812 * Management Interaction in AHCI 1.3.1. Therefore, do not enable 1813 * LPM if the port advertises itself as an external port. 1814 */ 1815 if (ap->pflags & ATA_PFLAG_EXTERNAL) { 1816 ap->flags |= ATA_FLAG_NO_LPM; 1817 ap->target_lpm_policy = ATA_LPM_MAX_POWER; 1818 return; 1819 } 1820 1821 /* If no Partial or no Slumber, we cannot support DIPM. */ 1822 if ((ap->host->flags & ATA_HOST_NO_PART) || 1823 (ap->host->flags & ATA_HOST_NO_SSC)) { 1824 ata_port_dbg(ap, "Host does not support DIPM\n"); 1825 ap->flags |= ATA_FLAG_NO_DIPM; 1826 } 1827 1828 /* If no LPM states are supported by the HBA, do not bother with LPM */ 1829 if ((ap->host->flags & ATA_HOST_NO_PART) && 1830 (ap->host->flags & ATA_HOST_NO_SSC) && 1831 (ap->host->flags & ATA_HOST_NO_DEVSLP)) { 1832 ata_port_dbg(ap, 1833 "No LPM states supported, forcing LPM max_power\n"); 1834 ap->flags |= ATA_FLAG_NO_LPM; 1835 ap->target_lpm_policy = ATA_LPM_MAX_POWER; 1836 return; 1837 } 1838 1839 /* user modified policy via module param */ 1840 if (mobile_lpm_policy != -1) { 1841 policy = mobile_lpm_policy; 1842 goto update_policy; 1843 } 1844 1845 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) { 1846 if (hpriv->cap & HOST_CAP_PART) 1847 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; 1848 else if (hpriv->cap & HOST_CAP_SSC) 1849 policy = ATA_LPM_MIN_POWER; 1850 } 1851 1852update_policy: 1853 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) 1854 ap->target_lpm_policy = policy; 1855} 1856 1857static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv) 1858{ 1859 u16 tmp16; 1860 1861 if (!(hpriv->flags & AHCI_HFLAG_INTEL_PCS_QUIRK)) 1862 return; 1863 1864 /* 1865 * port_map is determined from PORTS_IMPL PCI register which is 1866 * implemented as write or write-once register. If the register 1867 * isn't programmed, ahci automatically generates it from number 1868 * of ports, which is good enough for PCS programming. It is 1869 * otherwise expected that platform firmware enables the ports 1870 * before the OS boots. 1871 */ 1872 pci_read_config_word(pdev, PCS_6, &tmp16); 1873 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1874 tmp16 |= hpriv->port_map; 1875 pci_write_config_word(pdev, PCS_6, tmp16); 1876 } 1877} 1878 1879static ssize_t remapped_nvme_show(struct device *dev, 1880 struct device_attribute *attr, 1881 char *buf) 1882{ 1883 struct ata_host *host = dev_get_drvdata(dev); 1884 struct ahci_host_priv *hpriv = host->private_data; 1885 1886 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme); 1887} 1888 1889static DEVICE_ATTR_RO(remapped_nvme); 1890 1891static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1892{ 1893 unsigned int board_id = ent->driver_data; 1894 struct ata_port_info pi = ahci_port_info[board_id]; 1895 const struct ata_port_info *ppi[] = { &pi, NULL }; 1896 struct device *dev = &pdev->dev; 1897 struct ahci_host_priv *hpriv; 1898 struct ata_host *host; 1899 int n_ports, i, rc; 1900 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1901 1902 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1903 1904 ata_print_version_once(&pdev->dev, DRV_VERSION); 1905 1906 /* The AHCI driver can only drive the SATA ports, the PATA driver 1907 can drive them all so if both drivers are selected make sure 1908 AHCI stays out of the way */ 1909 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1910 return -ENODEV; 1911 1912 /* Apple BIOS on MCP89 prevents us using AHCI */ 1913 if (is_mcp89_apple(pdev)) 1914 ahci_mcp89_apple_enable(pdev); 1915 1916 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1917 * At the moment, we can only use the AHCI mode. Let the users know 1918 * that for SAS drives they're out of luck. 1919 */ 1920 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1921 dev_info(&pdev->dev, 1922 "PDC42819 can only drive SATA devices with this driver\n"); 1923 1924 /* Some devices use non-standard BARs */ 1925 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1926 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1927 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1928 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1929 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { 1930 if (pdev->device == 0xa01c) 1931 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1932 if (pdev->device == 0xa084) 1933 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; 1934 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) { 1935 if (pdev->device == 0x7a08) 1936 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON; 1937 } 1938 1939 /* acquire resources */ 1940 rc = pcim_enable_device(pdev); 1941 if (rc) 1942 return rc; 1943 1944 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1945 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1946 u8 map; 1947 1948 /* ICH6s share the same PCI ID for both piix and ahci 1949 * modes. Enabling ahci mode while MAP indicates 1950 * combined mode is a bad idea. Yield to ata_piix. 1951 */ 1952 pci_read_config_byte(pdev, ICH_MAP, &map); 1953 if (map & 0x3) { 1954 dev_info(&pdev->dev, 1955 "controller is in combined mode, can't enable AHCI mode\n"); 1956 return -ENODEV; 1957 } 1958 } 1959 1960 /* AHCI controllers often implement SFF compatible interface. 1961 * Grab all PCI BARs just in case. 1962 */ 1963 rc = pcim_request_all_regions(pdev, DRV_NAME); 1964 if (rc == -EBUSY) 1965 pcim_pin_device(pdev); 1966 if (rc) 1967 return rc; 1968 1969 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1970 if (!hpriv) 1971 return -ENOMEM; 1972 hpriv->flags |= (unsigned long)pi.private_data; 1973 1974 /* MCP65 revision A1 and A2 can't do MSI */ 1975 if (board_id == board_ahci_mcp65 && 1976 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1977 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1978 1979 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1980 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1981 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1982 1983 /* only some SB600s can do 64bit DMA */ 1984 if (ahci_sb600_enable_64bit(pdev)) 1985 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1986 1987 hpriv->mmio = pcim_iomap(pdev, ahci_pci_bar, 0); 1988 if (!hpriv->mmio) 1989 return -ENOMEM; 1990 1991 /* detect remapped nvme devices */ 1992 ahci_remap_check(pdev, ahci_pci_bar, hpriv); 1993 1994 sysfs_add_file_to_group(&pdev->dev.kobj, 1995 &dev_attr_remapped_nvme.attr, 1996 NULL); 1997 1998#ifdef CONFIG_ARM64 1999 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI && 2000 pdev->device == 0xa235 && 2001 pdev->revision < 0x30) 2002 hpriv->flags |= AHCI_HFLAG_NO_SXS; 2003 2004 if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 2005 hpriv->irq_handler = ahci_thunderx_irq_handler; 2006#endif 2007 2008 /* save initial config */ 2009 ahci_pci_save_initial_config(pdev, hpriv); 2010 2011 /* prepare host */ 2012 if (hpriv->cap & HOST_CAP_NCQ) { 2013 pi.flags |= ATA_FLAG_NCQ; 2014 /* 2015 * Auto-activate optimization is supposed to be 2016 * supported on all AHCI controllers indicating NCQ 2017 * capability, but it seems to be broken on some 2018 * chipsets including NVIDIAs. 2019 */ 2020 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 2021 pi.flags |= ATA_FLAG_FPDMA_AA; 2022 2023 /* 2024 * All AHCI controllers should be forward-compatible 2025 * with the new auxiliary field. This code should be 2026 * conditionalized if any buggy AHCI controllers are 2027 * encountered. 2028 */ 2029 pi.flags |= ATA_FLAG_FPDMA_AUX; 2030 } 2031 2032 if (hpriv->cap & HOST_CAP_PMP) 2033 pi.flags |= ATA_FLAG_PMP; 2034 2035 ahci_set_em_messages(hpriv, &pi); 2036 2037 if (ahci_broken_system_poweroff(pdev)) { 2038 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 2039 dev_info(&pdev->dev, 2040 "quirky BIOS, skipping spindown on poweroff\n"); 2041 } 2042 2043 if (ahci_broken_lpm(pdev)) { 2044 pi.flags |= ATA_FLAG_NO_LPM; 2045 dev_warn(&pdev->dev, 2046 "BIOS update required for Link Power Management support\n"); 2047 } 2048 2049 if (ahci_broken_suspend(pdev)) { 2050 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 2051 dev_warn(&pdev->dev, 2052 "BIOS update required for suspend/resume\n"); 2053 } 2054 2055 if (ahci_broken_online(pdev)) { 2056 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 2057 dev_info(&pdev->dev, 2058 "online status unreliable, applying workaround\n"); 2059 } 2060 2061 2062 /* Acer SA5-271 workaround modifies private_data */ 2063 acer_sa5_271_workaround(hpriv, pdev); 2064 2065 /* CAP.NP sometimes indicate the index of the last enabled 2066 * port, at other times, that of the last possible port, so 2067 * determining the maximum port number requires looking at 2068 * both CAP.NP and port_map. 2069 */ 2070 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 2071 2072 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 2073 if (!host) { 2074 rc = -ENOMEM; 2075 goto err_rm_sysfs_file; 2076 } 2077 host->private_data = hpriv; 2078 2079 ahci_init_irq(pdev, n_ports, hpriv); 2080 2081 hpriv->irq = pci_irq_vector(pdev, 0); 2082 2083 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 2084 host->flags |= ATA_HOST_PARALLEL_SCAN; 2085 else 2086 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 2087 2088 if (!(hpriv->cap & HOST_CAP_PART)) 2089 host->flags |= ATA_HOST_NO_PART; 2090 2091 if (!(hpriv->cap & HOST_CAP_SSC)) 2092 host->flags |= ATA_HOST_NO_SSC; 2093 2094 if (!(hpriv->cap2 & HOST_CAP2_SDS)) 2095 host->flags |= ATA_HOST_NO_DEVSLP; 2096 2097 if (pi.flags & ATA_FLAG_EM) 2098 ahci_reset_em(host); 2099 2100 for (i = 0; i < host->n_ports; i++) { 2101 struct ata_port *ap = host->ports[i]; 2102 2103 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 2104 ata_port_pbar_desc(ap, ahci_pci_bar, 2105 0x100 + ap->port_no * 0x80, "port"); 2106 2107 /* set enclosure management message type */ 2108 if (ap->flags & ATA_FLAG_EM) 2109 ap->em_message_type = hpriv->em_msg_type; 2110 2111 /* disabled/not-implemented port */ 2112 if (!(hpriv->port_map & (1 << i))) { 2113 ap->ops = &ata_dummy_port_ops; 2114 } else { 2115 ahci_mark_external_port(ap); 2116 ahci_update_initial_lpm_policy(ap); 2117 } 2118 } 2119 2120 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 2121 ahci_p5wdh_workaround(host); 2122 2123 /* apply gtf filter quirk */ 2124 ahci_gtf_filter_workaround(host); 2125 2126 /* initialize adapter */ 2127 rc = ahci_configure_dma_masks(pdev, hpriv); 2128 if (rc) 2129 goto err_rm_sysfs_file; 2130 2131 rc = ahci_pci_reset_controller(host); 2132 if (rc) 2133 goto err_rm_sysfs_file; 2134 2135 ahci_pci_init_controller(host); 2136 ahci_pci_print_info(host); 2137 2138 pci_set_master(pdev); 2139 2140 rc = ahci_host_activate(host, &ahci_sht); 2141 if (rc) 2142 goto err_rm_sysfs_file; 2143 2144 pm_runtime_put_noidle(&pdev->dev); 2145 return 0; 2146 2147err_rm_sysfs_file: 2148 sysfs_remove_file_from_group(&pdev->dev.kobj, 2149 &dev_attr_remapped_nvme.attr, NULL); 2150 return rc; 2151} 2152 2153static void ahci_shutdown_one(struct pci_dev *pdev) 2154{ 2155 ata_pci_shutdown_one(pdev); 2156} 2157 2158static void ahci_remove_one(struct pci_dev *pdev) 2159{ 2160 sysfs_remove_file_from_group(&pdev->dev.kobj, 2161 &dev_attr_remapped_nvme.attr, 2162 NULL); 2163 pm_runtime_get_noresume(&pdev->dev); 2164 ata_pci_remove_one(pdev); 2165} 2166 2167module_pci_driver(ahci_pci_driver); 2168 2169MODULE_AUTHOR("Jeff Garzik"); 2170MODULE_DESCRIPTION("AHCI SATA low-level driver"); 2171MODULE_LICENSE("GPL"); 2172MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 2173MODULE_VERSION(DRV_VERSION);
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