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lpss.c
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linux-6.19.14/drivers/acpi/x86/lpss.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * ACPI support for Intel Lynxpoint LPSS. 4 * 5 * Copyright (C) 2013, Intel Corporation 6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com> 8 */ 9 10#include <linux/acpi.h> 11#include <linux/clkdev.h> 12#include <linux/clk-provider.h> 13#include <linux/dmi.h> 14#include <linux/err.h> 15#include <linux/io.h> 16#include <linux/mutex.h> 17#include <linux/pci.h> 18#include <linux/platform_device.h> 19#include <linux/platform_data/x86/clk-lpss.h> 20#include <linux/platform_data/x86/pmc_atom.h> 21#include <linux/pm_domain.h> 22#include <linux/pm_runtime.h> 23#include <linux/pwm.h> 24#include <linux/pxa2xx_ssp.h> 25#include <linux/suspend.h> 26#include <linux/delay.h> 27 28#include "../internal.h" 29 30#ifdef CONFIG_X86_INTEL_LPSS 31 32#include <asm/cpu_device_id.h> 33#include <asm/intel-family.h> 34#include <asm/iosf_mbi.h> 35 36#define LPSS_ADDR(desc) ((unsigned long)&desc) 37 38#define LPSS_CLK_SIZE 0x04 39#define LPSS_LTR_SIZE 0x18 40 41/* Offsets relative to LPSS_PRIVATE_OFFSET */ 42#define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) 43#define LPSS_RESETS 0x04 44#define LPSS_RESETS_RESET_FUNC BIT(0) 45#define LPSS_RESETS_RESET_APB BIT(1) 46#define LPSS_GENERAL 0x08 47#define LPSS_GENERAL_LTR_MODE_SW BIT(2) 48#define LPSS_GENERAL_UART_RTS_OVRD BIT(3) 49#define LPSS_SW_LTR 0x10 50#define LPSS_AUTO_LTR 0x14 51#define LPSS_LTR_SNOOP_REQ BIT(15) 52#define LPSS_LTR_SNOOP_MASK 0x0000FFFF 53#define LPSS_LTR_SNOOP_LAT_1US 0x800 54#define LPSS_LTR_SNOOP_LAT_32US 0xC00 55#define LPSS_LTR_SNOOP_LAT_SHIFT 5 56#define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 57#define LPSS_LTR_MAX_VAL 0x3FF 58#define LPSS_TX_INT 0x20 59#define LPSS_TX_INT_MASK BIT(1) 60 61#define LPSS_PRV_REG_COUNT 9 62 63/* LPSS Flags */ 64#define LPSS_CLK BIT(0) 65#define LPSS_CLK_GATE BIT(1) 66#define LPSS_CLK_DIVIDER BIT(2) 67#define LPSS_LTR BIT(3) 68#define LPSS_SAVE_CTX BIT(4) 69/* 70 * For some devices the DSDT AML code for another device turns off the device 71 * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) 72 * as ctx register values. 73 * Luckily these devices always use the same ctx register values, so we can 74 * work around this by saving the ctx registers once on activation. 75 */ 76#define LPSS_SAVE_CTX_ONCE BIT(5) 77#define LPSS_NO_D3_DELAY BIT(6) 78 79struct lpss_private_data; 80 81struct lpss_device_desc { 82 unsigned int flags; 83 const char *clk_con_id; 84 unsigned int prv_offset; 85 size_t prv_size_override; 86 const struct property_entry *properties; 87 void (*setup)(struct lpss_private_data *pdata); 88 bool resume_from_noirq; 89}; 90 91static const struct lpss_device_desc lpss_dma_desc = { 92 .flags = LPSS_CLK, 93}; 94 95struct lpss_private_data { 96 struct acpi_device *adev; 97 void __iomem *mmio_base; 98 resource_size_t mmio_size; 99 unsigned int fixed_clk_rate; 100 struct clk *clk; 101 const struct lpss_device_desc *dev_desc; 102 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; 103}; 104 105/* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */ 106static u32 pmc_atom_d3_mask = 0xfe000ffe; 107 108/* LPSS run time quirks */ 109static unsigned int lpss_quirks; 110 111/* 112 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. 113 * 114 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover 115 * it can be powered off automatically whenever the last LPSS device goes down. 116 * In case of no power any access to the DMA controller will hang the system. 117 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as 118 * well as on ASuS T100TA transformer. 119 * 120 * This quirk overrides power state of entire LPSS island to keep DMA powered 121 * on whenever we have at least one other device in use. 122 */ 123#define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) 124 125/* UART Component Parameter Register */ 126#define LPSS_UART_CPR 0xF4 127#define LPSS_UART_CPR_AFCE BIT(4) 128 129static void lpss_uart_setup(struct lpss_private_data *pdata) 130{ 131 unsigned int offset; 132 u32 val; 133 134 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; 135 val = readl(pdata->mmio_base + offset); 136 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); 137 138 val = readl(pdata->mmio_base + LPSS_UART_CPR); 139 if (!(val & LPSS_UART_CPR_AFCE)) { 140 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; 141 val = readl(pdata->mmio_base + offset); 142 val |= LPSS_GENERAL_UART_RTS_OVRD; 143 writel(val, pdata->mmio_base + offset); 144 } 145} 146 147static void lpss_deassert_reset(struct lpss_private_data *pdata) 148{ 149 unsigned int offset; 150 u32 val; 151 152 offset = pdata->dev_desc->prv_offset + LPSS_RESETS; 153 val = readl(pdata->mmio_base + offset); 154 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; 155 writel(val, pdata->mmio_base + offset); 156} 157 158/* 159 * BYT PWM used for backlight control by the i915 driver on systems without 160 * the Crystal Cove PMIC. 161 */ 162static struct pwm_lookup byt_pwm_lookup[] = { 163 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", 164 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, 165 "pwm-lpss-platform"), 166}; 167 168static void byt_pwm_setup(struct lpss_private_data *pdata) 169{ 170 /* Only call pwm_add_table for the first PWM controller */ 171 if (acpi_dev_uid_match(pdata->adev, 1)) 172 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); 173} 174 175#define LPSS_I2C_ENABLE 0x6c 176 177static void byt_i2c_setup(struct lpss_private_data *pdata) 178{ 179 acpi_handle handle = pdata->adev->handle; 180 unsigned long long shared_host = 0; 181 acpi_status status; 182 u64 uid; 183 184 /* Expected to always be successful, but better safe then sorry */ 185 if (!acpi_dev_uid_to_integer(pdata->adev, &uid) && uid) { 186 /* Detect I2C bus shared with PUNIT and ignore its d3 status */ 187 status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); 188 if (ACPI_SUCCESS(status) && shared_host) 189 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1)); 190 } 191 192 lpss_deassert_reset(pdata); 193 194 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) 195 pdata->fixed_clk_rate = 133000000; 196 197 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); 198} 199 200/* 201 * BSW PWM1 is used for backlight control by the i915 driver 202 * BSW PWM2 is used for backlight control for fixed (etched into the glass) 203 * touch controls on some models. These touch-controls have specialized 204 * drivers which know they need the "pwm_soc_lpss_2" con-id. 205 */ 206static struct pwm_lookup bsw_pwm_lookup[] = { 207 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", 208 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, 209 "pwm-lpss-platform"), 210 PWM_LOOKUP_WITH_MODULE("80862289:00", 0, NULL, 211 "pwm_soc_lpss_2", 0, PWM_POLARITY_NORMAL, 212 "pwm-lpss-platform"), 213}; 214 215static void bsw_pwm_setup(struct lpss_private_data *pdata) 216{ 217 /* Only call pwm_add_table for the first PWM controller */ 218 if (acpi_dev_uid_match(pdata->adev, 1)) 219 pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); 220} 221 222static const struct property_entry lpt_spi_properties[] = { 223 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_LPT_SSP), 224 { } 225}; 226 227static const struct lpss_device_desc lpt_spi_dev_desc = { 228 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR 229 | LPSS_SAVE_CTX, 230 .prv_offset = 0x800, 231 .properties = lpt_spi_properties, 232}; 233 234static const struct lpss_device_desc lpt_i2c_dev_desc = { 235 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX, 236 .prv_offset = 0x800, 237}; 238 239static struct property_entry uart_properties[] = { 240 PROPERTY_ENTRY_U32("reg-io-width", 4), 241 PROPERTY_ENTRY_U32("reg-shift", 2), 242 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), 243 { }, 244}; 245 246static const struct lpss_device_desc lpt_uart_dev_desc = { 247 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR 248 | LPSS_SAVE_CTX, 249 .clk_con_id = "baudclk", 250 .prv_offset = 0x800, 251 .setup = lpss_uart_setup, 252 .properties = uart_properties, 253}; 254 255static const struct lpss_device_desc lpt_sdio_dev_desc = { 256 .flags = LPSS_LTR, 257 .prv_offset = 0x1000, 258 .prv_size_override = 0x1018, 259}; 260 261static const struct lpss_device_desc byt_pwm_dev_desc = { 262 .flags = LPSS_SAVE_CTX, 263 .prv_offset = 0x800, 264 .setup = byt_pwm_setup, 265}; 266 267static const struct lpss_device_desc bsw_pwm_dev_desc = { 268 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, 269 .prv_offset = 0x800, 270 .setup = bsw_pwm_setup, 271 .resume_from_noirq = true, 272}; 273 274static const struct lpss_device_desc bsw_pwm2_dev_desc = { 275 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, 276 .prv_offset = 0x800, 277 .resume_from_noirq = true, 278}; 279 280static const struct lpss_device_desc byt_uart_dev_desc = { 281 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 282 .clk_con_id = "baudclk", 283 .prv_offset = 0x800, 284 .setup = lpss_uart_setup, 285 .properties = uart_properties, 286}; 287 288static const struct lpss_device_desc bsw_uart_dev_desc = { 289 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 290 | LPSS_NO_D3_DELAY, 291 .clk_con_id = "baudclk", 292 .prv_offset = 0x800, 293 .setup = lpss_uart_setup, 294 .properties = uart_properties, 295}; 296 297static const struct property_entry byt_spi_properties[] = { 298 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BYT_SSP), 299 { } 300}; 301 302static const struct lpss_device_desc byt_spi_dev_desc = { 303 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 304 .prv_offset = 0x400, 305 .properties = byt_spi_properties, 306}; 307 308static const struct lpss_device_desc byt_sdio_dev_desc = { 309 .flags = LPSS_CLK, 310}; 311 312static const struct lpss_device_desc byt_i2c_dev_desc = { 313 .flags = LPSS_CLK | LPSS_SAVE_CTX, 314 .prv_offset = 0x800, 315 .setup = byt_i2c_setup, 316 .resume_from_noirq = true, 317}; 318 319static const struct lpss_device_desc bsw_i2c_dev_desc = { 320 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, 321 .prv_offset = 0x800, 322 .setup = byt_i2c_setup, 323 .resume_from_noirq = true, 324}; 325 326static const struct property_entry bsw_spi_properties[] = { 327 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BSW_SSP), 328 PROPERTY_ENTRY_U32("num-cs", 2), 329 { } 330}; 331 332static const struct lpss_device_desc bsw_spi_dev_desc = { 333 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 334 | LPSS_NO_D3_DELAY, 335 .prv_offset = 0x400, 336 .setup = lpss_deassert_reset, 337 .properties = bsw_spi_properties, 338}; 339 340static const struct x86_cpu_id lpss_cpu_ids[] = { 341 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, NULL), 342 X86_MATCH_VFM(INTEL_ATOM_AIRMONT, NULL), 343 {} 344}; 345 346#else 347 348#define LPSS_ADDR(desc) (0UL) 349 350#endif /* CONFIG_X86_INTEL_LPSS */ 351 352static const struct acpi_device_id acpi_lpss_device_ids[] = { 353 /* Generic LPSS devices */ 354 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, 355 356 /* Lynxpoint LPSS devices */ 357 { "INT33C0", LPSS_ADDR(lpt_spi_dev_desc) }, 358 { "INT33C1", LPSS_ADDR(lpt_spi_dev_desc) }, 359 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, 360 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, 361 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, 362 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, 363 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, 364 365 /* BayTrail LPSS devices */ 366 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, 367 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, 368 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, 369 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, 370 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, 371 372 /* Braswell LPSS devices */ 373 { "80862286", LPSS_ADDR(lpss_dma_desc) }, 374 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, 375 { "80862289", LPSS_ADDR(bsw_pwm2_dev_desc) }, 376 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, 377 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, 378 { "808622C0", LPSS_ADDR(lpss_dma_desc) }, 379 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, 380 381 /* Broadwell LPSS devices */ 382 { "INT3430", LPSS_ADDR(lpt_spi_dev_desc) }, 383 { "INT3431", LPSS_ADDR(lpt_spi_dev_desc) }, 384 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, 385 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, 386 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, 387 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, 388 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, 389 390 { } 391}; 392 393#ifdef CONFIG_X86_INTEL_LPSS 394 395/* LPSS main clock device. */ 396static struct platform_device *lpss_clk_dev; 397 398static inline void lpt_register_clock_device(void) 399{ 400 lpss_clk_dev = platform_device_register_simple("clk-lpss-atom", 401 PLATFORM_DEVID_NONE, 402 NULL, 0); 403} 404 405static int register_device_clock(struct acpi_device *adev, 406 struct lpss_private_data *pdata) 407{ 408 const struct lpss_device_desc *dev_desc = pdata->dev_desc; 409 const char *devname = dev_name(&adev->dev); 410 struct clk *clk; 411 struct lpss_clk_data *clk_data; 412 const char *parent, *clk_name; 413 void __iomem *prv_base; 414 415 if (!lpss_clk_dev) 416 lpt_register_clock_device(); 417 418 if (IS_ERR(lpss_clk_dev)) 419 return PTR_ERR(lpss_clk_dev); 420 421 clk_data = platform_get_drvdata(lpss_clk_dev); 422 if (!clk_data) 423 return -ENODEV; 424 clk = clk_data->clk; 425 426 if (!pdata->mmio_base 427 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) 428 return -ENODATA; 429 430 parent = clk_data->name; 431 prv_base = pdata->mmio_base + dev_desc->prv_offset; 432 433 if (pdata->fixed_clk_rate) { 434 clk = clk_register_fixed_rate(NULL, devname, parent, 0, 435 pdata->fixed_clk_rate); 436 goto out; 437 } 438 439 if (dev_desc->flags & LPSS_CLK_GATE) { 440 clk = clk_register_gate(NULL, devname, parent, 0, 441 prv_base, 0, 0, NULL); 442 parent = devname; 443 } 444 445 if (dev_desc->flags & LPSS_CLK_DIVIDER) { 446 /* Prevent division by zero */ 447 if (!readl(prv_base)) 448 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); 449 450 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); 451 if (!clk_name) 452 return -ENOMEM; 453 clk = clk_register_fractional_divider(NULL, clk_name, parent, 454 0, prv_base, 1, 15, 16, 15, 455 CLK_FRAC_DIVIDER_POWER_OF_TWO_PS, 456 NULL); 457 parent = clk_name; 458 459 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); 460 if (!clk_name) { 461 kfree(parent); 462 return -ENOMEM; 463 } 464 clk = clk_register_gate(NULL, clk_name, parent, 465 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, 466 prv_base, 31, 0, NULL); 467 kfree(parent); 468 kfree(clk_name); 469 } 470out: 471 if (IS_ERR(clk)) 472 return PTR_ERR(clk); 473 474 pdata->clk = clk; 475 clk_register_clkdev(clk, dev_desc->clk_con_id, devname); 476 return 0; 477} 478 479struct lpss_device_links { 480 const char *supplier_hid; 481 const char *supplier_uid; 482 const char *consumer_hid; 483 const char *consumer_uid; 484 u32 flags; 485 const struct dmi_system_id *dep_missing_ids; 486}; 487 488/* Please keep this list sorted alphabetically by vendor and model */ 489static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = { 490 { 491 .matches = { 492 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 493 DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"), 494 }, 495 }, 496 {} 497}; 498 499/* 500 * The _DEP method is used to identify dependencies but instead of creating 501 * device links for every handle in _DEP, only links in the following list are 502 * created. That is necessary because, in the general case, _DEP can refer to 503 * devices that might not have drivers, or that are on different buses, or where 504 * the supplier is not enumerated until after the consumer is probed. 505 */ 506static const struct lpss_device_links lpss_device_links[] = { 507 /* CHT External sdcard slot controller depends on PMIC I2C ctrl */ 508 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, 509 /* CHT iGPU depends on PMIC I2C controller */ 510 {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 511 /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */ 512 {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME, 513 i2c1_dep_missing_dmi_ids}, 514 /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */ 515 {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 516 /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */ 517 {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 518}; 519 520static bool acpi_lpss_is_supplier(struct acpi_device *adev, 521 const struct lpss_device_links *link) 522{ 523 return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid); 524} 525 526static bool acpi_lpss_is_consumer(struct acpi_device *adev, 527 const struct lpss_device_links *link) 528{ 529 return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid); 530} 531 532struct hid_uid { 533 const char *hid; 534 const char *uid; 535}; 536 537static int match_hid_uid(struct device *dev, const void *data) 538{ 539 struct acpi_device *adev = ACPI_COMPANION(dev); 540 const struct hid_uid *id = data; 541 542 if (!adev) 543 return 0; 544 545 return acpi_dev_hid_uid_match(adev, id->hid, id->uid); 546} 547 548static struct device *acpi_lpss_find_device(const char *hid, const char *uid) 549{ 550 struct device *dev; 551 552 struct hid_uid data = { 553 .hid = hid, 554 .uid = uid, 555 }; 556 557 dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); 558 if (dev) 559 return dev; 560 561 return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid); 562} 563 564static void acpi_lpss_link_consumer(struct device *dev1, 565 const struct lpss_device_links *link) 566{ 567 struct device *dev2; 568 569 dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); 570 if (!dev2) 571 return; 572 573 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) 574 || acpi_device_dep(ACPI_HANDLE(dev2), ACPI_HANDLE(dev1))) 575 device_link_add(dev2, dev1, link->flags); 576 577 put_device(dev2); 578} 579 580static void acpi_lpss_link_supplier(struct device *dev1, 581 const struct lpss_device_links *link) 582{ 583 struct device *dev2; 584 585 dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); 586 if (!dev2) 587 return; 588 589 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) 590 || acpi_device_dep(ACPI_HANDLE(dev1), ACPI_HANDLE(dev2))) 591 device_link_add(dev1, dev2, link->flags); 592 593 put_device(dev2); 594} 595 596static void acpi_lpss_create_device_links(struct acpi_device *adev, 597 struct platform_device *pdev) 598{ 599 int i; 600 601 for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { 602 const struct lpss_device_links *link = &lpss_device_links[i]; 603 604 if (acpi_lpss_is_supplier(adev, link)) 605 acpi_lpss_link_consumer(&pdev->dev, link); 606 607 if (acpi_lpss_is_consumer(adev, link)) 608 acpi_lpss_link_supplier(&pdev->dev, link); 609 } 610} 611 612static int acpi_lpss_create_device(struct acpi_device *adev, 613 const struct acpi_device_id *id) 614{ 615 const struct lpss_device_desc *dev_desc; 616 struct lpss_private_data *pdata; 617 struct resource_entry *rentry; 618 struct list_head resource_list; 619 struct platform_device *pdev; 620 int ret; 621 622 dev_desc = (const struct lpss_device_desc *)id->driver_data; 623 if (!dev_desc) 624 return -EINVAL; 625 626 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 627 if (!pdata) 628 return -ENOMEM; 629 630 INIT_LIST_HEAD(&resource_list); 631 ret = acpi_dev_get_memory_resources(adev, &resource_list); 632 if (ret < 0) 633 goto err_out; 634 635 rentry = list_first_entry_or_null(&resource_list, struct resource_entry, node); 636 if (rentry) { 637 if (dev_desc->prv_size_override) 638 pdata->mmio_size = dev_desc->prv_size_override; 639 else 640 pdata->mmio_size = resource_size(rentry->res); 641 pdata->mmio_base = ioremap(rentry->res->start, pdata->mmio_size); 642 } 643 644 acpi_dev_free_resource_list(&resource_list); 645 646 if (!pdata->mmio_base) { 647 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ 648 adev->pnp.type.platform_id = 0; 649 goto out_free; 650 } 651 652 pdata->adev = adev; 653 pdata->dev_desc = dev_desc; 654 655 if (dev_desc->setup) 656 dev_desc->setup(pdata); 657 658 if (dev_desc->flags & LPSS_CLK) { 659 ret = register_device_clock(adev, pdata); 660 if (ret) 661 goto out_free; 662 } 663 664 /* 665 * This works around a known issue in ACPI tables where LPSS devices 666 * have _PS0 and _PS3 without _PSC (and no power resources), so 667 * acpi_bus_init_power() will assume that the BIOS has put them into D0. 668 */ 669 acpi_device_fix_up_power(adev); 670 671 adev->driver_data = pdata; 672 pdev = acpi_create_platform_device(adev, dev_desc->properties); 673 if (IS_ERR_OR_NULL(pdev)) { 674 adev->driver_data = NULL; 675 ret = PTR_ERR(pdev); 676 goto err_out; 677 } 678 679 acpi_lpss_create_device_links(adev, pdev); 680 return 1; 681 682out_free: 683 /* Skip the device, but continue the namespace scan */ 684 ret = 0; 685err_out: 686 kfree(pdata); 687 return ret; 688} 689 690static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) 691{ 692 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 693} 694 695static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, 696 unsigned int reg) 697{ 698 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 699} 700 701static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) 702{ 703 struct acpi_device *adev = ACPI_COMPANION(dev); 704 struct lpss_private_data *pdata; 705 unsigned long flags; 706 int ret; 707 708 if (WARN_ON(!adev)) 709 return -ENODEV; 710 711 spin_lock_irqsave(&dev->power.lock, flags); 712 if (pm_runtime_suspended(dev)) { 713 ret = -EAGAIN; 714 goto out; 715 } 716 pdata = acpi_driver_data(adev); 717 if (WARN_ON(!pdata || !pdata->mmio_base)) { 718 ret = -ENODEV; 719 goto out; 720 } 721 *val = __lpss_reg_read(pdata, reg); 722 ret = 0; 723 724 out: 725 spin_unlock_irqrestore(&dev->power.lock, flags); 726 return ret; 727} 728 729static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, 730 char *buf) 731{ 732 u32 ltr_value = 0; 733 unsigned int reg; 734 int ret; 735 736 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; 737 ret = lpss_reg_read(dev, reg, <r_value); 738 if (ret) 739 return ret; 740 741 return sysfs_emit(buf, "%08x\n", ltr_value); 742} 743 744static ssize_t lpss_ltr_mode_show(struct device *dev, 745 struct device_attribute *attr, char *buf) 746{ 747 u32 ltr_mode = 0; 748 char *outstr; 749 int ret; 750 751 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); 752 if (ret) 753 return ret; 754 755 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; 756 return sprintf(buf, "%s\n", outstr); 757} 758 759static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); 760static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); 761static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); 762 763static struct attribute *lpss_attrs[] = { 764 &dev_attr_auto_ltr.attr, 765 &dev_attr_sw_ltr.attr, 766 &dev_attr_ltr_mode.attr, 767 NULL, 768}; 769 770static const struct attribute_group lpss_attr_group = { 771 .attrs = lpss_attrs, 772 .name = "lpss_ltr", 773}; 774 775static void acpi_lpss_set_ltr(struct device *dev, s32 val) 776{ 777 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 778 u32 ltr_mode, ltr_val; 779 780 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); 781 if (val < 0) { 782 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { 783 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; 784 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 785 } 786 return; 787 } 788 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; 789 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { 790 ltr_val |= LPSS_LTR_SNOOP_LAT_32US; 791 val = LPSS_LTR_MAX_VAL; 792 } else if (val > LPSS_LTR_MAX_VAL) { 793 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; 794 val >>= LPSS_LTR_SNOOP_LAT_SHIFT; 795 } else { 796 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; 797 } 798 ltr_val |= val; 799 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); 800 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { 801 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; 802 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 803 } 804} 805 806#ifdef CONFIG_PM 807/** 808 * acpi_lpss_save_ctx() - Save the private registers of LPSS device 809 * @dev: LPSS device 810 * @pdata: pointer to the private data of the LPSS device 811 * 812 * Most LPSS devices have private registers which may loose their context when 813 * the device is powered down. acpi_lpss_save_ctx() saves those registers into 814 * prv_reg_ctx array. 815 */ 816static void acpi_lpss_save_ctx(struct device *dev, 817 struct lpss_private_data *pdata) 818{ 819 unsigned int i; 820 821 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 822 unsigned long offset = i * sizeof(u32); 823 824 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); 825 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", 826 pdata->prv_reg_ctx[i], offset); 827 } 828} 829 830/** 831 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device 832 * @dev: LPSS device 833 * @pdata: pointer to the private data of the LPSS device 834 * 835 * Restores the registers that were previously stored with acpi_lpss_save_ctx(). 836 */ 837static void acpi_lpss_restore_ctx(struct device *dev, 838 struct lpss_private_data *pdata) 839{ 840 unsigned int i; 841 842 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 843 unsigned long offset = i * sizeof(u32); 844 845 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); 846 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", 847 pdata->prv_reg_ctx[i], offset); 848 } 849} 850 851static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) 852{ 853 /* 854 * The following delay is needed or the subsequent write operations may 855 * fail. The LPSS devices are actually PCI devices and the PCI spec 856 * expects 10ms delay before the device can be accessed after D3 to D0 857 * transition. However some platforms like BSW does not need this delay. 858 */ 859 unsigned int delay = 10; /* default 10ms delay */ 860 861 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) 862 delay = 0; 863 864 msleep(delay); 865} 866 867static int acpi_lpss_activate(struct device *dev) 868{ 869 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 870 int ret; 871 872 ret = acpi_dev_resume(dev); 873 if (ret) 874 return ret; 875 876 acpi_lpss_d3_to_d0_delay(pdata); 877 878 /* 879 * This is called only on ->probe() stage where a device is either in 880 * known state defined by BIOS or most likely powered off. Due to this 881 * we have to deassert reset line to be sure that ->probe() will 882 * recognize the device. 883 */ 884 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) 885 lpss_deassert_reset(pdata); 886 887 if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) 888 acpi_lpss_save_ctx(dev, pdata); 889 890 return 0; 891} 892 893static void acpi_lpss_dismiss(struct device *dev) 894{ 895 acpi_dev_suspend(dev, false); 896} 897 898/* IOSF SB for LPSS island */ 899#define LPSS_IOSF_UNIT_LPIOEP 0xA0 900#define LPSS_IOSF_UNIT_LPIO1 0xAB 901#define LPSS_IOSF_UNIT_LPIO2 0xAC 902 903#define LPSS_IOSF_PMCSR 0x84 904#define LPSS_PMCSR_D0 0 905#define LPSS_PMCSR_D3hot 3 906#define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) 907 908#define LPSS_IOSF_GPIODEF0 0x154 909#define LPSS_GPIODEF0_DMA1_D3 BIT(2) 910#define LPSS_GPIODEF0_DMA2_D3 BIT(3) 911#define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) 912#define LPSS_GPIODEF0_DMA_LLP BIT(13) 913 914static DEFINE_MUTEX(lpss_iosf_mutex); 915static bool lpss_iosf_d3_entered = true; 916 917static void lpss_iosf_enter_d3_state(void) 918{ 919 u32 value1 = 0; 920 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 921 u32 value2 = LPSS_PMCSR_D3hot; 922 u32 mask2 = LPSS_PMCSR_Dx_MASK; 923 /* 924 * PMC provides an information about actual status of the LPSS devices. 925 * Here we read the values related to LPSS power island, i.e. LPSS 926 * devices, excluding both LPSS DMA controllers, along with SCC domain. 927 */ 928 u32 func_dis, d3_sts_0, pmc_status; 929 int ret; 930 931 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); 932 if (ret) 933 return; 934 935 mutex_lock(&lpss_iosf_mutex); 936 937 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); 938 if (ret) 939 goto exit; 940 941 /* 942 * Get the status of entire LPSS power island per device basis. 943 * Shutdown both LPSS DMA controllers if and only if all other devices 944 * are already in D3hot. 945 */ 946 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask; 947 if (pmc_status) 948 goto exit; 949 950 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 951 LPSS_IOSF_PMCSR, value2, mask2); 952 953 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 954 LPSS_IOSF_PMCSR, value2, mask2); 955 956 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 957 LPSS_IOSF_GPIODEF0, value1, mask1); 958 959 lpss_iosf_d3_entered = true; 960 961exit: 962 mutex_unlock(&lpss_iosf_mutex); 963} 964 965static void lpss_iosf_exit_d3_state(void) 966{ 967 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | 968 LPSS_GPIODEF0_DMA_LLP; 969 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 970 u32 value2 = LPSS_PMCSR_D0; 971 u32 mask2 = LPSS_PMCSR_Dx_MASK; 972 973 mutex_lock(&lpss_iosf_mutex); 974 975 if (!lpss_iosf_d3_entered) 976 goto exit; 977 978 lpss_iosf_d3_entered = false; 979 980 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 981 LPSS_IOSF_GPIODEF0, value1, mask1); 982 983 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 984 LPSS_IOSF_PMCSR, value2, mask2); 985 986 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 987 LPSS_IOSF_PMCSR, value2, mask2); 988 989exit: 990 mutex_unlock(&lpss_iosf_mutex); 991} 992 993static int acpi_lpss_suspend(struct device *dev, bool wakeup) 994{ 995 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 996 int ret; 997 998 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 999 acpi_lpss_save_ctx(dev, pdata); 1000 1001 ret = acpi_dev_suspend(dev, wakeup); 1002 1003 /* 1004 * This call must be last in the sequence, otherwise PMC will return 1005 * wrong status for devices being about to be powered off. See 1006 * lpss_iosf_enter_d3_state() for further information. 1007 */ 1008 if (acpi_target_system_state() == ACPI_STATE_S0 && 1009 lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 1010 lpss_iosf_enter_d3_state(); 1011 1012 return ret; 1013} 1014 1015static int acpi_lpss_resume(struct device *dev) 1016{ 1017 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1018 int ret; 1019 1020 /* 1021 * This call is kept first to be in symmetry with 1022 * acpi_lpss_runtime_suspend() one. 1023 */ 1024 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 1025 lpss_iosf_exit_d3_state(); 1026 1027 ret = acpi_dev_resume(dev); 1028 if (ret) 1029 return ret; 1030 1031 acpi_lpss_d3_to_d0_delay(pdata); 1032 1033 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) 1034 acpi_lpss_restore_ctx(dev, pdata); 1035 1036 return 0; 1037} 1038 1039#ifdef CONFIG_PM_SLEEP 1040static int acpi_lpss_do_suspend_late(struct device *dev) 1041{ 1042 int ret; 1043 1044 if (dev_pm_skip_suspend(dev)) 1045 return 0; 1046 1047 ret = pm_generic_suspend_late(dev); 1048 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 1049} 1050 1051static int acpi_lpss_suspend_late(struct device *dev) 1052{ 1053 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1054 1055 if (pdata->dev_desc->resume_from_noirq) 1056 return 0; 1057 1058 return acpi_lpss_do_suspend_late(dev); 1059} 1060 1061static int acpi_lpss_suspend_noirq(struct device *dev) 1062{ 1063 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1064 int ret; 1065 1066 if (pdata->dev_desc->resume_from_noirq) { 1067 /* 1068 * The driver's ->suspend_late callback will be invoked by 1069 * acpi_lpss_do_suspend_late(), with the assumption that the 1070 * driver really wanted to run that code in ->suspend_noirq, but 1071 * it could not run after acpi_dev_suspend() and the driver 1072 * expected the latter to be called in the "late" phase. 1073 */ 1074 ret = acpi_lpss_do_suspend_late(dev); 1075 if (ret) 1076 return ret; 1077 } 1078 1079 return acpi_subsys_suspend_noirq(dev); 1080} 1081 1082static int acpi_lpss_do_resume_early(struct device *dev) 1083{ 1084 int ret = acpi_lpss_resume(dev); 1085 1086 return ret ? ret : pm_generic_resume_early(dev); 1087} 1088 1089static int acpi_lpss_resume_early(struct device *dev) 1090{ 1091 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1092 1093 if (pdata->dev_desc->resume_from_noirq) 1094 return 0; 1095 1096 if (dev_pm_skip_resume(dev)) 1097 return 0; 1098 1099 return acpi_lpss_do_resume_early(dev); 1100} 1101 1102static int acpi_lpss_resume_noirq(struct device *dev) 1103{ 1104 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1105 int ret; 1106 1107 /* Follow acpi_subsys_resume_noirq(). */ 1108 if (dev_pm_skip_resume(dev)) 1109 return 0; 1110 1111 ret = pm_generic_resume_noirq(dev); 1112 if (ret) 1113 return ret; 1114 1115 if (!pdata->dev_desc->resume_from_noirq) 1116 return 0; 1117 1118 /* 1119 * The driver's ->resume_early callback will be invoked by 1120 * acpi_lpss_do_resume_early(), with the assumption that the driver 1121 * really wanted to run that code in ->resume_noirq, but it could not 1122 * run before acpi_dev_resume() and the driver expected the latter to be 1123 * called in the "early" phase. 1124 */ 1125 return acpi_lpss_do_resume_early(dev); 1126} 1127 1128static int acpi_lpss_do_restore_early(struct device *dev) 1129{ 1130 int ret = acpi_lpss_resume(dev); 1131 1132 return ret ? ret : pm_generic_restore_early(dev); 1133} 1134 1135static int acpi_lpss_restore_early(struct device *dev) 1136{ 1137 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1138 1139 if (pdata->dev_desc->resume_from_noirq) 1140 return 0; 1141 1142 return acpi_lpss_do_restore_early(dev); 1143} 1144 1145static int acpi_lpss_restore_noirq(struct device *dev) 1146{ 1147 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1148 int ret; 1149 1150 ret = pm_generic_restore_noirq(dev); 1151 if (ret) 1152 return ret; 1153 1154 if (!pdata->dev_desc->resume_from_noirq) 1155 return 0; 1156 1157 /* This is analogous to what happens in acpi_lpss_resume_noirq(). */ 1158 return acpi_lpss_do_restore_early(dev); 1159} 1160 1161static int acpi_lpss_do_poweroff_late(struct device *dev) 1162{ 1163 int ret = pm_generic_poweroff_late(dev); 1164 1165 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 1166} 1167 1168static int acpi_lpss_poweroff_late(struct device *dev) 1169{ 1170 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1171 1172 if (dev_pm_skip_suspend(dev)) 1173 return 0; 1174 1175 if (pdata->dev_desc->resume_from_noirq) 1176 return 0; 1177 1178 return acpi_lpss_do_poweroff_late(dev); 1179} 1180 1181static int acpi_lpss_poweroff_noirq(struct device *dev) 1182{ 1183 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1184 1185 if (dev_pm_skip_suspend(dev)) 1186 return 0; 1187 1188 if (pdata->dev_desc->resume_from_noirq) { 1189 /* This is analogous to the acpi_lpss_suspend_noirq() case. */ 1190 int ret = acpi_lpss_do_poweroff_late(dev); 1191 1192 if (ret) 1193 return ret; 1194 } 1195 1196 return pm_generic_poweroff_noirq(dev); 1197} 1198#endif /* CONFIG_PM_SLEEP */ 1199 1200static int acpi_lpss_runtime_suspend(struct device *dev) 1201{ 1202 int ret = pm_generic_runtime_suspend(dev); 1203 1204 return ret ? ret : acpi_lpss_suspend(dev, true); 1205} 1206 1207static int acpi_lpss_runtime_resume(struct device *dev) 1208{ 1209 int ret = acpi_lpss_resume(dev); 1210 1211 return ret ? ret : pm_generic_runtime_resume(dev); 1212} 1213#endif /* CONFIG_PM */ 1214 1215static struct dev_pm_domain acpi_lpss_pm_domain = { 1216#ifdef CONFIG_PM 1217 .activate = acpi_lpss_activate, 1218 .dismiss = acpi_lpss_dismiss, 1219#endif 1220 .ops = { 1221#ifdef CONFIG_PM 1222#ifdef CONFIG_PM_SLEEP 1223 .prepare = acpi_subsys_prepare, 1224 .complete = acpi_subsys_complete, 1225 .suspend = acpi_subsys_suspend, 1226 .suspend_late = acpi_lpss_suspend_late, 1227 .suspend_noirq = acpi_lpss_suspend_noirq, 1228 .resume_noirq = acpi_lpss_resume_noirq, 1229 .resume_early = acpi_lpss_resume_early, 1230 .freeze = acpi_subsys_freeze, 1231 .poweroff = acpi_subsys_poweroff, 1232 .poweroff_late = acpi_lpss_poweroff_late, 1233 .poweroff_noirq = acpi_lpss_poweroff_noirq, 1234 .restore_noirq = acpi_lpss_restore_noirq, 1235 .restore_early = acpi_lpss_restore_early, 1236#endif 1237 .runtime_suspend = acpi_lpss_runtime_suspend, 1238 .runtime_resume = acpi_lpss_runtime_resume, 1239#endif 1240 }, 1241}; 1242 1243static int acpi_lpss_platform_notify(struct notifier_block *nb, 1244 unsigned long action, void *data) 1245{ 1246 struct platform_device *pdev = to_platform_device(data); 1247 struct lpss_private_data *pdata; 1248 struct acpi_device *adev; 1249 const struct acpi_device_id *id; 1250 1251 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); 1252 if (!id || !id->driver_data) 1253 return 0; 1254 1255 adev = ACPI_COMPANION(&pdev->dev); 1256 if (!adev) 1257 return 0; 1258 1259 pdata = acpi_driver_data(adev); 1260 if (!pdata) 1261 return 0; 1262 1263 if (pdata->mmio_base && 1264 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { 1265 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); 1266 return 0; 1267 } 1268 1269 switch (action) { 1270 case BUS_NOTIFY_BIND_DRIVER: 1271 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1272 break; 1273 case BUS_NOTIFY_DRIVER_NOT_BOUND: 1274 case BUS_NOTIFY_UNBOUND_DRIVER: 1275 dev_pm_domain_set(&pdev->dev, NULL); 1276 break; 1277 case BUS_NOTIFY_ADD_DEVICE: 1278 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1279 if (pdata->dev_desc->flags & LPSS_LTR) 1280 return sysfs_create_group(&pdev->dev.kobj, 1281 &lpss_attr_group); 1282 break; 1283 case BUS_NOTIFY_DEL_DEVICE: 1284 if (pdata->dev_desc->flags & LPSS_LTR) 1285 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); 1286 dev_pm_domain_set(&pdev->dev, NULL); 1287 break; 1288 default: 1289 break; 1290 } 1291 1292 return 0; 1293} 1294 1295static struct notifier_block acpi_lpss_nb = { 1296 .notifier_call = acpi_lpss_platform_notify, 1297}; 1298 1299static void acpi_lpss_bind(struct device *dev) 1300{ 1301 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1302 1303 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) 1304 return; 1305 1306 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) 1307 dev->power.set_latency_tolerance = acpi_lpss_set_ltr; 1308 else 1309 dev_err(dev, "MMIO size insufficient to access LTR\n"); 1310} 1311 1312static void acpi_lpss_unbind(struct device *dev) 1313{ 1314 dev->power.set_latency_tolerance = NULL; 1315} 1316 1317static struct acpi_scan_handler lpss_handler = { 1318 .ids = acpi_lpss_device_ids, 1319 .attach = acpi_lpss_create_device, 1320 .bind = acpi_lpss_bind, 1321 .unbind = acpi_lpss_unbind, 1322}; 1323 1324void __init acpi_lpss_init(void) 1325{ 1326 const struct x86_cpu_id *id; 1327 int ret; 1328 1329 ret = lpss_atom_clk_init(); 1330 if (ret) 1331 return; 1332 1333 id = x86_match_cpu(lpss_cpu_ids); 1334 if (id) 1335 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; 1336 1337 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); 1338 acpi_scan_add_handler(&lpss_handler); 1339} 1340 1341#else 1342 1343static struct acpi_scan_handler lpss_handler = { 1344 .ids = acpi_lpss_device_ids, 1345}; 1346 1347void __init acpi_lpss_init(void) 1348{ 1349 acpi_scan_add_handler(&lpss_handler); 1350} 1351 1352#endif /* CONFIG_X86_INTEL_LPSS */
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