spcr.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2012, Intel Corporation
  4 * Copyright (c) 2015, Red Hat, Inc.
  5 * Copyright (c) 2015, 2016 Linaro Ltd.
  6 */
  7
  8#define pr_fmt(fmt) "ACPI: SPCR: " fmt
  9
 10#include <linux/acpi.h>
 11#include <linux/console.h>
 12#include <linux/kernel.h>
 13#include <linux/serial_core.h>
 14
 15/*
 16 * Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit as
 17 * occasionally getting stuck as 1. To avoid the potential for a hang, check
 18 * TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART
 19 * implementations, so only do so if an affected platform is detected in
 20 * acpi_parse_spcr().
 21 */
 22bool qdf2400_e44_present;
 23EXPORT_SYMBOL(qdf2400_e44_present);
 24
 25/*
 26 * Some Qualcomm Datacenter Technologies SoCs have a defective UART BUSY bit.
 27 * Detect them by examining the OEM fields in the SPCR header, similar to PCI
 28 * quirk detection in pci_mcfg.c.
 29 */
 30static bool qdf2400_erratum_44_present(struct acpi_table_header *h)
 31{
 32	if (memcmp(h->oem_id, "QCOM  ", ACPI_OEM_ID_SIZE))
 33		return false;
 34
 35	if (!memcmp(h->oem_table_id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE))
 36		return true;
 37
 38	if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) &&
 39			h->oem_revision == 1)
 40		return true;
 41
 42	return false;
 43}
 44
 45/*
 46 * APM X-Gene v1 and v2 UART hardware is an 16550 like device but has its
 47 * register aligned to 32-bit. In addition, the BIOS also encoded the
 48 * access width to be 8 bits. This function detects this errata condition.
 49 */
 50static bool xgene_8250_erratum_present(struct acpi_table_spcr *tb)
 51{
 52	bool xgene_8250 = false;
 53
 54	if (tb->interface_type != ACPI_DBG2_16550_COMPATIBLE)
 55		return false;
 56
 57	if (memcmp(tb->header.oem_id, "APMC0D", ACPI_OEM_ID_SIZE) &&
 58	    memcmp(tb->header.oem_id, "HPE   ", ACPI_OEM_ID_SIZE))
 59		return false;
 60
 61	if (!memcmp(tb->header.oem_table_id, "XGENESPC",
 62	    ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 0)
 63		xgene_8250 = true;
 64
 65	if (!memcmp(tb->header.oem_table_id, "ProLiant",
 66	    ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 1)
 67		xgene_8250 = true;
 68
 69	return xgene_8250;
 70}
 71
 72/**
 73 * acpi_parse_spcr() - parse ACPI SPCR table and add preferred console
 74 * @enable_earlycon: set up earlycon for the console specified by the table
 75 * @enable_console: setup the console specified by the table.
 76 *
 77 * For the architectures with support for ACPI, CONFIG_ACPI_SPCR_TABLE may be
 78 * defined to parse ACPI SPCR table.  As a result of the parsing preferred
 79 * console is registered and if @enable_earlycon is true, earlycon is set up.
 80 * If @enable_console is true the system console is also configured.
 81 *
 82 * When CONFIG_ACPI_SPCR_TABLE is defined, this function should be called
 83 * from arch initialization code as soon as the DT/ACPI decision is made.
 84 */
 85int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
 86{
 87	static char opts[64];
 88	struct acpi_table_spcr *table;
 89	acpi_status status;
 90	char *uart;
 91	char *iotype;
 92	int baud_rate;
 93	int err;
 94
 95	if (acpi_disabled)
 96		return -ENODEV;
 97
 98	status = acpi_get_table(ACPI_SIG_SPCR, 0, (struct acpi_table_header **)&table);
 99	if (ACPI_FAILURE(status))
100		return -ENOENT;
101
102	if (table->header.revision < 2)
103		pr_info("SPCR table version %d\n", table->header.revision);
104
105	if (table->serial_port.space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
106		u32 bit_width = table->serial_port.access_width;
107
108		if (bit_width > ACPI_ACCESS_BIT_MAX) {
109			pr_err(FW_BUG "Unacceptable wide SPCR Access Width. Defaulting to byte size\n");
110			bit_width = ACPI_ACCESS_BIT_DEFAULT;
111		}
112		switch (ACPI_ACCESS_BIT_WIDTH((bit_width))) {
113		default:
114			pr_err(FW_BUG "Unexpected SPCR Access Width. Defaulting to byte size\n");
115			fallthrough;
116		case 8:
117			iotype = "mmio";
118			break;
119		case 16:
120			iotype = "mmio16";
121			break;
122		case 32:
123			iotype = "mmio32";
124			break;
125		}
126	} else
127		iotype = "io";
128
129	switch (table->interface_type) {
130	case ACPI_DBG2_ARM_SBSA_32BIT:
131		iotype = "mmio32";
132		fallthrough;
133	case ACPI_DBG2_ARM_PL011:
134	case ACPI_DBG2_ARM_SBSA_GENERIC:
135	case ACPI_DBG2_BCM2835:
136		uart = "pl011";
137		break;
138	case ACPI_DBG2_16550_COMPATIBLE:
139	case ACPI_DBG2_16550_SUBSET:
140	case ACPI_DBG2_16550_WITH_GAS:
141	case ACPI_DBG2_16550_NVIDIA:
142		uart = "uart";
143		break;
144	case ACPI_DBG2_RISCV_SBI_CON:
145		uart = "sbi";
146		break;
147	default:
148		err = -ENOENT;
149		goto done;
150	}
151
152	/*
153	 * SPCR 1.09 defines Precise Baud Rate Filed contains a specific
154	 * non-zero baud rate which overrides the value of the Configured
155	 * Baud Rate field. If this field is zero or not present, Configured
156	 * Baud Rate is used.
157	 */
158	if (table->header.revision >= 4 && table->precise_baudrate)
159		baud_rate = table->precise_baudrate;
160	else switch (table->baud_rate) {
161	case 0:
162		/*
163		 * SPCR 1.04 defines 0 as a preconfigured state of UART.
164		 * Assume firmware or bootloader configures console correctly.
165		 */
166		baud_rate = 0;
167		break;
168	case 3:
169		baud_rate = 9600;
170		break;
171	case 4:
172		baud_rate = 19200;
173		break;
174	case 6:
175		baud_rate = 57600;
176		break;
177	case 7:
178		baud_rate = 115200;
179		break;
180	default:
181		err = -ENOENT;
182		goto done;
183	}
184
185	/*
186	 * If the E44 erratum is required, then we need to tell the pl011
187	 * driver to implement the work-around.
188	 *
189	 * The global variable is used by the probe function when it
190	 * creates the UARTs, whether or not they're used as a console.
191	 *
192	 * If the user specifies "traditional" earlycon, the qdf2400_e44
193	 * console name matches the EARLYCON_DECLARE() statement, and
194	 * SPCR is not used.  Parameter "earlycon" is false.
195	 *
196	 * If the user specifies "SPCR" earlycon, then we need to update
197	 * the console name so that it also says "qdf2400_e44".  Parameter
198	 * "earlycon" is true.
199	 *
200	 * For consistency, if we change the console name, then we do it
201	 * for everyone, not just earlycon.
202	 */
203	if (qdf2400_erratum_44_present(&table->header)) {
204		qdf2400_e44_present = true;
205		if (enable_earlycon)
206			uart = "qdf2400_e44";
207	}
208
209	if (xgene_8250_erratum_present(table)) {
210		iotype = "mmio32";
211
212		/*
213		 * For xgene v1 and v2 we don't know the clock rate of the
214		 * UART so don't attempt to change to the baud rate state
215		 * in the table because driver cannot calculate the dividers
216		 */
217		baud_rate = 0;
218	}
219
220	if (!baud_rate) {
221		snprintf(opts, sizeof(opts), "%s,%s,0x%llx", uart, iotype,
222			 table->serial_port.address);
223	} else {
224		snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype,
225			 table->serial_port.address, baud_rate);
226	}
227
228	pr_info("console: %s\n", opts);
229
230	if (enable_earlycon)
231		setup_earlycon(opts);
232
233	if (enable_console)
234		err = add_preferred_console(uart, 0, opts + strlen(uart) + 1);
235	else
236		err = 0;
237done:
238	acpi_put_table((struct acpi_table_header *)table);
239	return err;
240}