rocket_registers.h

   1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
   2
   3#ifndef __ROCKET_REGISTERS_XML__
   4#define __ROCKET_REGISTERS_XML__
   5
   6/* Autogenerated file, DO NOT EDIT manually!
   7
   8This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
   9http://gitlab.freedesktop.org/mesa/mesa/
  10git clone https://gitlab.freedesktop.org/mesa/mesa.git
  11
  12The rules-ng-ng source files this header was generated from are:
  13
  14- /home/tomeu/src/mesa/src/gallium/drivers/rocket/registers.xml (  60076 bytes, from Wed Jun 12 10:02:25 2024)
  15
  16Copyright (C) 2024-2025 by the following authors:
  17- Tomeu Vizoso <tomeu@tomeuvizoso.net>
  18*/
  19
  20#define REG_PC_VERSION						0x00000000
  21#define PC_VERSION_VERSION__MASK				0xffffffff
  22#define PC_VERSION_VERSION__SHIFT				0
  23static inline uint32_t PC_VERSION_VERSION(uint32_t val)
  24{
  25	return ((val) << PC_VERSION_VERSION__SHIFT) & PC_VERSION_VERSION__MASK;
  26}
  27
  28#define REG_PC_VERSION_NUM					0x00000004
  29#define PC_VERSION_NUM_VERSION_NUM__MASK			0xffffffff
  30#define PC_VERSION_NUM_VERSION_NUM__SHIFT			0
  31static inline uint32_t PC_VERSION_NUM_VERSION_NUM(uint32_t val)
  32{
  33	return ((val) << PC_VERSION_NUM_VERSION_NUM__SHIFT) & PC_VERSION_NUM_VERSION_NUM__MASK;
  34}
  35
  36#define REG_PC_OPERATION_ENABLE					0x00000008
  37#define PC_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
  38#define PC_OPERATION_ENABLE_RESERVED_0__SHIFT			1
  39static inline uint32_t PC_OPERATION_ENABLE_RESERVED_0(uint32_t val)
  40{
  41	return ((val) << PC_OPERATION_ENABLE_RESERVED_0__SHIFT) & PC_OPERATION_ENABLE_RESERVED_0__MASK;
  42}
  43#define PC_OPERATION_ENABLE_OP_EN__MASK				0x00000001
  44#define PC_OPERATION_ENABLE_OP_EN__SHIFT			0
  45static inline uint32_t PC_OPERATION_ENABLE_OP_EN(uint32_t val)
  46{
  47	return ((val) << PC_OPERATION_ENABLE_OP_EN__SHIFT) & PC_OPERATION_ENABLE_OP_EN__MASK;
  48}
  49
  50#define REG_PC_BASE_ADDRESS					0x00000010
  51#define PC_BASE_ADDRESS_PC_SOURCE_ADDR__MASK			0xfffffff0
  52#define PC_BASE_ADDRESS_PC_SOURCE_ADDR__SHIFT			4
  53static inline uint32_t PC_BASE_ADDRESS_PC_SOURCE_ADDR(uint32_t val)
  54{
  55	return ((val) << PC_BASE_ADDRESS_PC_SOURCE_ADDR__SHIFT) & PC_BASE_ADDRESS_PC_SOURCE_ADDR__MASK;
  56}
  57#define PC_BASE_ADDRESS_RESERVED_0__MASK			0x0000000e
  58#define PC_BASE_ADDRESS_RESERVED_0__SHIFT			1
  59static inline uint32_t PC_BASE_ADDRESS_RESERVED_0(uint32_t val)
  60{
  61	return ((val) << PC_BASE_ADDRESS_RESERVED_0__SHIFT) & PC_BASE_ADDRESS_RESERVED_0__MASK;
  62}
  63#define PC_BASE_ADDRESS_PC_SEL__MASK				0x00000001
  64#define PC_BASE_ADDRESS_PC_SEL__SHIFT				0
  65static inline uint32_t PC_BASE_ADDRESS_PC_SEL(uint32_t val)
  66{
  67	return ((val) << PC_BASE_ADDRESS_PC_SEL__SHIFT) & PC_BASE_ADDRESS_PC_SEL__MASK;
  68}
  69
  70#define REG_PC_REGISTER_AMOUNTS					0x00000014
  71#define PC_REGISTER_AMOUNTS_RESERVED_0__MASK			0xffff0000
  72#define PC_REGISTER_AMOUNTS_RESERVED_0__SHIFT			16
  73static inline uint32_t PC_REGISTER_AMOUNTS_RESERVED_0(uint32_t val)
  74{
  75	return ((val) << PC_REGISTER_AMOUNTS_RESERVED_0__SHIFT) & PC_REGISTER_AMOUNTS_RESERVED_0__MASK;
  76}
  77#define PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__MASK		0x0000ffff
  78#define PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__SHIFT		0
  79static inline uint32_t PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT(uint32_t val)
  80{
  81	return ((val) << PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__SHIFT) & PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__MASK;
  82}
  83
  84#define REG_PC_INTERRUPT_MASK					0x00000020
  85#define PC_INTERRUPT_MASK_RESERVED_0__MASK			0xffffc000
  86#define PC_INTERRUPT_MASK_RESERVED_0__SHIFT			14
  87static inline uint32_t PC_INTERRUPT_MASK_RESERVED_0(uint32_t val)
  88{
  89	return ((val) << PC_INTERRUPT_MASK_RESERVED_0__SHIFT) & PC_INTERRUPT_MASK_RESERVED_0__MASK;
  90}
  91#define PC_INTERRUPT_MASK_DMA_WRITE_ERROR			0x00002000
  92#define PC_INTERRUPT_MASK_DMA_READ_ERROR			0x00001000
  93#define PC_INTERRUPT_MASK_PPU_1					0x00000800
  94#define PC_INTERRUPT_MASK_PPU_0					0x00000400
  95#define PC_INTERRUPT_MASK_DPU_1					0x00000200
  96#define PC_INTERRUPT_MASK_DPU_0					0x00000100
  97#define PC_INTERRUPT_MASK_CORE_1				0x00000080
  98#define PC_INTERRUPT_MASK_CORE_0				0x00000040
  99#define PC_INTERRUPT_MASK_CNA_CSC_1				0x00000020
 100#define PC_INTERRUPT_MASK_CNA_CSC_0				0x00000010
 101#define PC_INTERRUPT_MASK_CNA_WEIGHT_1				0x00000008
 102#define PC_INTERRUPT_MASK_CNA_WEIGHT_0				0x00000004
 103#define PC_INTERRUPT_MASK_CNA_FEATURE_1				0x00000002
 104#define PC_INTERRUPT_MASK_CNA_FEATURE_0				0x00000001
 105
 106#define REG_PC_INTERRUPT_CLEAR					0x00000024
 107#define PC_INTERRUPT_CLEAR_RESERVED_0__MASK			0xffffc000
 108#define PC_INTERRUPT_CLEAR_RESERVED_0__SHIFT			14
 109static inline uint32_t PC_INTERRUPT_CLEAR_RESERVED_0(uint32_t val)
 110{
 111	return ((val) << PC_INTERRUPT_CLEAR_RESERVED_0__SHIFT) & PC_INTERRUPT_CLEAR_RESERVED_0__MASK;
 112}
 113#define PC_INTERRUPT_CLEAR_DMA_WRITE_ERROR			0x00002000
 114#define PC_INTERRUPT_CLEAR_DMA_READ_ERROR			0x00001000
 115#define PC_INTERRUPT_CLEAR_PPU_1				0x00000800
 116#define PC_INTERRUPT_CLEAR_PPU_0				0x00000400
 117#define PC_INTERRUPT_CLEAR_DPU_1				0x00000200
 118#define PC_INTERRUPT_CLEAR_DPU_0				0x00000100
 119#define PC_INTERRUPT_CLEAR_CORE_1				0x00000080
 120#define PC_INTERRUPT_CLEAR_CORE_0				0x00000040
 121#define PC_INTERRUPT_CLEAR_CNA_CSC_1				0x00000020
 122#define PC_INTERRUPT_CLEAR_CNA_CSC_0				0x00000010
 123#define PC_INTERRUPT_CLEAR_CNA_WEIGHT_1				0x00000008
 124#define PC_INTERRUPT_CLEAR_CNA_WEIGHT_0				0x00000004
 125#define PC_INTERRUPT_CLEAR_CNA_FEATURE_1			0x00000002
 126#define PC_INTERRUPT_CLEAR_CNA_FEATURE_0			0x00000001
 127
 128#define REG_PC_INTERRUPT_STATUS					0x00000028
 129#define PC_INTERRUPT_STATUS_RESERVED_0__MASK			0xffffc000
 130#define PC_INTERRUPT_STATUS_RESERVED_0__SHIFT			14
 131static inline uint32_t PC_INTERRUPT_STATUS_RESERVED_0(uint32_t val)
 132{
 133	return ((val) << PC_INTERRUPT_STATUS_RESERVED_0__SHIFT) & PC_INTERRUPT_STATUS_RESERVED_0__MASK;
 134}
 135#define PC_INTERRUPT_STATUS_DMA_WRITE_ERROR			0x00002000
 136#define PC_INTERRUPT_STATUS_DMA_READ_ERROR			0x00001000
 137#define PC_INTERRUPT_STATUS_PPU_1				0x00000800
 138#define PC_INTERRUPT_STATUS_PPU_0				0x00000400
 139#define PC_INTERRUPT_STATUS_DPU_1				0x00000200
 140#define PC_INTERRUPT_STATUS_DPU_0				0x00000100
 141#define PC_INTERRUPT_STATUS_CORE_1				0x00000080
 142#define PC_INTERRUPT_STATUS_CORE_0				0x00000040
 143#define PC_INTERRUPT_STATUS_CNA_CSC_1				0x00000020
 144#define PC_INTERRUPT_STATUS_CNA_CSC_0				0x00000010
 145#define PC_INTERRUPT_STATUS_CNA_WEIGHT_1			0x00000008
 146#define PC_INTERRUPT_STATUS_CNA_WEIGHT_0			0x00000004
 147#define PC_INTERRUPT_STATUS_CNA_FEATURE_1			0x00000002
 148#define PC_INTERRUPT_STATUS_CNA_FEATURE_0			0x00000001
 149
 150#define REG_PC_INTERRUPT_RAW_STATUS				0x0000002c
 151#define PC_INTERRUPT_RAW_STATUS_RESERVED_0__MASK		0xffffc000
 152#define PC_INTERRUPT_RAW_STATUS_RESERVED_0__SHIFT		14
 153static inline uint32_t PC_INTERRUPT_RAW_STATUS_RESERVED_0(uint32_t val)
 154{
 155	return ((val) << PC_INTERRUPT_RAW_STATUS_RESERVED_0__SHIFT) & PC_INTERRUPT_RAW_STATUS_RESERVED_0__MASK;
 156}
 157#define PC_INTERRUPT_RAW_STATUS_DMA_WRITE_ERROR			0x00002000
 158#define PC_INTERRUPT_RAW_STATUS_DMA_READ_ERROR			0x00001000
 159#define PC_INTERRUPT_RAW_STATUS_PPU_1				0x00000800
 160#define PC_INTERRUPT_RAW_STATUS_PPU_0				0x00000400
 161#define PC_INTERRUPT_RAW_STATUS_DPU_1				0x00000200
 162#define PC_INTERRUPT_RAW_STATUS_DPU_0				0x00000100
 163#define PC_INTERRUPT_RAW_STATUS_CORE_1				0x00000080
 164#define PC_INTERRUPT_RAW_STATUS_CORE_0				0x00000040
 165#define PC_INTERRUPT_RAW_STATUS_CNA_CSC_1			0x00000020
 166#define PC_INTERRUPT_RAW_STATUS_CNA_CSC_0			0x00000010
 167#define PC_INTERRUPT_RAW_STATUS_CNA_WEIGHT_1			0x00000008
 168#define PC_INTERRUPT_RAW_STATUS_CNA_WEIGHT_0			0x00000004
 169#define PC_INTERRUPT_RAW_STATUS_CNA_FEATURE_1			0x00000002
 170#define PC_INTERRUPT_RAW_STATUS_CNA_FEATURE_0			0x00000001
 171
 172#define REG_PC_TASK_CON						0x00000030
 173#define PC_TASK_CON_RESERVED_0__MASK				0xffffc000
 174#define PC_TASK_CON_RESERVED_0__SHIFT				14
 175static inline uint32_t PC_TASK_CON_RESERVED_0(uint32_t val)
 176{
 177	return ((val) << PC_TASK_CON_RESERVED_0__SHIFT) & PC_TASK_CON_RESERVED_0__MASK;
 178}
 179#define PC_TASK_CON_TASK_COUNT_CLEAR__MASK			0x00002000
 180#define PC_TASK_CON_TASK_COUNT_CLEAR__SHIFT			13
 181static inline uint32_t PC_TASK_CON_TASK_COUNT_CLEAR(uint32_t val)
 182{
 183	return ((val) << PC_TASK_CON_TASK_COUNT_CLEAR__SHIFT) & PC_TASK_CON_TASK_COUNT_CLEAR__MASK;
 184}
 185#define PC_TASK_CON_TASK_PP_EN__MASK				0x00001000
 186#define PC_TASK_CON_TASK_PP_EN__SHIFT				12
 187static inline uint32_t PC_TASK_CON_TASK_PP_EN(uint32_t val)
 188{
 189	return ((val) << PC_TASK_CON_TASK_PP_EN__SHIFT) & PC_TASK_CON_TASK_PP_EN__MASK;
 190}
 191#define PC_TASK_CON_TASK_NUMBER__MASK				0x00000fff
 192#define PC_TASK_CON_TASK_NUMBER__SHIFT				0
 193static inline uint32_t PC_TASK_CON_TASK_NUMBER(uint32_t val)
 194{
 195	return ((val) << PC_TASK_CON_TASK_NUMBER__SHIFT) & PC_TASK_CON_TASK_NUMBER__MASK;
 196}
 197
 198#define REG_PC_TASK_DMA_BASE_ADDR				0x00000034
 199#define PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__MASK		0xfffffff0
 200#define PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__SHIFT		4
 201static inline uint32_t PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR(uint32_t val)
 202{
 203	return ((val) << PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__SHIFT) & PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__MASK;
 204}
 205#define PC_TASK_DMA_BASE_ADDR_RESERVED_0__MASK			0x0000000f
 206#define PC_TASK_DMA_BASE_ADDR_RESERVED_0__SHIFT			0
 207static inline uint32_t PC_TASK_DMA_BASE_ADDR_RESERVED_0(uint32_t val)
 208{
 209	return ((val) << PC_TASK_DMA_BASE_ADDR_RESERVED_0__SHIFT) & PC_TASK_DMA_BASE_ADDR_RESERVED_0__MASK;
 210}
 211
 212#define REG_PC_TASK_STATUS					0x0000003c
 213#define PC_TASK_STATUS_RESERVED_0__MASK				0xf0000000
 214#define PC_TASK_STATUS_RESERVED_0__SHIFT			28
 215static inline uint32_t PC_TASK_STATUS_RESERVED_0(uint32_t val)
 216{
 217	return ((val) << PC_TASK_STATUS_RESERVED_0__SHIFT) & PC_TASK_STATUS_RESERVED_0__MASK;
 218}
 219#define PC_TASK_STATUS_TASK_STATUS__MASK			0x0fffffff
 220#define PC_TASK_STATUS_TASK_STATUS__SHIFT			0
 221static inline uint32_t PC_TASK_STATUS_TASK_STATUS(uint32_t val)
 222{
 223	return ((val) << PC_TASK_STATUS_TASK_STATUS__SHIFT) & PC_TASK_STATUS_TASK_STATUS__MASK;
 224}
 225
 226#define REG_CNA_S_STATUS					0x00001000
 227#define CNA_S_STATUS_RESERVED_0__MASK				0xfffc0000
 228#define CNA_S_STATUS_RESERVED_0__SHIFT				18
 229static inline uint32_t CNA_S_STATUS_RESERVED_0(uint32_t val)
 230{
 231	return ((val) << CNA_S_STATUS_RESERVED_0__SHIFT) & CNA_S_STATUS_RESERVED_0__MASK;
 232}
 233#define CNA_S_STATUS_STATUS_1__MASK				0x00030000
 234#define CNA_S_STATUS_STATUS_1__SHIFT				16
 235static inline uint32_t CNA_S_STATUS_STATUS_1(uint32_t val)
 236{
 237	return ((val) << CNA_S_STATUS_STATUS_1__SHIFT) & CNA_S_STATUS_STATUS_1__MASK;
 238}
 239#define CNA_S_STATUS_RESERVED_1__MASK				0x0000fffc
 240#define CNA_S_STATUS_RESERVED_1__SHIFT				2
 241static inline uint32_t CNA_S_STATUS_RESERVED_1(uint32_t val)
 242{
 243	return ((val) << CNA_S_STATUS_RESERVED_1__SHIFT) & CNA_S_STATUS_RESERVED_1__MASK;
 244}
 245#define CNA_S_STATUS_STATUS_0__MASK				0x00000003
 246#define CNA_S_STATUS_STATUS_0__SHIFT				0
 247static inline uint32_t CNA_S_STATUS_STATUS_0(uint32_t val)
 248{
 249	return ((val) << CNA_S_STATUS_STATUS_0__SHIFT) & CNA_S_STATUS_STATUS_0__MASK;
 250}
 251
 252#define REG_CNA_S_POINTER					0x00001004
 253#define CNA_S_POINTER_RESERVED_0__MASK				0xfffe0000
 254#define CNA_S_POINTER_RESERVED_0__SHIFT				17
 255static inline uint32_t CNA_S_POINTER_RESERVED_0(uint32_t val)
 256{
 257	return ((val) << CNA_S_POINTER_RESERVED_0__SHIFT) & CNA_S_POINTER_RESERVED_0__MASK;
 258}
 259#define CNA_S_POINTER_EXECUTER__MASK				0x00010000
 260#define CNA_S_POINTER_EXECUTER__SHIFT				16
 261static inline uint32_t CNA_S_POINTER_EXECUTER(uint32_t val)
 262{
 263	return ((val) << CNA_S_POINTER_EXECUTER__SHIFT) & CNA_S_POINTER_EXECUTER__MASK;
 264}
 265#define CNA_S_POINTER_RESERVED_1__MASK				0x0000ffc0
 266#define CNA_S_POINTER_RESERVED_1__SHIFT				6
 267static inline uint32_t CNA_S_POINTER_RESERVED_1(uint32_t val)
 268{
 269	return ((val) << CNA_S_POINTER_RESERVED_1__SHIFT) & CNA_S_POINTER_RESERVED_1__MASK;
 270}
 271#define CNA_S_POINTER_EXECUTER_PP_CLEAR__MASK			0x00000020
 272#define CNA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT			5
 273static inline uint32_t CNA_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
 274{
 275	return ((val) << CNA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & CNA_S_POINTER_EXECUTER_PP_CLEAR__MASK;
 276}
 277#define CNA_S_POINTER_POINTER_PP_CLEAR__MASK			0x00000010
 278#define CNA_S_POINTER_POINTER_PP_CLEAR__SHIFT			4
 279static inline uint32_t CNA_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
 280{
 281	return ((val) << CNA_S_POINTER_POINTER_PP_CLEAR__SHIFT) & CNA_S_POINTER_POINTER_PP_CLEAR__MASK;
 282}
 283#define CNA_S_POINTER_POINTER_PP_MODE__MASK			0x00000008
 284#define CNA_S_POINTER_POINTER_PP_MODE__SHIFT			3
 285static inline uint32_t CNA_S_POINTER_POINTER_PP_MODE(uint32_t val)
 286{
 287	return ((val) << CNA_S_POINTER_POINTER_PP_MODE__SHIFT) & CNA_S_POINTER_POINTER_PP_MODE__MASK;
 288}
 289#define CNA_S_POINTER_EXECUTER_PP_EN__MASK			0x00000004
 290#define CNA_S_POINTER_EXECUTER_PP_EN__SHIFT			2
 291static inline uint32_t CNA_S_POINTER_EXECUTER_PP_EN(uint32_t val)
 292{
 293	return ((val) << CNA_S_POINTER_EXECUTER_PP_EN__SHIFT) & CNA_S_POINTER_EXECUTER_PP_EN__MASK;
 294}
 295#define CNA_S_POINTER_POINTER_PP_EN__MASK			0x00000002
 296#define CNA_S_POINTER_POINTER_PP_EN__SHIFT			1
 297static inline uint32_t CNA_S_POINTER_POINTER_PP_EN(uint32_t val)
 298{
 299	return ((val) << CNA_S_POINTER_POINTER_PP_EN__SHIFT) & CNA_S_POINTER_POINTER_PP_EN__MASK;
 300}
 301#define CNA_S_POINTER_POINTER__MASK				0x00000001
 302#define CNA_S_POINTER_POINTER__SHIFT				0
 303static inline uint32_t CNA_S_POINTER_POINTER(uint32_t val)
 304{
 305	return ((val) << CNA_S_POINTER_POINTER__SHIFT) & CNA_S_POINTER_POINTER__MASK;
 306}
 307
 308#define REG_CNA_OPERATION_ENABLE				0x00001008
 309#define CNA_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
 310#define CNA_OPERATION_ENABLE_RESERVED_0__SHIFT			1
 311static inline uint32_t CNA_OPERATION_ENABLE_RESERVED_0(uint32_t val)
 312{
 313	return ((val) << CNA_OPERATION_ENABLE_RESERVED_0__SHIFT) & CNA_OPERATION_ENABLE_RESERVED_0__MASK;
 314}
 315#define CNA_OPERATION_ENABLE_OP_EN__MASK			0x00000001
 316#define CNA_OPERATION_ENABLE_OP_EN__SHIFT			0
 317static inline uint32_t CNA_OPERATION_ENABLE_OP_EN(uint32_t val)
 318{
 319	return ((val) << CNA_OPERATION_ENABLE_OP_EN__SHIFT) & CNA_OPERATION_ENABLE_OP_EN__MASK;
 320}
 321
 322#define REG_CNA_CONV_CON1					0x0000100c
 323#define CNA_CONV_CON1_RESERVED_0__MASK				0x80000000
 324#define CNA_CONV_CON1_RESERVED_0__SHIFT				31
 325static inline uint32_t CNA_CONV_CON1_RESERVED_0(uint32_t val)
 326{
 327	return ((val) << CNA_CONV_CON1_RESERVED_0__SHIFT) & CNA_CONV_CON1_RESERVED_0__MASK;
 328}
 329#define CNA_CONV_CON1_NONALIGN_DMA__MASK			0x40000000
 330#define CNA_CONV_CON1_NONALIGN_DMA__SHIFT			30
 331static inline uint32_t CNA_CONV_CON1_NONALIGN_DMA(uint32_t val)
 332{
 333	return ((val) << CNA_CONV_CON1_NONALIGN_DMA__SHIFT) & CNA_CONV_CON1_NONALIGN_DMA__MASK;
 334}
 335#define CNA_CONV_CON1_GROUP_LINE_OFF__MASK			0x20000000
 336#define CNA_CONV_CON1_GROUP_LINE_OFF__SHIFT			29
 337static inline uint32_t CNA_CONV_CON1_GROUP_LINE_OFF(uint32_t val)
 338{
 339	return ((val) << CNA_CONV_CON1_GROUP_LINE_OFF__SHIFT) & CNA_CONV_CON1_GROUP_LINE_OFF__MASK;
 340}
 341#define CNA_CONV_CON1_RESERVED_1__MASK				0x1ffe0000
 342#define CNA_CONV_CON1_RESERVED_1__SHIFT				17
 343static inline uint32_t CNA_CONV_CON1_RESERVED_1(uint32_t val)
 344{
 345	return ((val) << CNA_CONV_CON1_RESERVED_1__SHIFT) & CNA_CONV_CON1_RESERVED_1__MASK;
 346}
 347#define CNA_CONV_CON1_DECONV__MASK				0x00010000
 348#define CNA_CONV_CON1_DECONV__SHIFT				16
 349static inline uint32_t CNA_CONV_CON1_DECONV(uint32_t val)
 350{
 351	return ((val) << CNA_CONV_CON1_DECONV__SHIFT) & CNA_CONV_CON1_DECONV__MASK;
 352}
 353#define CNA_CONV_CON1_ARGB_IN__MASK				0x0000f000
 354#define CNA_CONV_CON1_ARGB_IN__SHIFT				12
 355static inline uint32_t CNA_CONV_CON1_ARGB_IN(uint32_t val)
 356{
 357	return ((val) << CNA_CONV_CON1_ARGB_IN__SHIFT) & CNA_CONV_CON1_ARGB_IN__MASK;
 358}
 359#define CNA_CONV_CON1_RESERVED_2__MASK				0x00000c00
 360#define CNA_CONV_CON1_RESERVED_2__SHIFT				10
 361static inline uint32_t CNA_CONV_CON1_RESERVED_2(uint32_t val)
 362{
 363	return ((val) << CNA_CONV_CON1_RESERVED_2__SHIFT) & CNA_CONV_CON1_RESERVED_2__MASK;
 364}
 365#define CNA_CONV_CON1_PROC_PRECISION__MASK			0x00000380
 366#define CNA_CONV_CON1_PROC_PRECISION__SHIFT			7
 367static inline uint32_t CNA_CONV_CON1_PROC_PRECISION(uint32_t val)
 368{
 369	return ((val) << CNA_CONV_CON1_PROC_PRECISION__SHIFT) & CNA_CONV_CON1_PROC_PRECISION__MASK;
 370}
 371#define CNA_CONV_CON1_IN_PRECISION__MASK			0x00000070
 372#define CNA_CONV_CON1_IN_PRECISION__SHIFT			4
 373static inline uint32_t CNA_CONV_CON1_IN_PRECISION(uint32_t val)
 374{
 375	return ((val) << CNA_CONV_CON1_IN_PRECISION__SHIFT) & CNA_CONV_CON1_IN_PRECISION__MASK;
 376}
 377#define CNA_CONV_CON1_CONV_MODE__MASK				0x0000000f
 378#define CNA_CONV_CON1_CONV_MODE__SHIFT				0
 379static inline uint32_t CNA_CONV_CON1_CONV_MODE(uint32_t val)
 380{
 381	return ((val) << CNA_CONV_CON1_CONV_MODE__SHIFT) & CNA_CONV_CON1_CONV_MODE__MASK;
 382}
 383
 384#define REG_CNA_CONV_CON2					0x00001010
 385#define CNA_CONV_CON2_RESERVED_0__MASK				0xff000000
 386#define CNA_CONV_CON2_RESERVED_0__SHIFT				24
 387static inline uint32_t CNA_CONV_CON2_RESERVED_0(uint32_t val)
 388{
 389	return ((val) << CNA_CONV_CON2_RESERVED_0__SHIFT) & CNA_CONV_CON2_RESERVED_0__MASK;
 390}
 391#define CNA_CONV_CON2_KERNEL_GROUP__MASK			0x00ff0000
 392#define CNA_CONV_CON2_KERNEL_GROUP__SHIFT			16
 393static inline uint32_t CNA_CONV_CON2_KERNEL_GROUP(uint32_t val)
 394{
 395	return ((val) << CNA_CONV_CON2_KERNEL_GROUP__SHIFT) & CNA_CONV_CON2_KERNEL_GROUP__MASK;
 396}
 397#define CNA_CONV_CON2_RESERVED_1__MASK				0x0000c000
 398#define CNA_CONV_CON2_RESERVED_1__SHIFT				14
 399static inline uint32_t CNA_CONV_CON2_RESERVED_1(uint32_t val)
 400{
 401	return ((val) << CNA_CONV_CON2_RESERVED_1__SHIFT) & CNA_CONV_CON2_RESERVED_1__MASK;
 402}
 403#define CNA_CONV_CON2_FEATURE_GRAINS__MASK			0x00003ff0
 404#define CNA_CONV_CON2_FEATURE_GRAINS__SHIFT			4
 405static inline uint32_t CNA_CONV_CON2_FEATURE_GRAINS(uint32_t val)
 406{
 407	return ((val) << CNA_CONV_CON2_FEATURE_GRAINS__SHIFT) & CNA_CONV_CON2_FEATURE_GRAINS__MASK;
 408}
 409#define CNA_CONV_CON2_RESERVED_2__MASK				0x00000008
 410#define CNA_CONV_CON2_RESERVED_2__SHIFT				3
 411static inline uint32_t CNA_CONV_CON2_RESERVED_2(uint32_t val)
 412{
 413	return ((val) << CNA_CONV_CON2_RESERVED_2__SHIFT) & CNA_CONV_CON2_RESERVED_2__MASK;
 414}
 415#define CNA_CONV_CON2_CSC_WO_EN__MASK				0x00000004
 416#define CNA_CONV_CON2_CSC_WO_EN__SHIFT				2
 417static inline uint32_t CNA_CONV_CON2_CSC_WO_EN(uint32_t val)
 418{
 419	return ((val) << CNA_CONV_CON2_CSC_WO_EN__SHIFT) & CNA_CONV_CON2_CSC_WO_EN__MASK;
 420}
 421#define CNA_CONV_CON2_CSC_DO_EN__MASK				0x00000002
 422#define CNA_CONV_CON2_CSC_DO_EN__SHIFT				1
 423static inline uint32_t CNA_CONV_CON2_CSC_DO_EN(uint32_t val)
 424{
 425	return ((val) << CNA_CONV_CON2_CSC_DO_EN__SHIFT) & CNA_CONV_CON2_CSC_DO_EN__MASK;
 426}
 427#define CNA_CONV_CON2_CMD_FIFO_SRST__MASK			0x00000001
 428#define CNA_CONV_CON2_CMD_FIFO_SRST__SHIFT			0
 429static inline uint32_t CNA_CONV_CON2_CMD_FIFO_SRST(uint32_t val)
 430{
 431	return ((val) << CNA_CONV_CON2_CMD_FIFO_SRST__SHIFT) & CNA_CONV_CON2_CMD_FIFO_SRST__MASK;
 432}
 433
 434#define REG_CNA_CONV_CON3					0x00001014
 435#define CNA_CONV_CON3_RESERVED_0__MASK				0x80000000
 436#define CNA_CONV_CON3_RESERVED_0__SHIFT				31
 437static inline uint32_t CNA_CONV_CON3_RESERVED_0(uint32_t val)
 438{
 439	return ((val) << CNA_CONV_CON3_RESERVED_0__SHIFT) & CNA_CONV_CON3_RESERVED_0__MASK;
 440}
 441#define CNA_CONV_CON3_NN_MODE__MASK				0x70000000
 442#define CNA_CONV_CON3_NN_MODE__SHIFT				28
 443static inline uint32_t CNA_CONV_CON3_NN_MODE(uint32_t val)
 444{
 445	return ((val) << CNA_CONV_CON3_NN_MODE__SHIFT) & CNA_CONV_CON3_NN_MODE__MASK;
 446}
 447#define CNA_CONV_CON3_RESERVED_1__MASK				0x0c000000
 448#define CNA_CONV_CON3_RESERVED_1__SHIFT				26
 449static inline uint32_t CNA_CONV_CON3_RESERVED_1(uint32_t val)
 450{
 451	return ((val) << CNA_CONV_CON3_RESERVED_1__SHIFT) & CNA_CONV_CON3_RESERVED_1__MASK;
 452}
 453#define CNA_CONV_CON3_ATROUS_Y_DILATION__MASK			0x03e00000
 454#define CNA_CONV_CON3_ATROUS_Y_DILATION__SHIFT			21
 455static inline uint32_t CNA_CONV_CON3_ATROUS_Y_DILATION(uint32_t val)
 456{
 457	return ((val) << CNA_CONV_CON3_ATROUS_Y_DILATION__SHIFT) & CNA_CONV_CON3_ATROUS_Y_DILATION__MASK;
 458}
 459#define CNA_CONV_CON3_ATROUS_X_DILATION__MASK			0x001f0000
 460#define CNA_CONV_CON3_ATROUS_X_DILATION__SHIFT			16
 461static inline uint32_t CNA_CONV_CON3_ATROUS_X_DILATION(uint32_t val)
 462{
 463	return ((val) << CNA_CONV_CON3_ATROUS_X_DILATION__SHIFT) & CNA_CONV_CON3_ATROUS_X_DILATION__MASK;
 464}
 465#define CNA_CONV_CON3_RESERVED_2__MASK				0x0000c000
 466#define CNA_CONV_CON3_RESERVED_2__SHIFT				14
 467static inline uint32_t CNA_CONV_CON3_RESERVED_2(uint32_t val)
 468{
 469	return ((val) << CNA_CONV_CON3_RESERVED_2__SHIFT) & CNA_CONV_CON3_RESERVED_2__MASK;
 470}
 471#define CNA_CONV_CON3_DECONV_Y_STRIDE__MASK			0x00003800
 472#define CNA_CONV_CON3_DECONV_Y_STRIDE__SHIFT			11
 473static inline uint32_t CNA_CONV_CON3_DECONV_Y_STRIDE(uint32_t val)
 474{
 475	return ((val) << CNA_CONV_CON3_DECONV_Y_STRIDE__SHIFT) & CNA_CONV_CON3_DECONV_Y_STRIDE__MASK;
 476}
 477#define CNA_CONV_CON3_DECONV_X_STRIDE__MASK			0x00000700
 478#define CNA_CONV_CON3_DECONV_X_STRIDE__SHIFT			8
 479static inline uint32_t CNA_CONV_CON3_DECONV_X_STRIDE(uint32_t val)
 480{
 481	return ((val) << CNA_CONV_CON3_DECONV_X_STRIDE__SHIFT) & CNA_CONV_CON3_DECONV_X_STRIDE__MASK;
 482}
 483#define CNA_CONV_CON3_RESERVED_3__MASK				0x000000c0
 484#define CNA_CONV_CON3_RESERVED_3__SHIFT				6
 485static inline uint32_t CNA_CONV_CON3_RESERVED_3(uint32_t val)
 486{
 487	return ((val) << CNA_CONV_CON3_RESERVED_3__SHIFT) & CNA_CONV_CON3_RESERVED_3__MASK;
 488}
 489#define CNA_CONV_CON3_CONV_Y_STRIDE__MASK			0x00000038
 490#define CNA_CONV_CON3_CONV_Y_STRIDE__SHIFT			3
 491static inline uint32_t CNA_CONV_CON3_CONV_Y_STRIDE(uint32_t val)
 492{
 493	return ((val) << CNA_CONV_CON3_CONV_Y_STRIDE__SHIFT) & CNA_CONV_CON3_CONV_Y_STRIDE__MASK;
 494}
 495#define CNA_CONV_CON3_CONV_X_STRIDE__MASK			0x00000007
 496#define CNA_CONV_CON3_CONV_X_STRIDE__SHIFT			0
 497static inline uint32_t CNA_CONV_CON3_CONV_X_STRIDE(uint32_t val)
 498{
 499	return ((val) << CNA_CONV_CON3_CONV_X_STRIDE__SHIFT) & CNA_CONV_CON3_CONV_X_STRIDE__MASK;
 500}
 501
 502#define REG_CNA_DATA_SIZE0					0x00001020
 503#define CNA_DATA_SIZE0_RESERVED_0__MASK				0xf8000000
 504#define CNA_DATA_SIZE0_RESERVED_0__SHIFT			27
 505static inline uint32_t CNA_DATA_SIZE0_RESERVED_0(uint32_t val)
 506{
 507	return ((val) << CNA_DATA_SIZE0_RESERVED_0__SHIFT) & CNA_DATA_SIZE0_RESERVED_0__MASK;
 508}
 509#define CNA_DATA_SIZE0_DATAIN_WIDTH__MASK			0x07ff0000
 510#define CNA_DATA_SIZE0_DATAIN_WIDTH__SHIFT			16
 511static inline uint32_t CNA_DATA_SIZE0_DATAIN_WIDTH(uint32_t val)
 512{
 513	return ((val) << CNA_DATA_SIZE0_DATAIN_WIDTH__SHIFT) & CNA_DATA_SIZE0_DATAIN_WIDTH__MASK;
 514}
 515#define CNA_DATA_SIZE0_RESERVED_1__MASK				0x0000f800
 516#define CNA_DATA_SIZE0_RESERVED_1__SHIFT			11
 517static inline uint32_t CNA_DATA_SIZE0_RESERVED_1(uint32_t val)
 518{
 519	return ((val) << CNA_DATA_SIZE0_RESERVED_1__SHIFT) & CNA_DATA_SIZE0_RESERVED_1__MASK;
 520}
 521#define CNA_DATA_SIZE0_DATAIN_HEIGHT__MASK			0x000007ff
 522#define CNA_DATA_SIZE0_DATAIN_HEIGHT__SHIFT			0
 523static inline uint32_t CNA_DATA_SIZE0_DATAIN_HEIGHT(uint32_t val)
 524{
 525	return ((val) << CNA_DATA_SIZE0_DATAIN_HEIGHT__SHIFT) & CNA_DATA_SIZE0_DATAIN_HEIGHT__MASK;
 526}
 527
 528#define REG_CNA_DATA_SIZE1					0x00001024
 529#define CNA_DATA_SIZE1_RESERVED_0__MASK				0xc0000000
 530#define CNA_DATA_SIZE1_RESERVED_0__SHIFT			30
 531static inline uint32_t CNA_DATA_SIZE1_RESERVED_0(uint32_t val)
 532{
 533	return ((val) << CNA_DATA_SIZE1_RESERVED_0__SHIFT) & CNA_DATA_SIZE1_RESERVED_0__MASK;
 534}
 535#define CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__MASK		0x3fff0000
 536#define CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__SHIFT		16
 537static inline uint32_t CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL(uint32_t val)
 538{
 539	return ((val) << CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__SHIFT) & CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__MASK;
 540}
 541#define CNA_DATA_SIZE1_DATAIN_CHANNEL__MASK			0x0000ffff
 542#define CNA_DATA_SIZE1_DATAIN_CHANNEL__SHIFT			0
 543static inline uint32_t CNA_DATA_SIZE1_DATAIN_CHANNEL(uint32_t val)
 544{
 545	return ((val) << CNA_DATA_SIZE1_DATAIN_CHANNEL__SHIFT) & CNA_DATA_SIZE1_DATAIN_CHANNEL__MASK;
 546}
 547
 548#define REG_CNA_DATA_SIZE2					0x00001028
 549#define CNA_DATA_SIZE2_RESERVED_0__MASK				0xfffff800
 550#define CNA_DATA_SIZE2_RESERVED_0__SHIFT			11
 551static inline uint32_t CNA_DATA_SIZE2_RESERVED_0(uint32_t val)
 552{
 553	return ((val) << CNA_DATA_SIZE2_RESERVED_0__SHIFT) & CNA_DATA_SIZE2_RESERVED_0__MASK;
 554}
 555#define CNA_DATA_SIZE2_DATAOUT_WIDTH__MASK			0x000007ff
 556#define CNA_DATA_SIZE2_DATAOUT_WIDTH__SHIFT			0
 557static inline uint32_t CNA_DATA_SIZE2_DATAOUT_WIDTH(uint32_t val)
 558{
 559	return ((val) << CNA_DATA_SIZE2_DATAOUT_WIDTH__SHIFT) & CNA_DATA_SIZE2_DATAOUT_WIDTH__MASK;
 560}
 561
 562#define REG_CNA_DATA_SIZE3					0x0000102c
 563#define CNA_DATA_SIZE3_RESERVED_0__MASK				0xff000000
 564#define CNA_DATA_SIZE3_RESERVED_0__SHIFT			24
 565static inline uint32_t CNA_DATA_SIZE3_RESERVED_0(uint32_t val)
 566{
 567	return ((val) << CNA_DATA_SIZE3_RESERVED_0__SHIFT) & CNA_DATA_SIZE3_RESERVED_0__MASK;
 568}
 569#define CNA_DATA_SIZE3_SURF_MODE__MASK				0x00c00000
 570#define CNA_DATA_SIZE3_SURF_MODE__SHIFT				22
 571static inline uint32_t CNA_DATA_SIZE3_SURF_MODE(uint32_t val)
 572{
 573	return ((val) << CNA_DATA_SIZE3_SURF_MODE__SHIFT) & CNA_DATA_SIZE3_SURF_MODE__MASK;
 574}
 575#define CNA_DATA_SIZE3_DATAOUT_ATOMICS__MASK			0x003fffff
 576#define CNA_DATA_SIZE3_DATAOUT_ATOMICS__SHIFT			0
 577static inline uint32_t CNA_DATA_SIZE3_DATAOUT_ATOMICS(uint32_t val)
 578{
 579	return ((val) << CNA_DATA_SIZE3_DATAOUT_ATOMICS__SHIFT) & CNA_DATA_SIZE3_DATAOUT_ATOMICS__MASK;
 580}
 581
 582#define REG_CNA_WEIGHT_SIZE0					0x00001030
 583#define CNA_WEIGHT_SIZE0_WEIGHT_BYTES__MASK			0xffffffff
 584#define CNA_WEIGHT_SIZE0_WEIGHT_BYTES__SHIFT			0
 585static inline uint32_t CNA_WEIGHT_SIZE0_WEIGHT_BYTES(uint32_t val)
 586{
 587	return ((val) << CNA_WEIGHT_SIZE0_WEIGHT_BYTES__SHIFT) & CNA_WEIGHT_SIZE0_WEIGHT_BYTES__MASK;
 588}
 589
 590#define REG_CNA_WEIGHT_SIZE1					0x00001034
 591#define CNA_WEIGHT_SIZE1_RESERVED_0__MASK			0xfff80000
 592#define CNA_WEIGHT_SIZE1_RESERVED_0__SHIFT			19
 593static inline uint32_t CNA_WEIGHT_SIZE1_RESERVED_0(uint32_t val)
 594{
 595	return ((val) << CNA_WEIGHT_SIZE1_RESERVED_0__SHIFT) & CNA_WEIGHT_SIZE1_RESERVED_0__MASK;
 596}
 597#define CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__MASK		0x0007ffff
 598#define CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__SHIFT		0
 599static inline uint32_t CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL(uint32_t val)
 600{
 601	return ((val) << CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__SHIFT) & CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__MASK;
 602}
 603
 604#define REG_CNA_WEIGHT_SIZE2					0x00001038
 605#define CNA_WEIGHT_SIZE2_RESERVED_0__MASK			0xe0000000
 606#define CNA_WEIGHT_SIZE2_RESERVED_0__SHIFT			29
 607static inline uint32_t CNA_WEIGHT_SIZE2_RESERVED_0(uint32_t val)
 608{
 609	return ((val) << CNA_WEIGHT_SIZE2_RESERVED_0__SHIFT) & CNA_WEIGHT_SIZE2_RESERVED_0__MASK;
 610}
 611#define CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__MASK			0x1f000000
 612#define CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__SHIFT			24
 613static inline uint32_t CNA_WEIGHT_SIZE2_WEIGHT_WIDTH(uint32_t val)
 614{
 615	return ((val) << CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__SHIFT) & CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__MASK;
 616}
 617#define CNA_WEIGHT_SIZE2_RESERVED_1__MASK			0x00e00000
 618#define CNA_WEIGHT_SIZE2_RESERVED_1__SHIFT			21
 619static inline uint32_t CNA_WEIGHT_SIZE2_RESERVED_1(uint32_t val)
 620{
 621	return ((val) << CNA_WEIGHT_SIZE2_RESERVED_1__SHIFT) & CNA_WEIGHT_SIZE2_RESERVED_1__MASK;
 622}
 623#define CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__MASK			0x001f0000
 624#define CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__SHIFT			16
 625static inline uint32_t CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT(uint32_t val)
 626{
 627	return ((val) << CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__SHIFT) & CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__MASK;
 628}
 629#define CNA_WEIGHT_SIZE2_RESERVED_2__MASK			0x0000c000
 630#define CNA_WEIGHT_SIZE2_RESERVED_2__SHIFT			14
 631static inline uint32_t CNA_WEIGHT_SIZE2_RESERVED_2(uint32_t val)
 632{
 633	return ((val) << CNA_WEIGHT_SIZE2_RESERVED_2__SHIFT) & CNA_WEIGHT_SIZE2_RESERVED_2__MASK;
 634}
 635#define CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__MASK			0x00003fff
 636#define CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__SHIFT			0
 637static inline uint32_t CNA_WEIGHT_SIZE2_WEIGHT_KERNELS(uint32_t val)
 638{
 639	return ((val) << CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__SHIFT) & CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__MASK;
 640}
 641
 642#define REG_CNA_CBUF_CON0					0x00001040
 643#define CNA_CBUF_CON0_RESERVED_0__MASK				0xffffc000
 644#define CNA_CBUF_CON0_RESERVED_0__SHIFT				14
 645static inline uint32_t CNA_CBUF_CON0_RESERVED_0(uint32_t val)
 646{
 647	return ((val) << CNA_CBUF_CON0_RESERVED_0__SHIFT) & CNA_CBUF_CON0_RESERVED_0__MASK;
 648}
 649#define CNA_CBUF_CON0_WEIGHT_REUSE__MASK			0x00002000
 650#define CNA_CBUF_CON0_WEIGHT_REUSE__SHIFT			13
 651static inline uint32_t CNA_CBUF_CON0_WEIGHT_REUSE(uint32_t val)
 652{
 653	return ((val) << CNA_CBUF_CON0_WEIGHT_REUSE__SHIFT) & CNA_CBUF_CON0_WEIGHT_REUSE__MASK;
 654}
 655#define CNA_CBUF_CON0_DATA_REUSE__MASK				0x00001000
 656#define CNA_CBUF_CON0_DATA_REUSE__SHIFT				12
 657static inline uint32_t CNA_CBUF_CON0_DATA_REUSE(uint32_t val)
 658{
 659	return ((val) << CNA_CBUF_CON0_DATA_REUSE__SHIFT) & CNA_CBUF_CON0_DATA_REUSE__MASK;
 660}
 661#define CNA_CBUF_CON0_RESERVED_1__MASK				0x00000800
 662#define CNA_CBUF_CON0_RESERVED_1__SHIFT				11
 663static inline uint32_t CNA_CBUF_CON0_RESERVED_1(uint32_t val)
 664{
 665	return ((val) << CNA_CBUF_CON0_RESERVED_1__SHIFT) & CNA_CBUF_CON0_RESERVED_1__MASK;
 666}
 667#define CNA_CBUF_CON0_FC_DATA_BANK__MASK			0x00000700
 668#define CNA_CBUF_CON0_FC_DATA_BANK__SHIFT			8
 669static inline uint32_t CNA_CBUF_CON0_FC_DATA_BANK(uint32_t val)
 670{
 671	return ((val) << CNA_CBUF_CON0_FC_DATA_BANK__SHIFT) & CNA_CBUF_CON0_FC_DATA_BANK__MASK;
 672}
 673#define CNA_CBUF_CON0_WEIGHT_BANK__MASK				0x000000f0
 674#define CNA_CBUF_CON0_WEIGHT_BANK__SHIFT			4
 675static inline uint32_t CNA_CBUF_CON0_WEIGHT_BANK(uint32_t val)
 676{
 677	return ((val) << CNA_CBUF_CON0_WEIGHT_BANK__SHIFT) & CNA_CBUF_CON0_WEIGHT_BANK__MASK;
 678}
 679#define CNA_CBUF_CON0_DATA_BANK__MASK				0x0000000f
 680#define CNA_CBUF_CON0_DATA_BANK__SHIFT				0
 681static inline uint32_t CNA_CBUF_CON0_DATA_BANK(uint32_t val)
 682{
 683	return ((val) << CNA_CBUF_CON0_DATA_BANK__SHIFT) & CNA_CBUF_CON0_DATA_BANK__MASK;
 684}
 685
 686#define REG_CNA_CBUF_CON1					0x00001044
 687#define CNA_CBUF_CON1_RESERVED_0__MASK				0xffffc000
 688#define CNA_CBUF_CON1_RESERVED_0__SHIFT				14
 689static inline uint32_t CNA_CBUF_CON1_RESERVED_0(uint32_t val)
 690{
 691	return ((val) << CNA_CBUF_CON1_RESERVED_0__SHIFT) & CNA_CBUF_CON1_RESERVED_0__MASK;
 692}
 693#define CNA_CBUF_CON1_DATA_ENTRIES__MASK			0x00003fff
 694#define CNA_CBUF_CON1_DATA_ENTRIES__SHIFT			0
 695static inline uint32_t CNA_CBUF_CON1_DATA_ENTRIES(uint32_t val)
 696{
 697	return ((val) << CNA_CBUF_CON1_DATA_ENTRIES__SHIFT) & CNA_CBUF_CON1_DATA_ENTRIES__MASK;
 698}
 699
 700#define REG_CNA_CVT_CON0					0x0000104c
 701#define CNA_CVT_CON0_RESERVED_0__MASK				0xf0000000
 702#define CNA_CVT_CON0_RESERVED_0__SHIFT				28
 703static inline uint32_t CNA_CVT_CON0_RESERVED_0(uint32_t val)
 704{
 705	return ((val) << CNA_CVT_CON0_RESERVED_0__SHIFT) & CNA_CVT_CON0_RESERVED_0__MASK;
 706}
 707#define CNA_CVT_CON0_CVT_TRUNCATE_3__MASK			0x0fc00000
 708#define CNA_CVT_CON0_CVT_TRUNCATE_3__SHIFT			22
 709static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_3(uint32_t val)
 710{
 711	return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_3__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_3__MASK;
 712}
 713#define CNA_CVT_CON0_CVT_TRUNCATE_2__MASK			0x003f0000
 714#define CNA_CVT_CON0_CVT_TRUNCATE_2__SHIFT			16
 715static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_2(uint32_t val)
 716{
 717	return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_2__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_2__MASK;
 718}
 719#define CNA_CVT_CON0_CVT_TRUNCATE_1__MASK			0x0000fc00
 720#define CNA_CVT_CON0_CVT_TRUNCATE_1__SHIFT			10
 721static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_1(uint32_t val)
 722{
 723	return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_1__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_1__MASK;
 724}
 725#define CNA_CVT_CON0_CVT_TRUNCATE_0__MASK			0x000003f0
 726#define CNA_CVT_CON0_CVT_TRUNCATE_0__SHIFT			4
 727static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_0(uint32_t val)
 728{
 729	return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_0__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_0__MASK;
 730}
 731#define CNA_CVT_CON0_DATA_SIGN__MASK				0x00000008
 732#define CNA_CVT_CON0_DATA_SIGN__SHIFT				3
 733static inline uint32_t CNA_CVT_CON0_DATA_SIGN(uint32_t val)
 734{
 735	return ((val) << CNA_CVT_CON0_DATA_SIGN__SHIFT) & CNA_CVT_CON0_DATA_SIGN__MASK;
 736}
 737#define CNA_CVT_CON0_ROUND_TYPE__MASK				0x00000004
 738#define CNA_CVT_CON0_ROUND_TYPE__SHIFT				2
 739static inline uint32_t CNA_CVT_CON0_ROUND_TYPE(uint32_t val)
 740{
 741	return ((val) << CNA_CVT_CON0_ROUND_TYPE__SHIFT) & CNA_CVT_CON0_ROUND_TYPE__MASK;
 742}
 743#define CNA_CVT_CON0_CVT_TYPE__MASK				0x00000002
 744#define CNA_CVT_CON0_CVT_TYPE__SHIFT				1
 745static inline uint32_t CNA_CVT_CON0_CVT_TYPE(uint32_t val)
 746{
 747	return ((val) << CNA_CVT_CON0_CVT_TYPE__SHIFT) & CNA_CVT_CON0_CVT_TYPE__MASK;
 748}
 749#define CNA_CVT_CON0_CVT_BYPASS__MASK				0x00000001
 750#define CNA_CVT_CON0_CVT_BYPASS__SHIFT				0
 751static inline uint32_t CNA_CVT_CON0_CVT_BYPASS(uint32_t val)
 752{
 753	return ((val) << CNA_CVT_CON0_CVT_BYPASS__SHIFT) & CNA_CVT_CON0_CVT_BYPASS__MASK;
 754}
 755
 756#define REG_CNA_CVT_CON1					0x00001050
 757#define CNA_CVT_CON1_CVT_SCALE0__MASK				0xffff0000
 758#define CNA_CVT_CON1_CVT_SCALE0__SHIFT				16
 759static inline uint32_t CNA_CVT_CON1_CVT_SCALE0(uint32_t val)
 760{
 761	return ((val) << CNA_CVT_CON1_CVT_SCALE0__SHIFT) & CNA_CVT_CON1_CVT_SCALE0__MASK;
 762}
 763#define CNA_CVT_CON1_CVT_OFFSET0__MASK				0x0000ffff
 764#define CNA_CVT_CON1_CVT_OFFSET0__SHIFT				0
 765static inline uint32_t CNA_CVT_CON1_CVT_OFFSET0(uint32_t val)
 766{
 767	return ((val) << CNA_CVT_CON1_CVT_OFFSET0__SHIFT) & CNA_CVT_CON1_CVT_OFFSET0__MASK;
 768}
 769
 770#define REG_CNA_CVT_CON2					0x00001054
 771#define CNA_CVT_CON2_CVT_SCALE1__MASK				0xffff0000
 772#define CNA_CVT_CON2_CVT_SCALE1__SHIFT				16
 773static inline uint32_t CNA_CVT_CON2_CVT_SCALE1(uint32_t val)
 774{
 775	return ((val) << CNA_CVT_CON2_CVT_SCALE1__SHIFT) & CNA_CVT_CON2_CVT_SCALE1__MASK;
 776}
 777#define CNA_CVT_CON2_CVT_OFFSET1__MASK				0x0000ffff
 778#define CNA_CVT_CON2_CVT_OFFSET1__SHIFT				0
 779static inline uint32_t CNA_CVT_CON2_CVT_OFFSET1(uint32_t val)
 780{
 781	return ((val) << CNA_CVT_CON2_CVT_OFFSET1__SHIFT) & CNA_CVT_CON2_CVT_OFFSET1__MASK;
 782}
 783
 784#define REG_CNA_CVT_CON3					0x00001058
 785#define CNA_CVT_CON3_CVT_SCALE2__MASK				0xffff0000
 786#define CNA_CVT_CON3_CVT_SCALE2__SHIFT				16
 787static inline uint32_t CNA_CVT_CON3_CVT_SCALE2(uint32_t val)
 788{
 789	return ((val) << CNA_CVT_CON3_CVT_SCALE2__SHIFT) & CNA_CVT_CON3_CVT_SCALE2__MASK;
 790}
 791#define CNA_CVT_CON3_CVT_OFFSET2__MASK				0x0000ffff
 792#define CNA_CVT_CON3_CVT_OFFSET2__SHIFT				0
 793static inline uint32_t CNA_CVT_CON3_CVT_OFFSET2(uint32_t val)
 794{
 795	return ((val) << CNA_CVT_CON3_CVT_OFFSET2__SHIFT) & CNA_CVT_CON3_CVT_OFFSET2__MASK;
 796}
 797
 798#define REG_CNA_CVT_CON4					0x0000105c
 799#define CNA_CVT_CON4_CVT_SCALE3__MASK				0xffff0000
 800#define CNA_CVT_CON4_CVT_SCALE3__SHIFT				16
 801static inline uint32_t CNA_CVT_CON4_CVT_SCALE3(uint32_t val)
 802{
 803	return ((val) << CNA_CVT_CON4_CVT_SCALE3__SHIFT) & CNA_CVT_CON4_CVT_SCALE3__MASK;
 804}
 805#define CNA_CVT_CON4_CVT_OFFSET3__MASK				0x0000ffff
 806#define CNA_CVT_CON4_CVT_OFFSET3__SHIFT				0
 807static inline uint32_t CNA_CVT_CON4_CVT_OFFSET3(uint32_t val)
 808{
 809	return ((val) << CNA_CVT_CON4_CVT_OFFSET3__SHIFT) & CNA_CVT_CON4_CVT_OFFSET3__MASK;
 810}
 811
 812#define REG_CNA_FC_CON0						0x00001060
 813#define CNA_FC_CON0_FC_SKIP_DATA__MASK				0xffff0000
 814#define CNA_FC_CON0_FC_SKIP_DATA__SHIFT				16
 815static inline uint32_t CNA_FC_CON0_FC_SKIP_DATA(uint32_t val)
 816{
 817	return ((val) << CNA_FC_CON0_FC_SKIP_DATA__SHIFT) & CNA_FC_CON0_FC_SKIP_DATA__MASK;
 818}
 819#define CNA_FC_CON0_RESERVED_0__MASK				0x0000fffe
 820#define CNA_FC_CON0_RESERVED_0__SHIFT				1
 821static inline uint32_t CNA_FC_CON0_RESERVED_0(uint32_t val)
 822{
 823	return ((val) << CNA_FC_CON0_RESERVED_0__SHIFT) & CNA_FC_CON0_RESERVED_0__MASK;
 824}
 825#define CNA_FC_CON0_FC_SKIP_EN__MASK				0x00000001
 826#define CNA_FC_CON0_FC_SKIP_EN__SHIFT				0
 827static inline uint32_t CNA_FC_CON0_FC_SKIP_EN(uint32_t val)
 828{
 829	return ((val) << CNA_FC_CON0_FC_SKIP_EN__SHIFT) & CNA_FC_CON0_FC_SKIP_EN__MASK;
 830}
 831
 832#define REG_CNA_FC_CON1						0x00001064
 833#define CNA_FC_CON1_RESERVED_0__MASK				0xfffe0000
 834#define CNA_FC_CON1_RESERVED_0__SHIFT				17
 835static inline uint32_t CNA_FC_CON1_RESERVED_0(uint32_t val)
 836{
 837	return ((val) << CNA_FC_CON1_RESERVED_0__SHIFT) & CNA_FC_CON1_RESERVED_0__MASK;
 838}
 839#define CNA_FC_CON1_DATA_OFFSET__MASK				0x0001ffff
 840#define CNA_FC_CON1_DATA_OFFSET__SHIFT				0
 841static inline uint32_t CNA_FC_CON1_DATA_OFFSET(uint32_t val)
 842{
 843	return ((val) << CNA_FC_CON1_DATA_OFFSET__SHIFT) & CNA_FC_CON1_DATA_OFFSET__MASK;
 844}
 845
 846#define REG_CNA_PAD_CON0					0x00001068
 847#define CNA_PAD_CON0_RESERVED_0__MASK				0xffffff00
 848#define CNA_PAD_CON0_RESERVED_0__SHIFT				8
 849static inline uint32_t CNA_PAD_CON0_RESERVED_0(uint32_t val)
 850{
 851	return ((val) << CNA_PAD_CON0_RESERVED_0__SHIFT) & CNA_PAD_CON0_RESERVED_0__MASK;
 852}
 853#define CNA_PAD_CON0_PAD_LEFT__MASK				0x000000f0
 854#define CNA_PAD_CON0_PAD_LEFT__SHIFT				4
 855static inline uint32_t CNA_PAD_CON0_PAD_LEFT(uint32_t val)
 856{
 857	return ((val) << CNA_PAD_CON0_PAD_LEFT__SHIFT) & CNA_PAD_CON0_PAD_LEFT__MASK;
 858}
 859#define CNA_PAD_CON0_PAD_TOP__MASK				0x0000000f
 860#define CNA_PAD_CON0_PAD_TOP__SHIFT				0
 861static inline uint32_t CNA_PAD_CON0_PAD_TOP(uint32_t val)
 862{
 863	return ((val) << CNA_PAD_CON0_PAD_TOP__SHIFT) & CNA_PAD_CON0_PAD_TOP__MASK;
 864}
 865
 866#define REG_CNA_FEATURE_DATA_ADDR				0x00001070
 867#define CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__MASK		0xffffffff
 868#define CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__SHIFT		0
 869static inline uint32_t CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR(uint32_t val)
 870{
 871	return ((val) << CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__SHIFT) & CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__MASK;
 872}
 873
 874#define REG_CNA_FC_CON2						0x00001074
 875#define CNA_FC_CON2_RESERVED_0__MASK				0xfffe0000
 876#define CNA_FC_CON2_RESERVED_0__SHIFT				17
 877static inline uint32_t CNA_FC_CON2_RESERVED_0(uint32_t val)
 878{
 879	return ((val) << CNA_FC_CON2_RESERVED_0__SHIFT) & CNA_FC_CON2_RESERVED_0__MASK;
 880}
 881#define CNA_FC_CON2_WEIGHT_OFFSET__MASK				0x0001ffff
 882#define CNA_FC_CON2_WEIGHT_OFFSET__SHIFT			0
 883static inline uint32_t CNA_FC_CON2_WEIGHT_OFFSET(uint32_t val)
 884{
 885	return ((val) << CNA_FC_CON2_WEIGHT_OFFSET__SHIFT) & CNA_FC_CON2_WEIGHT_OFFSET__MASK;
 886}
 887
 888#define REG_CNA_DMA_CON0					0x00001078
 889#define CNA_DMA_CON0_OV4K_BYPASS__MASK				0x80000000
 890#define CNA_DMA_CON0_OV4K_BYPASS__SHIFT				31
 891static inline uint32_t CNA_DMA_CON0_OV4K_BYPASS(uint32_t val)
 892{
 893	return ((val) << CNA_DMA_CON0_OV4K_BYPASS__SHIFT) & CNA_DMA_CON0_OV4K_BYPASS__MASK;
 894}
 895#define CNA_DMA_CON0_RESERVED_0__MASK				0x7ff00000
 896#define CNA_DMA_CON0_RESERVED_0__SHIFT				20
 897static inline uint32_t CNA_DMA_CON0_RESERVED_0(uint32_t val)
 898{
 899	return ((val) << CNA_DMA_CON0_RESERVED_0__SHIFT) & CNA_DMA_CON0_RESERVED_0__MASK;
 900}
 901#define CNA_DMA_CON0_WEIGHT_BURST_LEN__MASK			0x000f0000
 902#define CNA_DMA_CON0_WEIGHT_BURST_LEN__SHIFT			16
 903static inline uint32_t CNA_DMA_CON0_WEIGHT_BURST_LEN(uint32_t val)
 904{
 905	return ((val) << CNA_DMA_CON0_WEIGHT_BURST_LEN__SHIFT) & CNA_DMA_CON0_WEIGHT_BURST_LEN__MASK;
 906}
 907#define CNA_DMA_CON0_RESERVED_1__MASK				0x0000fff0
 908#define CNA_DMA_CON0_RESERVED_1__SHIFT				4
 909static inline uint32_t CNA_DMA_CON0_RESERVED_1(uint32_t val)
 910{
 911	return ((val) << CNA_DMA_CON0_RESERVED_1__SHIFT) & CNA_DMA_CON0_RESERVED_1__MASK;
 912}
 913#define CNA_DMA_CON0_DATA_BURST_LEN__MASK			0x0000000f
 914#define CNA_DMA_CON0_DATA_BURST_LEN__SHIFT			0
 915static inline uint32_t CNA_DMA_CON0_DATA_BURST_LEN(uint32_t val)
 916{
 917	return ((val) << CNA_DMA_CON0_DATA_BURST_LEN__SHIFT) & CNA_DMA_CON0_DATA_BURST_LEN__MASK;
 918}
 919
 920#define REG_CNA_DMA_CON1					0x0000107c
 921#define CNA_DMA_CON1_RESERVED_0__MASK				0xf0000000
 922#define CNA_DMA_CON1_RESERVED_0__SHIFT				28
 923static inline uint32_t CNA_DMA_CON1_RESERVED_0(uint32_t val)
 924{
 925	return ((val) << CNA_DMA_CON1_RESERVED_0__SHIFT) & CNA_DMA_CON1_RESERVED_0__MASK;
 926}
 927#define CNA_DMA_CON1_LINE_STRIDE__MASK				0x0fffffff
 928#define CNA_DMA_CON1_LINE_STRIDE__SHIFT				0
 929static inline uint32_t CNA_DMA_CON1_LINE_STRIDE(uint32_t val)
 930{
 931	return ((val) << CNA_DMA_CON1_LINE_STRIDE__SHIFT) & CNA_DMA_CON1_LINE_STRIDE__MASK;
 932}
 933
 934#define REG_CNA_DMA_CON2					0x00001080
 935#define CNA_DMA_CON2_RESERVED_0__MASK				0xf0000000
 936#define CNA_DMA_CON2_RESERVED_0__SHIFT				28
 937static inline uint32_t CNA_DMA_CON2_RESERVED_0(uint32_t val)
 938{
 939	return ((val) << CNA_DMA_CON2_RESERVED_0__SHIFT) & CNA_DMA_CON2_RESERVED_0__MASK;
 940}
 941#define CNA_DMA_CON2_SURF_STRIDE__MASK				0x0fffffff
 942#define CNA_DMA_CON2_SURF_STRIDE__SHIFT				0
 943static inline uint32_t CNA_DMA_CON2_SURF_STRIDE(uint32_t val)
 944{
 945	return ((val) << CNA_DMA_CON2_SURF_STRIDE__SHIFT) & CNA_DMA_CON2_SURF_STRIDE__MASK;
 946}
 947
 948#define REG_CNA_FC_DATA_SIZE0					0x00001084
 949#define CNA_FC_DATA_SIZE0_RESERVED_0__MASK			0xc0000000
 950#define CNA_FC_DATA_SIZE0_RESERVED_0__SHIFT			30
 951static inline uint32_t CNA_FC_DATA_SIZE0_RESERVED_0(uint32_t val)
 952{
 953	return ((val) << CNA_FC_DATA_SIZE0_RESERVED_0__SHIFT) & CNA_FC_DATA_SIZE0_RESERVED_0__MASK;
 954}
 955#define CNA_FC_DATA_SIZE0_DMA_WIDTH__MASK			0x3fff0000
 956#define CNA_FC_DATA_SIZE0_DMA_WIDTH__SHIFT			16
 957static inline uint32_t CNA_FC_DATA_SIZE0_DMA_WIDTH(uint32_t val)
 958{
 959	return ((val) << CNA_FC_DATA_SIZE0_DMA_WIDTH__SHIFT) & CNA_FC_DATA_SIZE0_DMA_WIDTH__MASK;
 960}
 961#define CNA_FC_DATA_SIZE0_RESERVED_1__MASK			0x0000f800
 962#define CNA_FC_DATA_SIZE0_RESERVED_1__SHIFT			11
 963static inline uint32_t CNA_FC_DATA_SIZE0_RESERVED_1(uint32_t val)
 964{
 965	return ((val) << CNA_FC_DATA_SIZE0_RESERVED_1__SHIFT) & CNA_FC_DATA_SIZE0_RESERVED_1__MASK;
 966}
 967#define CNA_FC_DATA_SIZE0_DMA_HEIGHT__MASK			0x000007ff
 968#define CNA_FC_DATA_SIZE0_DMA_HEIGHT__SHIFT			0
 969static inline uint32_t CNA_FC_DATA_SIZE0_DMA_HEIGHT(uint32_t val)
 970{
 971	return ((val) << CNA_FC_DATA_SIZE0_DMA_HEIGHT__SHIFT) & CNA_FC_DATA_SIZE0_DMA_HEIGHT__MASK;
 972}
 973
 974#define REG_CNA_FC_DATA_SIZE1					0x00001088
 975#define CNA_FC_DATA_SIZE1_RESERVED_0__MASK			0xffff0000
 976#define CNA_FC_DATA_SIZE1_RESERVED_0__SHIFT			16
 977static inline uint32_t CNA_FC_DATA_SIZE1_RESERVED_0(uint32_t val)
 978{
 979	return ((val) << CNA_FC_DATA_SIZE1_RESERVED_0__SHIFT) & CNA_FC_DATA_SIZE1_RESERVED_0__MASK;
 980}
 981#define CNA_FC_DATA_SIZE1_DMA_CHANNEL__MASK			0x0000ffff
 982#define CNA_FC_DATA_SIZE1_DMA_CHANNEL__SHIFT			0
 983static inline uint32_t CNA_FC_DATA_SIZE1_DMA_CHANNEL(uint32_t val)
 984{
 985	return ((val) << CNA_FC_DATA_SIZE1_DMA_CHANNEL__SHIFT) & CNA_FC_DATA_SIZE1_DMA_CHANNEL__MASK;
 986}
 987
 988#define REG_CNA_CLK_GATE					0x00001090
 989#define CNA_CLK_GATE_RESERVED_0__MASK				0xffffffe0
 990#define CNA_CLK_GATE_RESERVED_0__SHIFT				5
 991static inline uint32_t CNA_CLK_GATE_RESERVED_0(uint32_t val)
 992{
 993	return ((val) << CNA_CLK_GATE_RESERVED_0__SHIFT) & CNA_CLK_GATE_RESERVED_0__MASK;
 994}
 995#define CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__MASK		0x00000010
 996#define CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__SHIFT		4
 997static inline uint32_t CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE(uint32_t val)
 998{
 999	return ((val) << CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__MASK;
1000}
1001#define CNA_CLK_GATE_RESERVED_1__MASK				0x00000008
1002#define CNA_CLK_GATE_RESERVED_1__SHIFT				3
1003static inline uint32_t CNA_CLK_GATE_RESERVED_1(uint32_t val)
1004{
1005	return ((val) << CNA_CLK_GATE_RESERVED_1__SHIFT) & CNA_CLK_GATE_RESERVED_1__MASK;
1006}
1007#define CNA_CLK_GATE_CSC_DISABLE_CLKGATE__MASK			0x00000004
1008#define CNA_CLK_GATE_CSC_DISABLE_CLKGATE__SHIFT			2
1009static inline uint32_t CNA_CLK_GATE_CSC_DISABLE_CLKGATE(uint32_t val)
1010{
1011	return ((val) << CNA_CLK_GATE_CSC_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CSC_DISABLE_CLKGATE__MASK;
1012}
1013#define CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__MASK		0x00000002
1014#define CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__SHIFT		1
1015static inline uint32_t CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE(uint32_t val)
1016{
1017	return ((val) << CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__MASK;
1018}
1019#define CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__MASK		0x00000001
1020#define CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__SHIFT		0
1021static inline uint32_t CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE(uint32_t val)
1022{
1023	return ((val) << CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__MASK;
1024}
1025
1026#define REG_CNA_DCOMP_CTRL					0x00001100
1027#define CNA_DCOMP_CTRL_RESERVED_0__MASK				0xfffffff0
1028#define CNA_DCOMP_CTRL_RESERVED_0__SHIFT			4
1029static inline uint32_t CNA_DCOMP_CTRL_RESERVED_0(uint32_t val)
1030{
1031	return ((val) << CNA_DCOMP_CTRL_RESERVED_0__SHIFT) & CNA_DCOMP_CTRL_RESERVED_0__MASK;
1032}
1033#define CNA_DCOMP_CTRL_WT_DEC_BYPASS__MASK			0x00000008
1034#define CNA_DCOMP_CTRL_WT_DEC_BYPASS__SHIFT			3
1035static inline uint32_t CNA_DCOMP_CTRL_WT_DEC_BYPASS(uint32_t val)
1036{
1037	return ((val) << CNA_DCOMP_CTRL_WT_DEC_BYPASS__SHIFT) & CNA_DCOMP_CTRL_WT_DEC_BYPASS__MASK;
1038}
1039#define CNA_DCOMP_CTRL_DECOMP_CONTROL__MASK			0x00000007
1040#define CNA_DCOMP_CTRL_DECOMP_CONTROL__SHIFT			0
1041static inline uint32_t CNA_DCOMP_CTRL_DECOMP_CONTROL(uint32_t val)
1042{
1043	return ((val) << CNA_DCOMP_CTRL_DECOMP_CONTROL__SHIFT) & CNA_DCOMP_CTRL_DECOMP_CONTROL__MASK;
1044}
1045
1046#define REG_CNA_DCOMP_REGNUM					0x00001104
1047#define CNA_DCOMP_REGNUM_DCOMP_REGNUM__MASK			0xffffffff
1048#define CNA_DCOMP_REGNUM_DCOMP_REGNUM__SHIFT			0
1049static inline uint32_t CNA_DCOMP_REGNUM_DCOMP_REGNUM(uint32_t val)
1050{
1051	return ((val) << CNA_DCOMP_REGNUM_DCOMP_REGNUM__SHIFT) & CNA_DCOMP_REGNUM_DCOMP_REGNUM__MASK;
1052}
1053
1054#define REG_CNA_DCOMP_ADDR0					0x00001110
1055#define CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__MASK			0xffffffff
1056#define CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__SHIFT			0
1057static inline uint32_t CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0(uint32_t val)
1058{
1059	return ((val) << CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__SHIFT) & CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__MASK;
1060}
1061
1062#define REG_CNA_DCOMP_AMOUNT0					0x00001140
1063#define CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__MASK			0xffffffff
1064#define CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__SHIFT			0
1065static inline uint32_t CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0(uint32_t val)
1066{
1067	return ((val) << CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__SHIFT) & CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__MASK;
1068}
1069
1070#define REG_CNA_DCOMP_AMOUNT1					0x00001144
1071#define CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__MASK			0xffffffff
1072#define CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__SHIFT			0
1073static inline uint32_t CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1(uint32_t val)
1074{
1075	return ((val) << CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__SHIFT) & CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__MASK;
1076}
1077
1078#define REG_CNA_DCOMP_AMOUNT2					0x00001148
1079#define CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__MASK			0xffffffff
1080#define CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__SHIFT			0
1081static inline uint32_t CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2(uint32_t val)
1082{
1083	return ((val) << CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__SHIFT) & CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__MASK;
1084}
1085
1086#define REG_CNA_DCOMP_AMOUNT3					0x0000114c
1087#define CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__MASK			0xffffffff
1088#define CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__SHIFT			0
1089static inline uint32_t CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3(uint32_t val)
1090{
1091	return ((val) << CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__SHIFT) & CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__MASK;
1092}
1093
1094#define REG_CNA_DCOMP_AMOUNT4					0x00001150
1095#define CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__MASK			0xffffffff
1096#define CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__SHIFT			0
1097static inline uint32_t CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4(uint32_t val)
1098{
1099	return ((val) << CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__SHIFT) & CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__MASK;
1100}
1101
1102#define REG_CNA_DCOMP_AMOUNT5					0x00001154
1103#define CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__MASK			0xffffffff
1104#define CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__SHIFT			0
1105static inline uint32_t CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5(uint32_t val)
1106{
1107	return ((val) << CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__SHIFT) & CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__MASK;
1108}
1109
1110#define REG_CNA_DCOMP_AMOUNT6					0x00001158
1111#define CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__MASK			0xffffffff
1112#define CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__SHIFT			0
1113static inline uint32_t CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6(uint32_t val)
1114{
1115	return ((val) << CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__SHIFT) & CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__MASK;
1116}
1117
1118#define REG_CNA_DCOMP_AMOUNT7					0x0000115c
1119#define CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__MASK			0xffffffff
1120#define CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__SHIFT			0
1121static inline uint32_t CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7(uint32_t val)
1122{
1123	return ((val) << CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__SHIFT) & CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__MASK;
1124}
1125
1126#define REG_CNA_DCOMP_AMOUNT8					0x00001160
1127#define CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__MASK			0xffffffff
1128#define CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__SHIFT			0
1129static inline uint32_t CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8(uint32_t val)
1130{
1131	return ((val) << CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__SHIFT) & CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__MASK;
1132}
1133
1134#define REG_CNA_DCOMP_AMOUNT9					0x00001164
1135#define CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__MASK			0xffffffff
1136#define CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__SHIFT			0
1137static inline uint32_t CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9(uint32_t val)
1138{
1139	return ((val) << CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__SHIFT) & CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__MASK;
1140}
1141
1142#define REG_CNA_DCOMP_AMOUNT10					0x00001168
1143#define CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__MASK			0xffffffff
1144#define CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__SHIFT		0
1145static inline uint32_t CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10(uint32_t val)
1146{
1147	return ((val) << CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__SHIFT) & CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__MASK;
1148}
1149
1150#define REG_CNA_DCOMP_AMOUNT11					0x0000116c
1151#define CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__MASK			0xffffffff
1152#define CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__SHIFT		0
1153static inline uint32_t CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11(uint32_t val)
1154{
1155	return ((val) << CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__SHIFT) & CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__MASK;
1156}
1157
1158#define REG_CNA_DCOMP_AMOUNT12					0x00001170
1159#define CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__MASK			0xffffffff
1160#define CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__SHIFT		0
1161static inline uint32_t CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12(uint32_t val)
1162{
1163	return ((val) << CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__SHIFT) & CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__MASK;
1164}
1165
1166#define REG_CNA_DCOMP_AMOUNT13					0x00001174
1167#define CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__MASK			0xffffffff
1168#define CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__SHIFT		0
1169static inline uint32_t CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13(uint32_t val)
1170{
1171	return ((val) << CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__SHIFT) & CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__MASK;
1172}
1173
1174#define REG_CNA_DCOMP_AMOUNT14					0x00001178
1175#define CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__MASK			0xffffffff
1176#define CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__SHIFT		0
1177static inline uint32_t CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14(uint32_t val)
1178{
1179	return ((val) << CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__SHIFT) & CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__MASK;
1180}
1181
1182#define REG_CNA_DCOMP_AMOUNT15					0x0000117c
1183#define CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__MASK			0xffffffff
1184#define CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__SHIFT		0
1185static inline uint32_t CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15(uint32_t val)
1186{
1187	return ((val) << CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__SHIFT) & CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__MASK;
1188}
1189
1190#define REG_CNA_CVT_CON5					0x00001180
1191#define CNA_CVT_CON5_PER_CHANNEL_CVT_EN__MASK			0xffffffff
1192#define CNA_CVT_CON5_PER_CHANNEL_CVT_EN__SHIFT			0
1193static inline uint32_t CNA_CVT_CON5_PER_CHANNEL_CVT_EN(uint32_t val)
1194{
1195	return ((val) << CNA_CVT_CON5_PER_CHANNEL_CVT_EN__SHIFT) & CNA_CVT_CON5_PER_CHANNEL_CVT_EN__MASK;
1196}
1197
1198#define REG_CNA_PAD_CON1					0x00001184
1199#define CNA_PAD_CON1_PAD_VALUE__MASK				0xffffffff
1200#define CNA_PAD_CON1_PAD_VALUE__SHIFT				0
1201static inline uint32_t CNA_PAD_CON1_PAD_VALUE(uint32_t val)
1202{
1203	return ((val) << CNA_PAD_CON1_PAD_VALUE__SHIFT) & CNA_PAD_CON1_PAD_VALUE__MASK;
1204}
1205
1206#define REG_CORE_S_STATUS					0x00003000
1207#define CORE_S_STATUS_RESERVED_0__MASK				0xfffc0000
1208#define CORE_S_STATUS_RESERVED_0__SHIFT				18
1209static inline uint32_t CORE_S_STATUS_RESERVED_0(uint32_t val)
1210{
1211	return ((val) << CORE_S_STATUS_RESERVED_0__SHIFT) & CORE_S_STATUS_RESERVED_0__MASK;
1212}
1213#define CORE_S_STATUS_STATUS_1__MASK				0x00030000
1214#define CORE_S_STATUS_STATUS_1__SHIFT				16
1215static inline uint32_t CORE_S_STATUS_STATUS_1(uint32_t val)
1216{
1217	return ((val) << CORE_S_STATUS_STATUS_1__SHIFT) & CORE_S_STATUS_STATUS_1__MASK;
1218}
1219#define CORE_S_STATUS_RESERVED_1__MASK				0x0000fffc
1220#define CORE_S_STATUS_RESERVED_1__SHIFT				2
1221static inline uint32_t CORE_S_STATUS_RESERVED_1(uint32_t val)
1222{
1223	return ((val) << CORE_S_STATUS_RESERVED_1__SHIFT) & CORE_S_STATUS_RESERVED_1__MASK;
1224}
1225#define CORE_S_STATUS_STATUS_0__MASK				0x00000003
1226#define CORE_S_STATUS_STATUS_0__SHIFT				0
1227static inline uint32_t CORE_S_STATUS_STATUS_0(uint32_t val)
1228{
1229	return ((val) << CORE_S_STATUS_STATUS_0__SHIFT) & CORE_S_STATUS_STATUS_0__MASK;
1230}
1231
1232#define REG_CORE_S_POINTER					0x00003004
1233#define CORE_S_POINTER_RESERVED_0__MASK				0xfffe0000
1234#define CORE_S_POINTER_RESERVED_0__SHIFT			17
1235static inline uint32_t CORE_S_POINTER_RESERVED_0(uint32_t val)
1236{
1237	return ((val) << CORE_S_POINTER_RESERVED_0__SHIFT) & CORE_S_POINTER_RESERVED_0__MASK;
1238}
1239#define CORE_S_POINTER_EXECUTER__MASK				0x00010000
1240#define CORE_S_POINTER_EXECUTER__SHIFT				16
1241static inline uint32_t CORE_S_POINTER_EXECUTER(uint32_t val)
1242{
1243	return ((val) << CORE_S_POINTER_EXECUTER__SHIFT) & CORE_S_POINTER_EXECUTER__MASK;
1244}
1245#define CORE_S_POINTER_RESERVED_1__MASK				0x0000ffc0
1246#define CORE_S_POINTER_RESERVED_1__SHIFT			6
1247static inline uint32_t CORE_S_POINTER_RESERVED_1(uint32_t val)
1248{
1249	return ((val) << CORE_S_POINTER_RESERVED_1__SHIFT) & CORE_S_POINTER_RESERVED_1__MASK;
1250}
1251#define CORE_S_POINTER_EXECUTER_PP_CLEAR__MASK			0x00000020
1252#define CORE_S_POINTER_EXECUTER_PP_CLEAR__SHIFT			5
1253static inline uint32_t CORE_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
1254{
1255	return ((val) << CORE_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & CORE_S_POINTER_EXECUTER_PP_CLEAR__MASK;
1256}
1257#define CORE_S_POINTER_POINTER_PP_CLEAR__MASK			0x00000010
1258#define CORE_S_POINTER_POINTER_PP_CLEAR__SHIFT			4
1259static inline uint32_t CORE_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
1260{
1261	return ((val) << CORE_S_POINTER_POINTER_PP_CLEAR__SHIFT) & CORE_S_POINTER_POINTER_PP_CLEAR__MASK;
1262}
1263#define CORE_S_POINTER_POINTER_PP_MODE__MASK			0x00000008
1264#define CORE_S_POINTER_POINTER_PP_MODE__SHIFT			3
1265static inline uint32_t CORE_S_POINTER_POINTER_PP_MODE(uint32_t val)
1266{
1267	return ((val) << CORE_S_POINTER_POINTER_PP_MODE__SHIFT) & CORE_S_POINTER_POINTER_PP_MODE__MASK;
1268}
1269#define CORE_S_POINTER_EXECUTER_PP_EN__MASK			0x00000004
1270#define CORE_S_POINTER_EXECUTER_PP_EN__SHIFT			2
1271static inline uint32_t CORE_S_POINTER_EXECUTER_PP_EN(uint32_t val)
1272{
1273	return ((val) << CORE_S_POINTER_EXECUTER_PP_EN__SHIFT) & CORE_S_POINTER_EXECUTER_PP_EN__MASK;
1274}
1275#define CORE_S_POINTER_POINTER_PP_EN__MASK			0x00000002
1276#define CORE_S_POINTER_POINTER_PP_EN__SHIFT			1
1277static inline uint32_t CORE_S_POINTER_POINTER_PP_EN(uint32_t val)
1278{
1279	return ((val) << CORE_S_POINTER_POINTER_PP_EN__SHIFT) & CORE_S_POINTER_POINTER_PP_EN__MASK;
1280}
1281#define CORE_S_POINTER_POINTER__MASK				0x00000001
1282#define CORE_S_POINTER_POINTER__SHIFT				0
1283static inline uint32_t CORE_S_POINTER_POINTER(uint32_t val)
1284{
1285	return ((val) << CORE_S_POINTER_POINTER__SHIFT) & CORE_S_POINTER_POINTER__MASK;
1286}
1287
1288#define REG_CORE_OPERATION_ENABLE				0x00003008
1289#define CORE_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
1290#define CORE_OPERATION_ENABLE_RESERVED_0__SHIFT			1
1291static inline uint32_t CORE_OPERATION_ENABLE_RESERVED_0(uint32_t val)
1292{
1293	return ((val) << CORE_OPERATION_ENABLE_RESERVED_0__SHIFT) & CORE_OPERATION_ENABLE_RESERVED_0__MASK;
1294}
1295#define CORE_OPERATION_ENABLE_OP_EN__MASK			0x00000001
1296#define CORE_OPERATION_ENABLE_OP_EN__SHIFT			0
1297static inline uint32_t CORE_OPERATION_ENABLE_OP_EN(uint32_t val)
1298{
1299	return ((val) << CORE_OPERATION_ENABLE_OP_EN__SHIFT) & CORE_OPERATION_ENABLE_OP_EN__MASK;
1300}
1301
1302#define REG_CORE_MAC_GATING					0x0000300c
1303#define CORE_MAC_GATING_RESERVED_0__MASK			0xf8000000
1304#define CORE_MAC_GATING_RESERVED_0__SHIFT			27
1305static inline uint32_t CORE_MAC_GATING_RESERVED_0(uint32_t val)
1306{
1307	return ((val) << CORE_MAC_GATING_RESERVED_0__SHIFT) & CORE_MAC_GATING_RESERVED_0__MASK;
1308}
1309#define CORE_MAC_GATING_SLCG_OP_EN__MASK			0x07ffffff
1310#define CORE_MAC_GATING_SLCG_OP_EN__SHIFT			0
1311static inline uint32_t CORE_MAC_GATING_SLCG_OP_EN(uint32_t val)
1312{
1313	return ((val) << CORE_MAC_GATING_SLCG_OP_EN__SHIFT) & CORE_MAC_GATING_SLCG_OP_EN__MASK;
1314}
1315
1316#define REG_CORE_MISC_CFG					0x00003010
1317#define CORE_MISC_CFG_RESERVED_0__MASK				0xfff00000
1318#define CORE_MISC_CFG_RESERVED_0__SHIFT				20
1319static inline uint32_t CORE_MISC_CFG_RESERVED_0(uint32_t val)
1320{
1321	return ((val) << CORE_MISC_CFG_RESERVED_0__SHIFT) & CORE_MISC_CFG_RESERVED_0__MASK;
1322}
1323#define CORE_MISC_CFG_SOFT_GATING__MASK				0x000fc000
1324#define CORE_MISC_CFG_SOFT_GATING__SHIFT			14
1325static inline uint32_t CORE_MISC_CFG_SOFT_GATING(uint32_t val)
1326{
1327	return ((val) << CORE_MISC_CFG_SOFT_GATING__SHIFT) & CORE_MISC_CFG_SOFT_GATING__MASK;
1328}
1329#define CORE_MISC_CFG_RESERVED_1__MASK				0x00003800
1330#define CORE_MISC_CFG_RESERVED_1__SHIFT				11
1331static inline uint32_t CORE_MISC_CFG_RESERVED_1(uint32_t val)
1332{
1333	return ((val) << CORE_MISC_CFG_RESERVED_1__SHIFT) & CORE_MISC_CFG_RESERVED_1__MASK;
1334}
1335#define CORE_MISC_CFG_PROC_PRECISION__MASK			0x00000700
1336#define CORE_MISC_CFG_PROC_PRECISION__SHIFT			8
1337static inline uint32_t CORE_MISC_CFG_PROC_PRECISION(uint32_t val)
1338{
1339	return ((val) << CORE_MISC_CFG_PROC_PRECISION__SHIFT) & CORE_MISC_CFG_PROC_PRECISION__MASK;
1340}
1341#define CORE_MISC_CFG_RESERVED_2__MASK				0x000000fc
1342#define CORE_MISC_CFG_RESERVED_2__SHIFT				2
1343static inline uint32_t CORE_MISC_CFG_RESERVED_2(uint32_t val)
1344{
1345	return ((val) << CORE_MISC_CFG_RESERVED_2__SHIFT) & CORE_MISC_CFG_RESERVED_2__MASK;
1346}
1347#define CORE_MISC_CFG_DW_EN__MASK				0x00000002
1348#define CORE_MISC_CFG_DW_EN__SHIFT				1
1349static inline uint32_t CORE_MISC_CFG_DW_EN(uint32_t val)
1350{
1351	return ((val) << CORE_MISC_CFG_DW_EN__SHIFT) & CORE_MISC_CFG_DW_EN__MASK;
1352}
1353#define CORE_MISC_CFG_QD_EN__MASK				0x00000001
1354#define CORE_MISC_CFG_QD_EN__SHIFT				0
1355static inline uint32_t CORE_MISC_CFG_QD_EN(uint32_t val)
1356{
1357	return ((val) << CORE_MISC_CFG_QD_EN__SHIFT) & CORE_MISC_CFG_QD_EN__MASK;
1358}
1359
1360#define REG_CORE_DATAOUT_SIZE_0					0x00003014
1361#define CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__MASK		0xffff0000
1362#define CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__SHIFT		16
1363static inline uint32_t CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT(uint32_t val)
1364{
1365	return ((val) << CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__SHIFT) & CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__MASK;
1366}
1367#define CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__MASK			0x0000ffff
1368#define CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__SHIFT		0
1369static inline uint32_t CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH(uint32_t val)
1370{
1371	return ((val) << CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__SHIFT) & CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__MASK;
1372}
1373
1374#define REG_CORE_DATAOUT_SIZE_1					0x00003018
1375#define CORE_DATAOUT_SIZE_1_RESERVED_0__MASK			0xffff0000
1376#define CORE_DATAOUT_SIZE_1_RESERVED_0__SHIFT			16
1377static inline uint32_t CORE_DATAOUT_SIZE_1_RESERVED_0(uint32_t val)
1378{
1379	return ((val) << CORE_DATAOUT_SIZE_1_RESERVED_0__SHIFT) & CORE_DATAOUT_SIZE_1_RESERVED_0__MASK;
1380}
1381#define CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__MASK		0x0000ffff
1382#define CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__SHIFT		0
1383static inline uint32_t CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL(uint32_t val)
1384{
1385	return ((val) << CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__SHIFT) & CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__MASK;
1386}
1387
1388#define REG_CORE_CLIP_TRUNCATE					0x0000301c
1389#define CORE_CLIP_TRUNCATE_RESERVED_0__MASK			0xffffff80
1390#define CORE_CLIP_TRUNCATE_RESERVED_0__SHIFT			7
1391static inline uint32_t CORE_CLIP_TRUNCATE_RESERVED_0(uint32_t val)
1392{
1393	return ((val) << CORE_CLIP_TRUNCATE_RESERVED_0__SHIFT) & CORE_CLIP_TRUNCATE_RESERVED_0__MASK;
1394}
1395#define CORE_CLIP_TRUNCATE_ROUND_TYPE__MASK			0x00000040
1396#define CORE_CLIP_TRUNCATE_ROUND_TYPE__SHIFT			6
1397static inline uint32_t CORE_CLIP_TRUNCATE_ROUND_TYPE(uint32_t val)
1398{
1399	return ((val) << CORE_CLIP_TRUNCATE_ROUND_TYPE__SHIFT) & CORE_CLIP_TRUNCATE_ROUND_TYPE__MASK;
1400}
1401#define CORE_CLIP_TRUNCATE_RESERVED_1__MASK			0x00000020
1402#define CORE_CLIP_TRUNCATE_RESERVED_1__SHIFT			5
1403static inline uint32_t CORE_CLIP_TRUNCATE_RESERVED_1(uint32_t val)
1404{
1405	return ((val) << CORE_CLIP_TRUNCATE_RESERVED_1__SHIFT) & CORE_CLIP_TRUNCATE_RESERVED_1__MASK;
1406}
1407#define CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__MASK			0x0000001f
1408#define CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__SHIFT			0
1409static inline uint32_t CORE_CLIP_TRUNCATE_CLIP_TRUNCATE(uint32_t val)
1410{
1411	return ((val) << CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__SHIFT) & CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__MASK;
1412}
1413
1414#define REG_DPU_S_STATUS					0x00004000
1415#define DPU_S_STATUS_RESERVED_0__MASK				0xfffc0000
1416#define DPU_S_STATUS_RESERVED_0__SHIFT				18
1417static inline uint32_t DPU_S_STATUS_RESERVED_0(uint32_t val)
1418{
1419	return ((val) << DPU_S_STATUS_RESERVED_0__SHIFT) & DPU_S_STATUS_RESERVED_0__MASK;
1420}
1421#define DPU_S_STATUS_STATUS_1__MASK				0x00030000
1422#define DPU_S_STATUS_STATUS_1__SHIFT				16
1423static inline uint32_t DPU_S_STATUS_STATUS_1(uint32_t val)
1424{
1425	return ((val) << DPU_S_STATUS_STATUS_1__SHIFT) & DPU_S_STATUS_STATUS_1__MASK;
1426}
1427#define DPU_S_STATUS_RESERVED_1__MASK				0x0000fffc
1428#define DPU_S_STATUS_RESERVED_1__SHIFT				2
1429static inline uint32_t DPU_S_STATUS_RESERVED_1(uint32_t val)
1430{
1431	return ((val) << DPU_S_STATUS_RESERVED_1__SHIFT) & DPU_S_STATUS_RESERVED_1__MASK;
1432}
1433#define DPU_S_STATUS_STATUS_0__MASK				0x00000003
1434#define DPU_S_STATUS_STATUS_0__SHIFT				0
1435static inline uint32_t DPU_S_STATUS_STATUS_0(uint32_t val)
1436{
1437	return ((val) << DPU_S_STATUS_STATUS_0__SHIFT) & DPU_S_STATUS_STATUS_0__MASK;
1438}
1439
1440#define REG_DPU_S_POINTER					0x00004004
1441#define DPU_S_POINTER_RESERVED_0__MASK				0xfffe0000
1442#define DPU_S_POINTER_RESERVED_0__SHIFT				17
1443static inline uint32_t DPU_S_POINTER_RESERVED_0(uint32_t val)
1444{
1445	return ((val) << DPU_S_POINTER_RESERVED_0__SHIFT) & DPU_S_POINTER_RESERVED_0__MASK;
1446}
1447#define DPU_S_POINTER_EXECUTER__MASK				0x00010000
1448#define DPU_S_POINTER_EXECUTER__SHIFT				16
1449static inline uint32_t DPU_S_POINTER_EXECUTER(uint32_t val)
1450{
1451	return ((val) << DPU_S_POINTER_EXECUTER__SHIFT) & DPU_S_POINTER_EXECUTER__MASK;
1452}
1453#define DPU_S_POINTER_RESERVED_1__MASK				0x0000ffc0
1454#define DPU_S_POINTER_RESERVED_1__SHIFT				6
1455static inline uint32_t DPU_S_POINTER_RESERVED_1(uint32_t val)
1456{
1457	return ((val) << DPU_S_POINTER_RESERVED_1__SHIFT) & DPU_S_POINTER_RESERVED_1__MASK;
1458}
1459#define DPU_S_POINTER_EXECUTER_PP_CLEAR__MASK			0x00000020
1460#define DPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT			5
1461static inline uint32_t DPU_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
1462{
1463	return ((val) << DPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & DPU_S_POINTER_EXECUTER_PP_CLEAR__MASK;
1464}
1465#define DPU_S_POINTER_POINTER_PP_CLEAR__MASK			0x00000010
1466#define DPU_S_POINTER_POINTER_PP_CLEAR__SHIFT			4
1467static inline uint32_t DPU_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
1468{
1469	return ((val) << DPU_S_POINTER_POINTER_PP_CLEAR__SHIFT) & DPU_S_POINTER_POINTER_PP_CLEAR__MASK;
1470}
1471#define DPU_S_POINTER_POINTER_PP_MODE__MASK			0x00000008
1472#define DPU_S_POINTER_POINTER_PP_MODE__SHIFT			3
1473static inline uint32_t DPU_S_POINTER_POINTER_PP_MODE(uint32_t val)
1474{
1475	return ((val) << DPU_S_POINTER_POINTER_PP_MODE__SHIFT) & DPU_S_POINTER_POINTER_PP_MODE__MASK;
1476}
1477#define DPU_S_POINTER_EXECUTER_PP_EN__MASK			0x00000004
1478#define DPU_S_POINTER_EXECUTER_PP_EN__SHIFT			2
1479static inline uint32_t DPU_S_POINTER_EXECUTER_PP_EN(uint32_t val)
1480{
1481	return ((val) << DPU_S_POINTER_EXECUTER_PP_EN__SHIFT) & DPU_S_POINTER_EXECUTER_PP_EN__MASK;
1482}
1483#define DPU_S_POINTER_POINTER_PP_EN__MASK			0x00000002
1484#define DPU_S_POINTER_POINTER_PP_EN__SHIFT			1
1485static inline uint32_t DPU_S_POINTER_POINTER_PP_EN(uint32_t val)
1486{
1487	return ((val) << DPU_S_POINTER_POINTER_PP_EN__SHIFT) & DPU_S_POINTER_POINTER_PP_EN__MASK;
1488}
1489#define DPU_S_POINTER_POINTER__MASK				0x00000001
1490#define DPU_S_POINTER_POINTER__SHIFT				0
1491static inline uint32_t DPU_S_POINTER_POINTER(uint32_t val)
1492{
1493	return ((val) << DPU_S_POINTER_POINTER__SHIFT) & DPU_S_POINTER_POINTER__MASK;
1494}
1495
1496#define REG_DPU_OPERATION_ENABLE				0x00004008
1497#define DPU_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
1498#define DPU_OPERATION_ENABLE_RESERVED_0__SHIFT			1
1499static inline uint32_t DPU_OPERATION_ENABLE_RESERVED_0(uint32_t val)
1500{
1501	return ((val) << DPU_OPERATION_ENABLE_RESERVED_0__SHIFT) & DPU_OPERATION_ENABLE_RESERVED_0__MASK;
1502}
1503#define DPU_OPERATION_ENABLE_OP_EN__MASK			0x00000001
1504#define DPU_OPERATION_ENABLE_OP_EN__SHIFT			0
1505static inline uint32_t DPU_OPERATION_ENABLE_OP_EN(uint32_t val)
1506{
1507	return ((val) << DPU_OPERATION_ENABLE_OP_EN__SHIFT) & DPU_OPERATION_ENABLE_OP_EN__MASK;
1508}
1509
1510#define REG_DPU_FEATURE_MODE_CFG				0x0000400c
1511#define DPU_FEATURE_MODE_CFG_COMB_USE__MASK			0x80000000
1512#define DPU_FEATURE_MODE_CFG_COMB_USE__SHIFT			31
1513static inline uint32_t DPU_FEATURE_MODE_CFG_COMB_USE(uint32_t val)
1514{
1515	return ((val) << DPU_FEATURE_MODE_CFG_COMB_USE__SHIFT) & DPU_FEATURE_MODE_CFG_COMB_USE__MASK;
1516}
1517#define DPU_FEATURE_MODE_CFG_TP_EN__MASK			0x40000000
1518#define DPU_FEATURE_MODE_CFG_TP_EN__SHIFT			30
1519static inline uint32_t DPU_FEATURE_MODE_CFG_TP_EN(uint32_t val)
1520{
1521	return ((val) << DPU_FEATURE_MODE_CFG_TP_EN__SHIFT) & DPU_FEATURE_MODE_CFG_TP_EN__MASK;
1522}
1523#define DPU_FEATURE_MODE_CFG_RGP_TYPE__MASK			0x3c000000
1524#define DPU_FEATURE_MODE_CFG_RGP_TYPE__SHIFT			26
1525static inline uint32_t DPU_FEATURE_MODE_CFG_RGP_TYPE(uint32_t val)
1526{
1527	return ((val) << DPU_FEATURE_MODE_CFG_RGP_TYPE__SHIFT) & DPU_FEATURE_MODE_CFG_RGP_TYPE__MASK;
1528}
1529#define DPU_FEATURE_MODE_CFG_NONALIGN__MASK			0x02000000
1530#define DPU_FEATURE_MODE_CFG_NONALIGN__SHIFT			25
1531static inline uint32_t DPU_FEATURE_MODE_CFG_NONALIGN(uint32_t val)
1532{
1533	return ((val) << DPU_FEATURE_MODE_CFG_NONALIGN__SHIFT) & DPU_FEATURE_MODE_CFG_NONALIGN__MASK;
1534}
1535#define DPU_FEATURE_MODE_CFG_SURF_LEN__MASK			0x01fffe00
1536#define DPU_FEATURE_MODE_CFG_SURF_LEN__SHIFT			9
1537static inline uint32_t DPU_FEATURE_MODE_CFG_SURF_LEN(uint32_t val)
1538{
1539	return ((val) << DPU_FEATURE_MODE_CFG_SURF_LEN__SHIFT) & DPU_FEATURE_MODE_CFG_SURF_LEN__MASK;
1540}
1541#define DPU_FEATURE_MODE_CFG_BURST_LEN__MASK			0x000001e0
1542#define DPU_FEATURE_MODE_CFG_BURST_LEN__SHIFT			5
1543static inline uint32_t DPU_FEATURE_MODE_CFG_BURST_LEN(uint32_t val)
1544{
1545	return ((val) << DPU_FEATURE_MODE_CFG_BURST_LEN__SHIFT) & DPU_FEATURE_MODE_CFG_BURST_LEN__MASK;
1546}
1547#define DPU_FEATURE_MODE_CFG_CONV_MODE__MASK			0x00000018
1548#define DPU_FEATURE_MODE_CFG_CONV_MODE__SHIFT			3
1549static inline uint32_t DPU_FEATURE_MODE_CFG_CONV_MODE(uint32_t val)
1550{
1551	return ((val) << DPU_FEATURE_MODE_CFG_CONV_MODE__SHIFT) & DPU_FEATURE_MODE_CFG_CONV_MODE__MASK;
1552}
1553#define DPU_FEATURE_MODE_CFG_OUTPUT_MODE__MASK			0x00000006
1554#define DPU_FEATURE_MODE_CFG_OUTPUT_MODE__SHIFT			1
1555static inline uint32_t DPU_FEATURE_MODE_CFG_OUTPUT_MODE(uint32_t val)
1556{
1557	return ((val) << DPU_FEATURE_MODE_CFG_OUTPUT_MODE__SHIFT) & DPU_FEATURE_MODE_CFG_OUTPUT_MODE__MASK;
1558}
1559#define DPU_FEATURE_MODE_CFG_FLYING_MODE__MASK			0x00000001
1560#define DPU_FEATURE_MODE_CFG_FLYING_MODE__SHIFT			0
1561static inline uint32_t DPU_FEATURE_MODE_CFG_FLYING_MODE(uint32_t val)
1562{
1563	return ((val) << DPU_FEATURE_MODE_CFG_FLYING_MODE__SHIFT) & DPU_FEATURE_MODE_CFG_FLYING_MODE__MASK;
1564}
1565
1566#define REG_DPU_DATA_FORMAT					0x00004010
1567#define DPU_DATA_FORMAT_OUT_PRECISION__MASK			0xe0000000
1568#define DPU_DATA_FORMAT_OUT_PRECISION__SHIFT			29
1569static inline uint32_t DPU_DATA_FORMAT_OUT_PRECISION(uint32_t val)
1570{
1571	return ((val) << DPU_DATA_FORMAT_OUT_PRECISION__SHIFT) & DPU_DATA_FORMAT_OUT_PRECISION__MASK;
1572}
1573#define DPU_DATA_FORMAT_IN_PRECISION__MASK			0x1c000000
1574#define DPU_DATA_FORMAT_IN_PRECISION__SHIFT			26
1575static inline uint32_t DPU_DATA_FORMAT_IN_PRECISION(uint32_t val)
1576{
1577	return ((val) << DPU_DATA_FORMAT_IN_PRECISION__SHIFT) & DPU_DATA_FORMAT_IN_PRECISION__MASK;
1578}
1579#define DPU_DATA_FORMAT_EW_TRUNCATE_NEG__MASK			0x03ff0000
1580#define DPU_DATA_FORMAT_EW_TRUNCATE_NEG__SHIFT			16
1581static inline uint32_t DPU_DATA_FORMAT_EW_TRUNCATE_NEG(uint32_t val)
1582{
1583	return ((val) << DPU_DATA_FORMAT_EW_TRUNCATE_NEG__SHIFT) & DPU_DATA_FORMAT_EW_TRUNCATE_NEG__MASK;
1584}
1585#define DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__MASK		0x0000fc00
1586#define DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__SHIFT		10
1587static inline uint32_t DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG(uint32_t val)
1588{
1589	return ((val) << DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__SHIFT) & DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__MASK;
1590}
1591#define DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__MASK		0x000003f0
1592#define DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__SHIFT		4
1593static inline uint32_t DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG(uint32_t val)
1594{
1595	return ((val) << DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__SHIFT) & DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__MASK;
1596}
1597#define DPU_DATA_FORMAT_MC_SURF_OUT__MASK			0x00000008
1598#define DPU_DATA_FORMAT_MC_SURF_OUT__SHIFT			3
1599static inline uint32_t DPU_DATA_FORMAT_MC_SURF_OUT(uint32_t val)
1600{
1601	return ((val) << DPU_DATA_FORMAT_MC_SURF_OUT__SHIFT) & DPU_DATA_FORMAT_MC_SURF_OUT__MASK;
1602}
1603#define DPU_DATA_FORMAT_PROC_PRECISION__MASK			0x00000007
1604#define DPU_DATA_FORMAT_PROC_PRECISION__SHIFT			0
1605static inline uint32_t DPU_DATA_FORMAT_PROC_PRECISION(uint32_t val)
1606{
1607	return ((val) << DPU_DATA_FORMAT_PROC_PRECISION__SHIFT) & DPU_DATA_FORMAT_PROC_PRECISION__MASK;
1608}
1609
1610#define REG_DPU_OFFSET_PEND					0x00004014
1611#define DPU_OFFSET_PEND_RESERVED_0__MASK			0xffff0000
1612#define DPU_OFFSET_PEND_RESERVED_0__SHIFT			16
1613static inline uint32_t DPU_OFFSET_PEND_RESERVED_0(uint32_t val)
1614{
1615	return ((val) << DPU_OFFSET_PEND_RESERVED_0__SHIFT) & DPU_OFFSET_PEND_RESERVED_0__MASK;
1616}
1617#define DPU_OFFSET_PEND_OFFSET_PEND__MASK			0x0000ffff
1618#define DPU_OFFSET_PEND_OFFSET_PEND__SHIFT			0
1619static inline uint32_t DPU_OFFSET_PEND_OFFSET_PEND(uint32_t val)
1620{
1621	return ((val) << DPU_OFFSET_PEND_OFFSET_PEND__SHIFT) & DPU_OFFSET_PEND_OFFSET_PEND__MASK;
1622}
1623
1624#define REG_DPU_DST_BASE_ADDR					0x00004020
1625#define DPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK			0xffffffff
1626#define DPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT			0
1627static inline uint32_t DPU_DST_BASE_ADDR_DST_BASE_ADDR(uint32_t val)
1628{
1629	return ((val) << DPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT) & DPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK;
1630}
1631
1632#define REG_DPU_DST_SURF_STRIDE					0x00004024
1633#define DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK		0xfffffff0
1634#define DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT		4
1635static inline uint32_t DPU_DST_SURF_STRIDE_DST_SURF_STRIDE(uint32_t val)
1636{
1637	return ((val) << DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT) & DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK;
1638}
1639#define DPU_DST_SURF_STRIDE_RESERVED_0__MASK			0x0000000f
1640#define DPU_DST_SURF_STRIDE_RESERVED_0__SHIFT			0
1641static inline uint32_t DPU_DST_SURF_STRIDE_RESERVED_0(uint32_t val)
1642{
1643	return ((val) << DPU_DST_SURF_STRIDE_RESERVED_0__SHIFT) & DPU_DST_SURF_STRIDE_RESERVED_0__MASK;
1644}
1645
1646#define REG_DPU_DATA_CUBE_WIDTH					0x00004030
1647#define DPU_DATA_CUBE_WIDTH_RESERVED_0__MASK			0xffffe000
1648#define DPU_DATA_CUBE_WIDTH_RESERVED_0__SHIFT			13
1649static inline uint32_t DPU_DATA_CUBE_WIDTH_RESERVED_0(uint32_t val)
1650{
1651	return ((val) << DPU_DATA_CUBE_WIDTH_RESERVED_0__SHIFT) & DPU_DATA_CUBE_WIDTH_RESERVED_0__MASK;
1652}
1653#define DPU_DATA_CUBE_WIDTH_WIDTH__MASK				0x00001fff
1654#define DPU_DATA_CUBE_WIDTH_WIDTH__SHIFT			0
1655static inline uint32_t DPU_DATA_CUBE_WIDTH_WIDTH(uint32_t val)
1656{
1657	return ((val) << DPU_DATA_CUBE_WIDTH_WIDTH__SHIFT) & DPU_DATA_CUBE_WIDTH_WIDTH__MASK;
1658}
1659
1660#define REG_DPU_DATA_CUBE_HEIGHT				0x00004034
1661#define DPU_DATA_CUBE_HEIGHT_RESERVED_0__MASK			0xfe000000
1662#define DPU_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT			25
1663static inline uint32_t DPU_DATA_CUBE_HEIGHT_RESERVED_0(uint32_t val)
1664{
1665	return ((val) << DPU_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT) & DPU_DATA_CUBE_HEIGHT_RESERVED_0__MASK;
1666}
1667#define DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__MASK			0x01c00000
1668#define DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__SHIFT			22
1669static inline uint32_t DPU_DATA_CUBE_HEIGHT_MINMAX_CTL(uint32_t val)
1670{
1671	return ((val) << DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__SHIFT) & DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__MASK;
1672}
1673#define DPU_DATA_CUBE_HEIGHT_RESERVED_1__MASK			0x003fe000
1674#define DPU_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT			13
1675static inline uint32_t DPU_DATA_CUBE_HEIGHT_RESERVED_1(uint32_t val)
1676{
1677	return ((val) << DPU_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT) & DPU_DATA_CUBE_HEIGHT_RESERVED_1__MASK;
1678}
1679#define DPU_DATA_CUBE_HEIGHT_HEIGHT__MASK			0x00001fff
1680#define DPU_DATA_CUBE_HEIGHT_HEIGHT__SHIFT			0
1681static inline uint32_t DPU_DATA_CUBE_HEIGHT_HEIGHT(uint32_t val)
1682{
1683	return ((val) << DPU_DATA_CUBE_HEIGHT_HEIGHT__SHIFT) & DPU_DATA_CUBE_HEIGHT_HEIGHT__MASK;
1684}
1685
1686#define REG_DPU_DATA_CUBE_NOTCH_ADDR				0x00004038
1687#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__MASK		0xe0000000
1688#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__SHIFT		29
1689static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0(uint32_t val)
1690{
1691	return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__MASK;
1692}
1693#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__MASK		0x1fff0000
1694#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__SHIFT		16
1695static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1(uint32_t val)
1696{
1697	return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__MASK;
1698}
1699#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__MASK		0x0000e000
1700#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__SHIFT		13
1701static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1(uint32_t val)
1702{
1703	return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__MASK;
1704}
1705#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__MASK		0x00001fff
1706#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__SHIFT		0
1707static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0(uint32_t val)
1708{
1709	return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__MASK;
1710}
1711
1712#define REG_DPU_DATA_CUBE_CHANNEL				0x0000403c
1713#define DPU_DATA_CUBE_CHANNEL_RESERVED_0__MASK			0xe0000000
1714#define DPU_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT			29
1715static inline uint32_t DPU_DATA_CUBE_CHANNEL_RESERVED_0(uint32_t val)
1716{
1717	return ((val) << DPU_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT) & DPU_DATA_CUBE_CHANNEL_RESERVED_0__MASK;
1718}
1719#define DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__MASK		0x1fff0000
1720#define DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__SHIFT		16
1721static inline uint32_t DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL(uint32_t val)
1722{
1723	return ((val) << DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__SHIFT) & DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__MASK;
1724}
1725#define DPU_DATA_CUBE_CHANNEL_RESERVED_1__MASK			0x0000e000
1726#define DPU_DATA_CUBE_CHANNEL_RESERVED_1__SHIFT			13
1727static inline uint32_t DPU_DATA_CUBE_CHANNEL_RESERVED_1(uint32_t val)
1728{
1729	return ((val) << DPU_DATA_CUBE_CHANNEL_RESERVED_1__SHIFT) & DPU_DATA_CUBE_CHANNEL_RESERVED_1__MASK;
1730}
1731#define DPU_DATA_CUBE_CHANNEL_CHANNEL__MASK			0x00001fff
1732#define DPU_DATA_CUBE_CHANNEL_CHANNEL__SHIFT			0
1733static inline uint32_t DPU_DATA_CUBE_CHANNEL_CHANNEL(uint32_t val)
1734{
1735	return ((val) << DPU_DATA_CUBE_CHANNEL_CHANNEL__SHIFT) & DPU_DATA_CUBE_CHANNEL_CHANNEL__MASK;
1736}
1737
1738#define REG_DPU_BS_CFG						0x00004040
1739#define DPU_BS_CFG_RESERVED_0__MASK				0xfff00000
1740#define DPU_BS_CFG_RESERVED_0__SHIFT				20
1741static inline uint32_t DPU_BS_CFG_RESERVED_0(uint32_t val)
1742{
1743	return ((val) << DPU_BS_CFG_RESERVED_0__SHIFT) & DPU_BS_CFG_RESERVED_0__MASK;
1744}
1745#define DPU_BS_CFG_BS_ALU_ALGO__MASK				0x000f0000
1746#define DPU_BS_CFG_BS_ALU_ALGO__SHIFT				16
1747static inline uint32_t DPU_BS_CFG_BS_ALU_ALGO(uint32_t val)
1748{
1749	return ((val) << DPU_BS_CFG_BS_ALU_ALGO__SHIFT) & DPU_BS_CFG_BS_ALU_ALGO__MASK;
1750}
1751#define DPU_BS_CFG_RESERVED_1__MASK				0x0000fe00
1752#define DPU_BS_CFG_RESERVED_1__SHIFT				9
1753static inline uint32_t DPU_BS_CFG_RESERVED_1(uint32_t val)
1754{
1755	return ((val) << DPU_BS_CFG_RESERVED_1__SHIFT) & DPU_BS_CFG_RESERVED_1__MASK;
1756}
1757#define DPU_BS_CFG_BS_ALU_SRC__MASK				0x00000100
1758#define DPU_BS_CFG_BS_ALU_SRC__SHIFT				8
1759static inline uint32_t DPU_BS_CFG_BS_ALU_SRC(uint32_t val)
1760{
1761	return ((val) << DPU_BS_CFG_BS_ALU_SRC__SHIFT) & DPU_BS_CFG_BS_ALU_SRC__MASK;
1762}
1763#define DPU_BS_CFG_BS_RELUX_EN__MASK				0x00000080
1764#define DPU_BS_CFG_BS_RELUX_EN__SHIFT				7
1765static inline uint32_t DPU_BS_CFG_BS_RELUX_EN(uint32_t val)
1766{
1767	return ((val) << DPU_BS_CFG_BS_RELUX_EN__SHIFT) & DPU_BS_CFG_BS_RELUX_EN__MASK;
1768}
1769#define DPU_BS_CFG_BS_RELU_BYPASS__MASK				0x00000040
1770#define DPU_BS_CFG_BS_RELU_BYPASS__SHIFT			6
1771static inline uint32_t DPU_BS_CFG_BS_RELU_BYPASS(uint32_t val)
1772{
1773	return ((val) << DPU_BS_CFG_BS_RELU_BYPASS__SHIFT) & DPU_BS_CFG_BS_RELU_BYPASS__MASK;
1774}
1775#define DPU_BS_CFG_BS_MUL_PRELU__MASK				0x00000020
1776#define DPU_BS_CFG_BS_MUL_PRELU__SHIFT				5
1777static inline uint32_t DPU_BS_CFG_BS_MUL_PRELU(uint32_t val)
1778{
1779	return ((val) << DPU_BS_CFG_BS_MUL_PRELU__SHIFT) & DPU_BS_CFG_BS_MUL_PRELU__MASK;
1780}
1781#define DPU_BS_CFG_BS_MUL_BYPASS__MASK				0x00000010
1782#define DPU_BS_CFG_BS_MUL_BYPASS__SHIFT				4
1783static inline uint32_t DPU_BS_CFG_BS_MUL_BYPASS(uint32_t val)
1784{
1785	return ((val) << DPU_BS_CFG_BS_MUL_BYPASS__SHIFT) & DPU_BS_CFG_BS_MUL_BYPASS__MASK;
1786}
1787#define DPU_BS_CFG_RESERVED_2__MASK				0x0000000c
1788#define DPU_BS_CFG_RESERVED_2__SHIFT				2
1789static inline uint32_t DPU_BS_CFG_RESERVED_2(uint32_t val)
1790{
1791	return ((val) << DPU_BS_CFG_RESERVED_2__SHIFT) & DPU_BS_CFG_RESERVED_2__MASK;
1792}
1793#define DPU_BS_CFG_BS_ALU_BYPASS__MASK				0x00000002
1794#define DPU_BS_CFG_BS_ALU_BYPASS__SHIFT				1
1795static inline uint32_t DPU_BS_CFG_BS_ALU_BYPASS(uint32_t val)
1796{
1797	return ((val) << DPU_BS_CFG_BS_ALU_BYPASS__SHIFT) & DPU_BS_CFG_BS_ALU_BYPASS__MASK;
1798}
1799#define DPU_BS_CFG_BS_BYPASS__MASK				0x00000001
1800#define DPU_BS_CFG_BS_BYPASS__SHIFT				0
1801static inline uint32_t DPU_BS_CFG_BS_BYPASS(uint32_t val)
1802{
1803	return ((val) << DPU_BS_CFG_BS_BYPASS__SHIFT) & DPU_BS_CFG_BS_BYPASS__MASK;
1804}
1805
1806#define REG_DPU_BS_ALU_CFG					0x00004044
1807#define DPU_BS_ALU_CFG_BS_ALU_OPERAND__MASK			0xffffffff
1808#define DPU_BS_ALU_CFG_BS_ALU_OPERAND__SHIFT			0
1809static inline uint32_t DPU_BS_ALU_CFG_BS_ALU_OPERAND(uint32_t val)
1810{
1811	return ((val) << DPU_BS_ALU_CFG_BS_ALU_OPERAND__SHIFT) & DPU_BS_ALU_CFG_BS_ALU_OPERAND__MASK;
1812}
1813
1814#define REG_DPU_BS_MUL_CFG					0x00004048
1815#define DPU_BS_MUL_CFG_BS_MUL_OPERAND__MASK			0xffff0000
1816#define DPU_BS_MUL_CFG_BS_MUL_OPERAND__SHIFT			16
1817static inline uint32_t DPU_BS_MUL_CFG_BS_MUL_OPERAND(uint32_t val)
1818{
1819	return ((val) << DPU_BS_MUL_CFG_BS_MUL_OPERAND__SHIFT) & DPU_BS_MUL_CFG_BS_MUL_OPERAND__MASK;
1820}
1821#define DPU_BS_MUL_CFG_RESERVED_0__MASK				0x0000c000
1822#define DPU_BS_MUL_CFG_RESERVED_0__SHIFT			14
1823static inline uint32_t DPU_BS_MUL_CFG_RESERVED_0(uint32_t val)
1824{
1825	return ((val) << DPU_BS_MUL_CFG_RESERVED_0__SHIFT) & DPU_BS_MUL_CFG_RESERVED_0__MASK;
1826}
1827#define DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__MASK			0x00003f00
1828#define DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__SHIFT		8
1829static inline uint32_t DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE(uint32_t val)
1830{
1831	return ((val) << DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__SHIFT) & DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__MASK;
1832}
1833#define DPU_BS_MUL_CFG_RESERVED_1__MASK				0x000000fc
1834#define DPU_BS_MUL_CFG_RESERVED_1__SHIFT			2
1835static inline uint32_t DPU_BS_MUL_CFG_RESERVED_1(uint32_t val)
1836{
1837	return ((val) << DPU_BS_MUL_CFG_RESERVED_1__SHIFT) & DPU_BS_MUL_CFG_RESERVED_1__MASK;
1838}
1839#define DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__MASK			0x00000002
1840#define DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__SHIFT			1
1841static inline uint32_t DPU_BS_MUL_CFG_BS_TRUNCATE_SRC(uint32_t val)
1842{
1843	return ((val) << DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__SHIFT) & DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__MASK;
1844}
1845#define DPU_BS_MUL_CFG_BS_MUL_SRC__MASK				0x00000001
1846#define DPU_BS_MUL_CFG_BS_MUL_SRC__SHIFT			0
1847static inline uint32_t DPU_BS_MUL_CFG_BS_MUL_SRC(uint32_t val)
1848{
1849	return ((val) << DPU_BS_MUL_CFG_BS_MUL_SRC__SHIFT) & DPU_BS_MUL_CFG_BS_MUL_SRC__MASK;
1850}
1851
1852#define REG_DPU_BS_RELUX_CMP_VALUE				0x0000404c
1853#define DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__MASK		0xffffffff
1854#define DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__SHIFT		0
1855static inline uint32_t DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT(uint32_t val)
1856{
1857	return ((val) << DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__SHIFT) & DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__MASK;
1858}
1859
1860#define REG_DPU_BS_OW_CFG					0x00004050
1861#define DPU_BS_OW_CFG_RGP_CNTER__MASK				0xf0000000
1862#define DPU_BS_OW_CFG_RGP_CNTER__SHIFT				28
1863static inline uint32_t DPU_BS_OW_CFG_RGP_CNTER(uint32_t val)
1864{
1865	return ((val) << DPU_BS_OW_CFG_RGP_CNTER__SHIFT) & DPU_BS_OW_CFG_RGP_CNTER__MASK;
1866}
1867#define DPU_BS_OW_CFG_TP_ORG_EN__MASK				0x08000000
1868#define DPU_BS_OW_CFG_TP_ORG_EN__SHIFT				27
1869static inline uint32_t DPU_BS_OW_CFG_TP_ORG_EN(uint32_t val)
1870{
1871	return ((val) << DPU_BS_OW_CFG_TP_ORG_EN__SHIFT) & DPU_BS_OW_CFG_TP_ORG_EN__MASK;
1872}
1873#define DPU_BS_OW_CFG_RESERVED_0__MASK				0x07fff800
1874#define DPU_BS_OW_CFG_RESERVED_0__SHIFT				11
1875static inline uint32_t DPU_BS_OW_CFG_RESERVED_0(uint32_t val)
1876{
1877	return ((val) << DPU_BS_OW_CFG_RESERVED_0__SHIFT) & DPU_BS_OW_CFG_RESERVED_0__MASK;
1878}
1879#define DPU_BS_OW_CFG_SIZE_E_2__MASK				0x00000700
1880#define DPU_BS_OW_CFG_SIZE_E_2__SHIFT				8
1881static inline uint32_t DPU_BS_OW_CFG_SIZE_E_2(uint32_t val)
1882{
1883	return ((val) << DPU_BS_OW_CFG_SIZE_E_2__SHIFT) & DPU_BS_OW_CFG_SIZE_E_2__MASK;
1884}
1885#define DPU_BS_OW_CFG_SIZE_E_1__MASK				0x000000e0
1886#define DPU_BS_OW_CFG_SIZE_E_1__SHIFT				5
1887static inline uint32_t DPU_BS_OW_CFG_SIZE_E_1(uint32_t val)
1888{
1889	return ((val) << DPU_BS_OW_CFG_SIZE_E_1__SHIFT) & DPU_BS_OW_CFG_SIZE_E_1__MASK;
1890}
1891#define DPU_BS_OW_CFG_SIZE_E_0__MASK				0x0000001c
1892#define DPU_BS_OW_CFG_SIZE_E_0__SHIFT				2
1893static inline uint32_t DPU_BS_OW_CFG_SIZE_E_0(uint32_t val)
1894{
1895	return ((val) << DPU_BS_OW_CFG_SIZE_E_0__SHIFT) & DPU_BS_OW_CFG_SIZE_E_0__MASK;
1896}
1897#define DPU_BS_OW_CFG_OD_BYPASS__MASK				0x00000002
1898#define DPU_BS_OW_CFG_OD_BYPASS__SHIFT				1
1899static inline uint32_t DPU_BS_OW_CFG_OD_BYPASS(uint32_t val)
1900{
1901	return ((val) << DPU_BS_OW_CFG_OD_BYPASS__SHIFT) & DPU_BS_OW_CFG_OD_BYPASS__MASK;
1902}
1903#define DPU_BS_OW_CFG_OW_SRC__MASK				0x00000001
1904#define DPU_BS_OW_CFG_OW_SRC__SHIFT				0
1905static inline uint32_t DPU_BS_OW_CFG_OW_SRC(uint32_t val)
1906{
1907	return ((val) << DPU_BS_OW_CFG_OW_SRC__SHIFT) & DPU_BS_OW_CFG_OW_SRC__MASK;
1908}
1909
1910#define REG_DPU_BS_OW_OP					0x00004054
1911#define DPU_BS_OW_OP_RESERVED_0__MASK				0xffff0000
1912#define DPU_BS_OW_OP_RESERVED_0__SHIFT				16
1913static inline uint32_t DPU_BS_OW_OP_RESERVED_0(uint32_t val)
1914{
1915	return ((val) << DPU_BS_OW_OP_RESERVED_0__SHIFT) & DPU_BS_OW_OP_RESERVED_0__MASK;
1916}
1917#define DPU_BS_OW_OP_OW_OP__MASK				0x0000ffff
1918#define DPU_BS_OW_OP_OW_OP__SHIFT				0
1919static inline uint32_t DPU_BS_OW_OP_OW_OP(uint32_t val)
1920{
1921	return ((val) << DPU_BS_OW_OP_OW_OP__SHIFT) & DPU_BS_OW_OP_OW_OP__MASK;
1922}
1923
1924#define REG_DPU_WDMA_SIZE_0					0x00004058
1925#define DPU_WDMA_SIZE_0_RESERVED_0__MASK			0xf0000000
1926#define DPU_WDMA_SIZE_0_RESERVED_0__SHIFT			28
1927static inline uint32_t DPU_WDMA_SIZE_0_RESERVED_0(uint32_t val)
1928{
1929	return ((val) << DPU_WDMA_SIZE_0_RESERVED_0__SHIFT) & DPU_WDMA_SIZE_0_RESERVED_0__MASK;
1930}
1931#define DPU_WDMA_SIZE_0_TP_PRECISION__MASK			0x08000000
1932#define DPU_WDMA_SIZE_0_TP_PRECISION__SHIFT			27
1933static inline uint32_t DPU_WDMA_SIZE_0_TP_PRECISION(uint32_t val)
1934{
1935	return ((val) << DPU_WDMA_SIZE_0_TP_PRECISION__SHIFT) & DPU_WDMA_SIZE_0_TP_PRECISION__MASK;
1936}
1937#define DPU_WDMA_SIZE_0_SIZE_C_WDMA__MASK			0x07ff0000
1938#define DPU_WDMA_SIZE_0_SIZE_C_WDMA__SHIFT			16
1939static inline uint32_t DPU_WDMA_SIZE_0_SIZE_C_WDMA(uint32_t val)
1940{
1941	return ((val) << DPU_WDMA_SIZE_0_SIZE_C_WDMA__SHIFT) & DPU_WDMA_SIZE_0_SIZE_C_WDMA__MASK;
1942}
1943#define DPU_WDMA_SIZE_0_RESERVED_1__MASK			0x0000e000
1944#define DPU_WDMA_SIZE_0_RESERVED_1__SHIFT			13
1945static inline uint32_t DPU_WDMA_SIZE_0_RESERVED_1(uint32_t val)
1946{
1947	return ((val) << DPU_WDMA_SIZE_0_RESERVED_1__SHIFT) & DPU_WDMA_SIZE_0_RESERVED_1__MASK;
1948}
1949#define DPU_WDMA_SIZE_0_CHANNEL_WDMA__MASK			0x00001fff
1950#define DPU_WDMA_SIZE_0_CHANNEL_WDMA__SHIFT			0
1951static inline uint32_t DPU_WDMA_SIZE_0_CHANNEL_WDMA(uint32_t val)
1952{
1953	return ((val) << DPU_WDMA_SIZE_0_CHANNEL_WDMA__SHIFT) & DPU_WDMA_SIZE_0_CHANNEL_WDMA__MASK;
1954}
1955
1956#define REG_DPU_WDMA_SIZE_1					0x0000405c
1957#define DPU_WDMA_SIZE_1_RESERVED_0__MASK			0xe0000000
1958#define DPU_WDMA_SIZE_1_RESERVED_0__SHIFT			29
1959static inline uint32_t DPU_WDMA_SIZE_1_RESERVED_0(uint32_t val)
1960{
1961	return ((val) << DPU_WDMA_SIZE_1_RESERVED_0__SHIFT) & DPU_WDMA_SIZE_1_RESERVED_0__MASK;
1962}
1963#define DPU_WDMA_SIZE_1_HEIGHT_WDMA__MASK			0x1fff0000
1964#define DPU_WDMA_SIZE_1_HEIGHT_WDMA__SHIFT			16
1965static inline uint32_t DPU_WDMA_SIZE_1_HEIGHT_WDMA(uint32_t val)
1966{
1967	return ((val) << DPU_WDMA_SIZE_1_HEIGHT_WDMA__SHIFT) & DPU_WDMA_SIZE_1_HEIGHT_WDMA__MASK;
1968}
1969#define DPU_WDMA_SIZE_1_RESERVED_1__MASK			0x0000e000
1970#define DPU_WDMA_SIZE_1_RESERVED_1__SHIFT			13
1971static inline uint32_t DPU_WDMA_SIZE_1_RESERVED_1(uint32_t val)
1972{
1973	return ((val) << DPU_WDMA_SIZE_1_RESERVED_1__SHIFT) & DPU_WDMA_SIZE_1_RESERVED_1__MASK;
1974}
1975#define DPU_WDMA_SIZE_1_WIDTH_WDMA__MASK			0x00001fff
1976#define DPU_WDMA_SIZE_1_WIDTH_WDMA__SHIFT			0
1977static inline uint32_t DPU_WDMA_SIZE_1_WIDTH_WDMA(uint32_t val)
1978{
1979	return ((val) << DPU_WDMA_SIZE_1_WIDTH_WDMA__SHIFT) & DPU_WDMA_SIZE_1_WIDTH_WDMA__MASK;
1980}
1981
1982#define REG_DPU_BN_CFG						0x00004060
1983#define DPU_BN_CFG_RESERVED_0__MASK				0xfff00000
1984#define DPU_BN_CFG_RESERVED_0__SHIFT				20
1985static inline uint32_t DPU_BN_CFG_RESERVED_0(uint32_t val)
1986{
1987	return ((val) << DPU_BN_CFG_RESERVED_0__SHIFT) & DPU_BN_CFG_RESERVED_0__MASK;
1988}
1989#define DPU_BN_CFG_BN_ALU_ALGO__MASK				0x000f0000
1990#define DPU_BN_CFG_BN_ALU_ALGO__SHIFT				16
1991static inline uint32_t DPU_BN_CFG_BN_ALU_ALGO(uint32_t val)
1992{
1993	return ((val) << DPU_BN_CFG_BN_ALU_ALGO__SHIFT) & DPU_BN_CFG_BN_ALU_ALGO__MASK;
1994}
1995#define DPU_BN_CFG_RESERVED_1__MASK				0x0000fe00
1996#define DPU_BN_CFG_RESERVED_1__SHIFT				9
1997static inline uint32_t DPU_BN_CFG_RESERVED_1(uint32_t val)
1998{
1999	return ((val) << DPU_BN_CFG_RESERVED_1__SHIFT) & DPU_BN_CFG_RESERVED_1__MASK;
2000}
2001#define DPU_BN_CFG_BN_ALU_SRC__MASK				0x00000100
2002#define DPU_BN_CFG_BN_ALU_SRC__SHIFT				8
2003static inline uint32_t DPU_BN_CFG_BN_ALU_SRC(uint32_t val)
2004{
2005	return ((val) << DPU_BN_CFG_BN_ALU_SRC__SHIFT) & DPU_BN_CFG_BN_ALU_SRC__MASK;
2006}
2007#define DPU_BN_CFG_BN_RELUX_EN__MASK				0x00000080
2008#define DPU_BN_CFG_BN_RELUX_EN__SHIFT				7
2009static inline uint32_t DPU_BN_CFG_BN_RELUX_EN(uint32_t val)
2010{
2011	return ((val) << DPU_BN_CFG_BN_RELUX_EN__SHIFT) & DPU_BN_CFG_BN_RELUX_EN__MASK;
2012}
2013#define DPU_BN_CFG_BN_RELU_BYPASS__MASK				0x00000040
2014#define DPU_BN_CFG_BN_RELU_BYPASS__SHIFT			6
2015static inline uint32_t DPU_BN_CFG_BN_RELU_BYPASS(uint32_t val)
2016{
2017	return ((val) << DPU_BN_CFG_BN_RELU_BYPASS__SHIFT) & DPU_BN_CFG_BN_RELU_BYPASS__MASK;
2018}
2019#define DPU_BN_CFG_BN_MUL_PRELU__MASK				0x00000020
2020#define DPU_BN_CFG_BN_MUL_PRELU__SHIFT				5
2021static inline uint32_t DPU_BN_CFG_BN_MUL_PRELU(uint32_t val)
2022{
2023	return ((val) << DPU_BN_CFG_BN_MUL_PRELU__SHIFT) & DPU_BN_CFG_BN_MUL_PRELU__MASK;
2024}
2025#define DPU_BN_CFG_BN_MUL_BYPASS__MASK				0x00000010
2026#define DPU_BN_CFG_BN_MUL_BYPASS__SHIFT				4
2027static inline uint32_t DPU_BN_CFG_BN_MUL_BYPASS(uint32_t val)
2028{
2029	return ((val) << DPU_BN_CFG_BN_MUL_BYPASS__SHIFT) & DPU_BN_CFG_BN_MUL_BYPASS__MASK;
2030}
2031#define DPU_BN_CFG_RESERVED_2__MASK				0x0000000c
2032#define DPU_BN_CFG_RESERVED_2__SHIFT				2
2033static inline uint32_t DPU_BN_CFG_RESERVED_2(uint32_t val)
2034{
2035	return ((val) << DPU_BN_CFG_RESERVED_2__SHIFT) & DPU_BN_CFG_RESERVED_2__MASK;
2036}
2037#define DPU_BN_CFG_BN_ALU_BYPASS__MASK				0x00000002
2038#define DPU_BN_CFG_BN_ALU_BYPASS__SHIFT				1
2039static inline uint32_t DPU_BN_CFG_BN_ALU_BYPASS(uint32_t val)
2040{
2041	return ((val) << DPU_BN_CFG_BN_ALU_BYPASS__SHIFT) & DPU_BN_CFG_BN_ALU_BYPASS__MASK;
2042}
2043#define DPU_BN_CFG_BN_BYPASS__MASK				0x00000001
2044#define DPU_BN_CFG_BN_BYPASS__SHIFT				0
2045static inline uint32_t DPU_BN_CFG_BN_BYPASS(uint32_t val)
2046{
2047	return ((val) << DPU_BN_CFG_BN_BYPASS__SHIFT) & DPU_BN_CFG_BN_BYPASS__MASK;
2048}
2049
2050#define REG_DPU_BN_ALU_CFG					0x00004064
2051#define DPU_BN_ALU_CFG_BN_ALU_OPERAND__MASK			0xffffffff
2052#define DPU_BN_ALU_CFG_BN_ALU_OPERAND__SHIFT			0
2053static inline uint32_t DPU_BN_ALU_CFG_BN_ALU_OPERAND(uint32_t val)
2054{
2055	return ((val) << DPU_BN_ALU_CFG_BN_ALU_OPERAND__SHIFT) & DPU_BN_ALU_CFG_BN_ALU_OPERAND__MASK;
2056}
2057
2058#define REG_DPU_BN_MUL_CFG					0x00004068
2059#define DPU_BN_MUL_CFG_BN_MUL_OPERAND__MASK			0xffff0000
2060#define DPU_BN_MUL_CFG_BN_MUL_OPERAND__SHIFT			16
2061static inline uint32_t DPU_BN_MUL_CFG_BN_MUL_OPERAND(uint32_t val)
2062{
2063	return ((val) << DPU_BN_MUL_CFG_BN_MUL_OPERAND__SHIFT) & DPU_BN_MUL_CFG_BN_MUL_OPERAND__MASK;
2064}
2065#define DPU_BN_MUL_CFG_RESERVED_0__MASK				0x0000c000
2066#define DPU_BN_MUL_CFG_RESERVED_0__SHIFT			14
2067static inline uint32_t DPU_BN_MUL_CFG_RESERVED_0(uint32_t val)
2068{
2069	return ((val) << DPU_BN_MUL_CFG_RESERVED_0__SHIFT) & DPU_BN_MUL_CFG_RESERVED_0__MASK;
2070}
2071#define DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__MASK			0x00003f00
2072#define DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__SHIFT		8
2073static inline uint32_t DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE(uint32_t val)
2074{
2075	return ((val) << DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__SHIFT) & DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__MASK;
2076}
2077#define DPU_BN_MUL_CFG_RESERVED_1__MASK				0x000000fc
2078#define DPU_BN_MUL_CFG_RESERVED_1__SHIFT			2
2079static inline uint32_t DPU_BN_MUL_CFG_RESERVED_1(uint32_t val)
2080{
2081	return ((val) << DPU_BN_MUL_CFG_RESERVED_1__SHIFT) & DPU_BN_MUL_CFG_RESERVED_1__MASK;
2082}
2083#define DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__MASK			0x00000002
2084#define DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__SHIFT			1
2085static inline uint32_t DPU_BN_MUL_CFG_BN_TRUNCATE_SRC(uint32_t val)
2086{
2087	return ((val) << DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__SHIFT) & DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__MASK;
2088}
2089#define DPU_BN_MUL_CFG_BN_MUL_SRC__MASK				0x00000001
2090#define DPU_BN_MUL_CFG_BN_MUL_SRC__SHIFT			0
2091static inline uint32_t DPU_BN_MUL_CFG_BN_MUL_SRC(uint32_t val)
2092{
2093	return ((val) << DPU_BN_MUL_CFG_BN_MUL_SRC__SHIFT) & DPU_BN_MUL_CFG_BN_MUL_SRC__MASK;
2094}
2095
2096#define REG_DPU_BN_RELUX_CMP_VALUE				0x0000406c
2097#define DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__MASK		0xffffffff
2098#define DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__SHIFT		0
2099static inline uint32_t DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT(uint32_t val)
2100{
2101	return ((val) << DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__SHIFT) & DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__MASK;
2102}
2103
2104#define REG_DPU_EW_CFG						0x00004070
2105#define DPU_EW_CFG_EW_CVT_TYPE__MASK				0x80000000
2106#define DPU_EW_CFG_EW_CVT_TYPE__SHIFT				31
2107static inline uint32_t DPU_EW_CFG_EW_CVT_TYPE(uint32_t val)
2108{
2109	return ((val) << DPU_EW_CFG_EW_CVT_TYPE__SHIFT) & DPU_EW_CFG_EW_CVT_TYPE__MASK;
2110}
2111#define DPU_EW_CFG_EW_CVT_ROUND__MASK				0x40000000
2112#define DPU_EW_CFG_EW_CVT_ROUND__SHIFT				30
2113static inline uint32_t DPU_EW_CFG_EW_CVT_ROUND(uint32_t val)
2114{
2115	return ((val) << DPU_EW_CFG_EW_CVT_ROUND__SHIFT) & DPU_EW_CFG_EW_CVT_ROUND__MASK;
2116}
2117#define DPU_EW_CFG_EW_DATA_MODE__MASK				0x30000000
2118#define DPU_EW_CFG_EW_DATA_MODE__SHIFT				28
2119static inline uint32_t DPU_EW_CFG_EW_DATA_MODE(uint32_t val)
2120{
2121	return ((val) << DPU_EW_CFG_EW_DATA_MODE__SHIFT) & DPU_EW_CFG_EW_DATA_MODE__MASK;
2122}
2123#define DPU_EW_CFG_RESERVED_0__MASK				0x0f000000
2124#define DPU_EW_CFG_RESERVED_0__SHIFT				24
2125static inline uint32_t DPU_EW_CFG_RESERVED_0(uint32_t val)
2126{
2127	return ((val) << DPU_EW_CFG_RESERVED_0__SHIFT) & DPU_EW_CFG_RESERVED_0__MASK;
2128}
2129#define DPU_EW_CFG_EDATA_SIZE__MASK				0x00c00000
2130#define DPU_EW_CFG_EDATA_SIZE__SHIFT				22
2131static inline uint32_t DPU_EW_CFG_EDATA_SIZE(uint32_t val)
2132{
2133	return ((val) << DPU_EW_CFG_EDATA_SIZE__SHIFT) & DPU_EW_CFG_EDATA_SIZE__MASK;
2134}
2135#define DPU_EW_CFG_EW_EQUAL_EN__MASK				0x00200000
2136#define DPU_EW_CFG_EW_EQUAL_EN__SHIFT				21
2137static inline uint32_t DPU_EW_CFG_EW_EQUAL_EN(uint32_t val)
2138{
2139	return ((val) << DPU_EW_CFG_EW_EQUAL_EN__SHIFT) & DPU_EW_CFG_EW_EQUAL_EN__MASK;
2140}
2141#define DPU_EW_CFG_EW_BINARY_EN__MASK				0x00100000
2142#define DPU_EW_CFG_EW_BINARY_EN__SHIFT				20
2143static inline uint32_t DPU_EW_CFG_EW_BINARY_EN(uint32_t val)
2144{
2145	return ((val) << DPU_EW_CFG_EW_BINARY_EN__SHIFT) & DPU_EW_CFG_EW_BINARY_EN__MASK;
2146}
2147#define DPU_EW_CFG_EW_ALU_ALGO__MASK				0x000f0000
2148#define DPU_EW_CFG_EW_ALU_ALGO__SHIFT				16
2149static inline uint32_t DPU_EW_CFG_EW_ALU_ALGO(uint32_t val)
2150{
2151	return ((val) << DPU_EW_CFG_EW_ALU_ALGO__SHIFT) & DPU_EW_CFG_EW_ALU_ALGO__MASK;
2152}
2153#define DPU_EW_CFG_RESERVED_1__MASK				0x0000f800
2154#define DPU_EW_CFG_RESERVED_1__SHIFT				11
2155static inline uint32_t DPU_EW_CFG_RESERVED_1(uint32_t val)
2156{
2157	return ((val) << DPU_EW_CFG_RESERVED_1__SHIFT) & DPU_EW_CFG_RESERVED_1__MASK;
2158}
2159#define DPU_EW_CFG_EW_RELUX_EN__MASK				0x00000400
2160#define DPU_EW_CFG_EW_RELUX_EN__SHIFT				10
2161static inline uint32_t DPU_EW_CFG_EW_RELUX_EN(uint32_t val)
2162{
2163	return ((val) << DPU_EW_CFG_EW_RELUX_EN__SHIFT) & DPU_EW_CFG_EW_RELUX_EN__MASK;
2164}
2165#define DPU_EW_CFG_EW_RELU_BYPASS__MASK				0x00000200
2166#define DPU_EW_CFG_EW_RELU_BYPASS__SHIFT			9
2167static inline uint32_t DPU_EW_CFG_EW_RELU_BYPASS(uint32_t val)
2168{
2169	return ((val) << DPU_EW_CFG_EW_RELU_BYPASS__SHIFT) & DPU_EW_CFG_EW_RELU_BYPASS__MASK;
2170}
2171#define DPU_EW_CFG_EW_OP_CVT_BYPASS__MASK			0x00000100
2172#define DPU_EW_CFG_EW_OP_CVT_BYPASS__SHIFT			8
2173static inline uint32_t DPU_EW_CFG_EW_OP_CVT_BYPASS(uint32_t val)
2174{
2175	return ((val) << DPU_EW_CFG_EW_OP_CVT_BYPASS__SHIFT) & DPU_EW_CFG_EW_OP_CVT_BYPASS__MASK;
2176}
2177#define DPU_EW_CFG_EW_LUT_BYPASS__MASK				0x00000080
2178#define DPU_EW_CFG_EW_LUT_BYPASS__SHIFT				7
2179static inline uint32_t DPU_EW_CFG_EW_LUT_BYPASS(uint32_t val)
2180{
2181	return ((val) << DPU_EW_CFG_EW_LUT_BYPASS__SHIFT) & DPU_EW_CFG_EW_LUT_BYPASS__MASK;
2182}
2183#define DPU_EW_CFG_EW_OP_SRC__MASK				0x00000040
2184#define DPU_EW_CFG_EW_OP_SRC__SHIFT				6
2185static inline uint32_t DPU_EW_CFG_EW_OP_SRC(uint32_t val)
2186{
2187	return ((val) << DPU_EW_CFG_EW_OP_SRC__SHIFT) & DPU_EW_CFG_EW_OP_SRC__MASK;
2188}
2189#define DPU_EW_CFG_EW_MUL_PRELU__MASK				0x00000020
2190#define DPU_EW_CFG_EW_MUL_PRELU__SHIFT				5
2191static inline uint32_t DPU_EW_CFG_EW_MUL_PRELU(uint32_t val)
2192{
2193	return ((val) << DPU_EW_CFG_EW_MUL_PRELU__SHIFT) & DPU_EW_CFG_EW_MUL_PRELU__MASK;
2194}
2195#define DPU_EW_CFG_RESERVED_2__MASK				0x00000018
2196#define DPU_EW_CFG_RESERVED_2__SHIFT				3
2197static inline uint32_t DPU_EW_CFG_RESERVED_2(uint32_t val)
2198{
2199	return ((val) << DPU_EW_CFG_RESERVED_2__SHIFT) & DPU_EW_CFG_RESERVED_2__MASK;
2200}
2201#define DPU_EW_CFG_EW_OP_TYPE__MASK				0x00000004
2202#define DPU_EW_CFG_EW_OP_TYPE__SHIFT				2
2203static inline uint32_t DPU_EW_CFG_EW_OP_TYPE(uint32_t val)
2204{
2205	return ((val) << DPU_EW_CFG_EW_OP_TYPE__SHIFT) & DPU_EW_CFG_EW_OP_TYPE__MASK;
2206}
2207#define DPU_EW_CFG_EW_OP_BYPASS__MASK				0x00000002
2208#define DPU_EW_CFG_EW_OP_BYPASS__SHIFT				1
2209static inline uint32_t DPU_EW_CFG_EW_OP_BYPASS(uint32_t val)
2210{
2211	return ((val) << DPU_EW_CFG_EW_OP_BYPASS__SHIFT) & DPU_EW_CFG_EW_OP_BYPASS__MASK;
2212}
2213#define DPU_EW_CFG_EW_BYPASS__MASK				0x00000001
2214#define DPU_EW_CFG_EW_BYPASS__SHIFT				0
2215static inline uint32_t DPU_EW_CFG_EW_BYPASS(uint32_t val)
2216{
2217	return ((val) << DPU_EW_CFG_EW_BYPASS__SHIFT) & DPU_EW_CFG_EW_BYPASS__MASK;
2218}
2219
2220#define REG_DPU_EW_CVT_OFFSET_VALUE				0x00004074
2221#define DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__MASK		0xffffffff
2222#define DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__SHIFT		0
2223static inline uint32_t DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET(uint32_t val)
2224{
2225	return ((val) << DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__SHIFT) & DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__MASK;
2226}
2227
2228#define REG_DPU_EW_CVT_SCALE_VALUE				0x00004078
2229#define DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__MASK		0xffc00000
2230#define DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__SHIFT		22
2231static inline uint32_t DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE(uint32_t val)
2232{
2233	return ((val) << DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__SHIFT) & DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__MASK;
2234}
2235#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__MASK		0x003f0000
2236#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__SHIFT		16
2237static inline uint32_t DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT(uint32_t val)
2238{
2239	return ((val) << DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__SHIFT) & DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__MASK;
2240}
2241#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__MASK		0x0000ffff
2242#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__SHIFT		0
2243static inline uint32_t DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE(uint32_t val)
2244{
2245	return ((val) << DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__SHIFT) & DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__MASK;
2246}
2247
2248#define REG_DPU_EW_RELUX_CMP_VALUE				0x0000407c
2249#define DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__MASK		0xffffffff
2250#define DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__SHIFT		0
2251static inline uint32_t DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT(uint32_t val)
2252{
2253	return ((val) << DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__SHIFT) & DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__MASK;
2254}
2255
2256#define REG_DPU_OUT_CVT_OFFSET					0x00004080
2257#define DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__MASK			0xffffffff
2258#define DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__SHIFT		0
2259static inline uint32_t DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET(uint32_t val)
2260{
2261	return ((val) << DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__SHIFT) & DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__MASK;
2262}
2263
2264#define REG_DPU_OUT_CVT_SCALE					0x00004084
2265#define DPU_OUT_CVT_SCALE_RESERVED_0__MASK			0xfffe0000
2266#define DPU_OUT_CVT_SCALE_RESERVED_0__SHIFT			17
2267static inline uint32_t DPU_OUT_CVT_SCALE_RESERVED_0(uint32_t val)
2268{
2269	return ((val) << DPU_OUT_CVT_SCALE_RESERVED_0__SHIFT) & DPU_OUT_CVT_SCALE_RESERVED_0__MASK;
2270}
2271#define DPU_OUT_CVT_SCALE_FP32TOFP16_EN__MASK			0x00010000
2272#define DPU_OUT_CVT_SCALE_FP32TOFP16_EN__SHIFT			16
2273static inline uint32_t DPU_OUT_CVT_SCALE_FP32TOFP16_EN(uint32_t val)
2274{
2275	return ((val) << DPU_OUT_CVT_SCALE_FP32TOFP16_EN__SHIFT) & DPU_OUT_CVT_SCALE_FP32TOFP16_EN__MASK;
2276}
2277#define DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__MASK			0x0000ffff
2278#define DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__SHIFT			0
2279static inline uint32_t DPU_OUT_CVT_SCALE_OUT_CVT_SCALE(uint32_t val)
2280{
2281	return ((val) << DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__SHIFT) & DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__MASK;
2282}
2283
2284#define REG_DPU_OUT_CVT_SHIFT					0x00004088
2285#define DPU_OUT_CVT_SHIFT_CVT_TYPE__MASK			0x80000000
2286#define DPU_OUT_CVT_SHIFT_CVT_TYPE__SHIFT			31
2287static inline uint32_t DPU_OUT_CVT_SHIFT_CVT_TYPE(uint32_t val)
2288{
2289	return ((val) << DPU_OUT_CVT_SHIFT_CVT_TYPE__SHIFT) & DPU_OUT_CVT_SHIFT_CVT_TYPE__MASK;
2290}
2291#define DPU_OUT_CVT_SHIFT_CVT_ROUND__MASK			0x40000000
2292#define DPU_OUT_CVT_SHIFT_CVT_ROUND__SHIFT			30
2293static inline uint32_t DPU_OUT_CVT_SHIFT_CVT_ROUND(uint32_t val)
2294{
2295	return ((val) << DPU_OUT_CVT_SHIFT_CVT_ROUND__SHIFT) & DPU_OUT_CVT_SHIFT_CVT_ROUND__MASK;
2296}
2297#define DPU_OUT_CVT_SHIFT_RESERVED_0__MASK			0x3ff00000
2298#define DPU_OUT_CVT_SHIFT_RESERVED_0__SHIFT			20
2299static inline uint32_t DPU_OUT_CVT_SHIFT_RESERVED_0(uint32_t val)
2300{
2301	return ((val) << DPU_OUT_CVT_SHIFT_RESERVED_0__SHIFT) & DPU_OUT_CVT_SHIFT_RESERVED_0__MASK;
2302}
2303#define DPU_OUT_CVT_SHIFT_MINUS_EXP__MASK			0x000ff000
2304#define DPU_OUT_CVT_SHIFT_MINUS_EXP__SHIFT			12
2305static inline uint32_t DPU_OUT_CVT_SHIFT_MINUS_EXP(uint32_t val)
2306{
2307	return ((val) << DPU_OUT_CVT_SHIFT_MINUS_EXP__SHIFT) & DPU_OUT_CVT_SHIFT_MINUS_EXP__MASK;
2308}
2309#define DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__MASK			0x00000fff
2310#define DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__SHIFT			0
2311static inline uint32_t DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT(uint32_t val)
2312{
2313	return ((val) << DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__SHIFT) & DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__MASK;
2314}
2315
2316#define REG_DPU_EW_OP_VALUE_0					0x00004090
2317#define DPU_EW_OP_VALUE_0_EW_OPERAND_0__MASK			0xffffffff
2318#define DPU_EW_OP_VALUE_0_EW_OPERAND_0__SHIFT			0
2319static inline uint32_t DPU_EW_OP_VALUE_0_EW_OPERAND_0(uint32_t val)
2320{
2321	return ((val) << DPU_EW_OP_VALUE_0_EW_OPERAND_0__SHIFT) & DPU_EW_OP_VALUE_0_EW_OPERAND_0__MASK;
2322}
2323
2324#define REG_DPU_EW_OP_VALUE_1					0x00004094
2325#define DPU_EW_OP_VALUE_1_EW_OPERAND_1__MASK			0xffffffff
2326#define DPU_EW_OP_VALUE_1_EW_OPERAND_1__SHIFT			0
2327static inline uint32_t DPU_EW_OP_VALUE_1_EW_OPERAND_1(uint32_t val)
2328{
2329	return ((val) << DPU_EW_OP_VALUE_1_EW_OPERAND_1__SHIFT) & DPU_EW_OP_VALUE_1_EW_OPERAND_1__MASK;
2330}
2331
2332#define REG_DPU_EW_OP_VALUE_2					0x00004098
2333#define DPU_EW_OP_VALUE_2_EW_OPERAND_2__MASK			0xffffffff
2334#define DPU_EW_OP_VALUE_2_EW_OPERAND_2__SHIFT			0
2335static inline uint32_t DPU_EW_OP_VALUE_2_EW_OPERAND_2(uint32_t val)
2336{
2337	return ((val) << DPU_EW_OP_VALUE_2_EW_OPERAND_2__SHIFT) & DPU_EW_OP_VALUE_2_EW_OPERAND_2__MASK;
2338}
2339
2340#define REG_DPU_EW_OP_VALUE_3					0x0000409c
2341#define DPU_EW_OP_VALUE_3_EW_OPERAND_3__MASK			0xffffffff
2342#define DPU_EW_OP_VALUE_3_EW_OPERAND_3__SHIFT			0
2343static inline uint32_t DPU_EW_OP_VALUE_3_EW_OPERAND_3(uint32_t val)
2344{
2345	return ((val) << DPU_EW_OP_VALUE_3_EW_OPERAND_3__SHIFT) & DPU_EW_OP_VALUE_3_EW_OPERAND_3__MASK;
2346}
2347
2348#define REG_DPU_EW_OP_VALUE_4					0x000040a0
2349#define DPU_EW_OP_VALUE_4_EW_OPERAND_4__MASK			0xffffffff
2350#define DPU_EW_OP_VALUE_4_EW_OPERAND_4__SHIFT			0
2351static inline uint32_t DPU_EW_OP_VALUE_4_EW_OPERAND_4(uint32_t val)
2352{
2353	return ((val) << DPU_EW_OP_VALUE_4_EW_OPERAND_4__SHIFT) & DPU_EW_OP_VALUE_4_EW_OPERAND_4__MASK;
2354}
2355
2356#define REG_DPU_EW_OP_VALUE_5					0x000040a4
2357#define DPU_EW_OP_VALUE_5_EW_OPERAND_5__MASK			0xffffffff
2358#define DPU_EW_OP_VALUE_5_EW_OPERAND_5__SHIFT			0
2359static inline uint32_t DPU_EW_OP_VALUE_5_EW_OPERAND_5(uint32_t val)
2360{
2361	return ((val) << DPU_EW_OP_VALUE_5_EW_OPERAND_5__SHIFT) & DPU_EW_OP_VALUE_5_EW_OPERAND_5__MASK;
2362}
2363
2364#define REG_DPU_EW_OP_VALUE_6					0x000040a8
2365#define DPU_EW_OP_VALUE_6_EW_OPERAND_6__MASK			0xffffffff
2366#define DPU_EW_OP_VALUE_6_EW_OPERAND_6__SHIFT			0
2367static inline uint32_t DPU_EW_OP_VALUE_6_EW_OPERAND_6(uint32_t val)
2368{
2369	return ((val) << DPU_EW_OP_VALUE_6_EW_OPERAND_6__SHIFT) & DPU_EW_OP_VALUE_6_EW_OPERAND_6__MASK;
2370}
2371
2372#define REG_DPU_EW_OP_VALUE_7					0x000040ac
2373#define DPU_EW_OP_VALUE_7_EW_OPERAND_7__MASK			0xffffffff
2374#define DPU_EW_OP_VALUE_7_EW_OPERAND_7__SHIFT			0
2375static inline uint32_t DPU_EW_OP_VALUE_7_EW_OPERAND_7(uint32_t val)
2376{
2377	return ((val) << DPU_EW_OP_VALUE_7_EW_OPERAND_7__SHIFT) & DPU_EW_OP_VALUE_7_EW_OPERAND_7__MASK;
2378}
2379
2380#define REG_DPU_SURFACE_ADD					0x000040c0
2381#define DPU_SURFACE_ADD_SURF_ADD__MASK				0xfffffff0
2382#define DPU_SURFACE_ADD_SURF_ADD__SHIFT				4
2383static inline uint32_t DPU_SURFACE_ADD_SURF_ADD(uint32_t val)
2384{
2385	return ((val) << DPU_SURFACE_ADD_SURF_ADD__SHIFT) & DPU_SURFACE_ADD_SURF_ADD__MASK;
2386}
2387#define DPU_SURFACE_ADD_RESERVED_0__MASK			0x0000000f
2388#define DPU_SURFACE_ADD_RESERVED_0__SHIFT			0
2389static inline uint32_t DPU_SURFACE_ADD_RESERVED_0(uint32_t val)
2390{
2391	return ((val) << DPU_SURFACE_ADD_RESERVED_0__SHIFT) & DPU_SURFACE_ADD_RESERVED_0__MASK;
2392}
2393
2394#define REG_DPU_LUT_ACCESS_CFG					0x00004100
2395#define DPU_LUT_ACCESS_CFG_RESERVED_0__MASK			0xfffc0000
2396#define DPU_LUT_ACCESS_CFG_RESERVED_0__SHIFT			18
2397static inline uint32_t DPU_LUT_ACCESS_CFG_RESERVED_0(uint32_t val)
2398{
2399	return ((val) << DPU_LUT_ACCESS_CFG_RESERVED_0__SHIFT) & DPU_LUT_ACCESS_CFG_RESERVED_0__MASK;
2400}
2401#define DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__MASK		0x00020000
2402#define DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__SHIFT		17
2403static inline uint32_t DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE(uint32_t val)
2404{
2405	return ((val) << DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__SHIFT) & DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__MASK;
2406}
2407#define DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__MASK			0x00010000
2408#define DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__SHIFT			16
2409static inline uint32_t DPU_LUT_ACCESS_CFG_LUT_TABLE_ID(uint32_t val)
2410{
2411	return ((val) << DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__SHIFT) & DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__MASK;
2412}
2413#define DPU_LUT_ACCESS_CFG_RESERVED_1__MASK			0x0000fc00
2414#define DPU_LUT_ACCESS_CFG_RESERVED_1__SHIFT			10
2415static inline uint32_t DPU_LUT_ACCESS_CFG_RESERVED_1(uint32_t val)
2416{
2417	return ((val) << DPU_LUT_ACCESS_CFG_RESERVED_1__SHIFT) & DPU_LUT_ACCESS_CFG_RESERVED_1__MASK;
2418}
2419#define DPU_LUT_ACCESS_CFG_LUT_ADDR__MASK			0x000003ff
2420#define DPU_LUT_ACCESS_CFG_LUT_ADDR__SHIFT			0
2421static inline uint32_t DPU_LUT_ACCESS_CFG_LUT_ADDR(uint32_t val)
2422{
2423	return ((val) << DPU_LUT_ACCESS_CFG_LUT_ADDR__SHIFT) & DPU_LUT_ACCESS_CFG_LUT_ADDR__MASK;
2424}
2425
2426#define REG_DPU_LUT_ACCESS_DATA					0x00004104
2427#define DPU_LUT_ACCESS_DATA_RESERVED_0__MASK			0xffff0000
2428#define DPU_LUT_ACCESS_DATA_RESERVED_0__SHIFT			16
2429static inline uint32_t DPU_LUT_ACCESS_DATA_RESERVED_0(uint32_t val)
2430{
2431	return ((val) << DPU_LUT_ACCESS_DATA_RESERVED_0__SHIFT) & DPU_LUT_ACCESS_DATA_RESERVED_0__MASK;
2432}
2433#define DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__MASK		0x0000ffff
2434#define DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__SHIFT		0
2435static inline uint32_t DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA(uint32_t val)
2436{
2437	return ((val) << DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__SHIFT) & DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__MASK;
2438}
2439
2440#define REG_DPU_LUT_CFG						0x00004108
2441#define DPU_LUT_CFG_RESERVED_0__MASK				0xffffff00
2442#define DPU_LUT_CFG_RESERVED_0__SHIFT				8
2443static inline uint32_t DPU_LUT_CFG_RESERVED_0(uint32_t val)
2444{
2445	return ((val) << DPU_LUT_CFG_RESERVED_0__SHIFT) & DPU_LUT_CFG_RESERVED_0__MASK;
2446}
2447#define DPU_LUT_CFG_LUT_CAL_SEL__MASK				0x00000080
2448#define DPU_LUT_CFG_LUT_CAL_SEL__SHIFT				7
2449static inline uint32_t DPU_LUT_CFG_LUT_CAL_SEL(uint32_t val)
2450{
2451	return ((val) << DPU_LUT_CFG_LUT_CAL_SEL__SHIFT) & DPU_LUT_CFG_LUT_CAL_SEL__MASK;
2452}
2453#define DPU_LUT_CFG_LUT_HYBRID_PRIORITY__MASK			0x00000040
2454#define DPU_LUT_CFG_LUT_HYBRID_PRIORITY__SHIFT			6
2455static inline uint32_t DPU_LUT_CFG_LUT_HYBRID_PRIORITY(uint32_t val)
2456{
2457	return ((val) << DPU_LUT_CFG_LUT_HYBRID_PRIORITY__SHIFT) & DPU_LUT_CFG_LUT_HYBRID_PRIORITY__MASK;
2458}
2459#define DPU_LUT_CFG_LUT_OFLOW_PRIORITY__MASK			0x00000020
2460#define DPU_LUT_CFG_LUT_OFLOW_PRIORITY__SHIFT			5
2461static inline uint32_t DPU_LUT_CFG_LUT_OFLOW_PRIORITY(uint32_t val)
2462{
2463	return ((val) << DPU_LUT_CFG_LUT_OFLOW_PRIORITY__SHIFT) & DPU_LUT_CFG_LUT_OFLOW_PRIORITY__MASK;
2464}
2465#define DPU_LUT_CFG_LUT_UFLOW_PRIORITY__MASK			0x00000010
2466#define DPU_LUT_CFG_LUT_UFLOW_PRIORITY__SHIFT			4
2467static inline uint32_t DPU_LUT_CFG_LUT_UFLOW_PRIORITY(uint32_t val)
2468{
2469	return ((val) << DPU_LUT_CFG_LUT_UFLOW_PRIORITY__SHIFT) & DPU_LUT_CFG_LUT_UFLOW_PRIORITY__MASK;
2470}
2471#define DPU_LUT_CFG_LUT_LO_LE_MUX__MASK				0x0000000c
2472#define DPU_LUT_CFG_LUT_LO_LE_MUX__SHIFT			2
2473static inline uint32_t DPU_LUT_CFG_LUT_LO_LE_MUX(uint32_t val)
2474{
2475	return ((val) << DPU_LUT_CFG_LUT_LO_LE_MUX__SHIFT) & DPU_LUT_CFG_LUT_LO_LE_MUX__MASK;
2476}
2477#define DPU_LUT_CFG_LUT_EXPAND_EN__MASK				0x00000002
2478#define DPU_LUT_CFG_LUT_EXPAND_EN__SHIFT			1
2479static inline uint32_t DPU_LUT_CFG_LUT_EXPAND_EN(uint32_t val)
2480{
2481	return ((val) << DPU_LUT_CFG_LUT_EXPAND_EN__SHIFT) & DPU_LUT_CFG_LUT_EXPAND_EN__MASK;
2482}
2483#define DPU_LUT_CFG_LUT_ROAD_SEL__MASK				0x00000001
2484#define DPU_LUT_CFG_LUT_ROAD_SEL__SHIFT				0
2485static inline uint32_t DPU_LUT_CFG_LUT_ROAD_SEL(uint32_t val)
2486{
2487	return ((val) << DPU_LUT_CFG_LUT_ROAD_SEL__SHIFT) & DPU_LUT_CFG_LUT_ROAD_SEL__MASK;
2488}
2489
2490#define REG_DPU_LUT_INFO					0x0000410c
2491#define DPU_LUT_INFO_RESERVED_0__MASK				0xff000000
2492#define DPU_LUT_INFO_RESERVED_0__SHIFT				24
2493static inline uint32_t DPU_LUT_INFO_RESERVED_0(uint32_t val)
2494{
2495	return ((val) << DPU_LUT_INFO_RESERVED_0__SHIFT) & DPU_LUT_INFO_RESERVED_0__MASK;
2496}
2497#define DPU_LUT_INFO_LUT_LO_INDEX_SELECT__MASK			0x00ff0000
2498#define DPU_LUT_INFO_LUT_LO_INDEX_SELECT__SHIFT			16
2499static inline uint32_t DPU_LUT_INFO_LUT_LO_INDEX_SELECT(uint32_t val)
2500{
2501	return ((val) << DPU_LUT_INFO_LUT_LO_INDEX_SELECT__SHIFT) & DPU_LUT_INFO_LUT_LO_INDEX_SELECT__MASK;
2502}
2503#define DPU_LUT_INFO_LUT_LE_INDEX_SELECT__MASK			0x0000ff00
2504#define DPU_LUT_INFO_LUT_LE_INDEX_SELECT__SHIFT			8
2505static inline uint32_t DPU_LUT_INFO_LUT_LE_INDEX_SELECT(uint32_t val)
2506{
2507	return ((val) << DPU_LUT_INFO_LUT_LE_INDEX_SELECT__SHIFT) & DPU_LUT_INFO_LUT_LE_INDEX_SELECT__MASK;
2508}
2509#define DPU_LUT_INFO_RESERVED_1__MASK				0x000000ff
2510#define DPU_LUT_INFO_RESERVED_1__SHIFT				0
2511static inline uint32_t DPU_LUT_INFO_RESERVED_1(uint32_t val)
2512{
2513	return ((val) << DPU_LUT_INFO_RESERVED_1__SHIFT) & DPU_LUT_INFO_RESERVED_1__MASK;
2514}
2515
2516#define REG_DPU_LUT_LE_START					0x00004110
2517#define DPU_LUT_LE_START_LUT_LE_START__MASK			0xffffffff
2518#define DPU_LUT_LE_START_LUT_LE_START__SHIFT			0
2519static inline uint32_t DPU_LUT_LE_START_LUT_LE_START(uint32_t val)
2520{
2521	return ((val) << DPU_LUT_LE_START_LUT_LE_START__SHIFT) & DPU_LUT_LE_START_LUT_LE_START__MASK;
2522}
2523
2524#define REG_DPU_LUT_LE_END					0x00004114
2525#define DPU_LUT_LE_END_LUT_LE_END__MASK				0xffffffff
2526#define DPU_LUT_LE_END_LUT_LE_END__SHIFT			0
2527static inline uint32_t DPU_LUT_LE_END_LUT_LE_END(uint32_t val)
2528{
2529	return ((val) << DPU_LUT_LE_END_LUT_LE_END__SHIFT) & DPU_LUT_LE_END_LUT_LE_END__MASK;
2530}
2531
2532#define REG_DPU_LUT_LO_START					0x00004118
2533#define DPU_LUT_LO_START_LUT_LO_START__MASK			0xffffffff
2534#define DPU_LUT_LO_START_LUT_LO_START__SHIFT			0
2535static inline uint32_t DPU_LUT_LO_START_LUT_LO_START(uint32_t val)
2536{
2537	return ((val) << DPU_LUT_LO_START_LUT_LO_START__SHIFT) & DPU_LUT_LO_START_LUT_LO_START__MASK;
2538}
2539
2540#define REG_DPU_LUT_LO_END					0x0000411c
2541#define DPU_LUT_LO_END_LUT_LO_END__MASK				0xffffffff
2542#define DPU_LUT_LO_END_LUT_LO_END__SHIFT			0
2543static inline uint32_t DPU_LUT_LO_END_LUT_LO_END(uint32_t val)
2544{
2545	return ((val) << DPU_LUT_LO_END_LUT_LO_END__SHIFT) & DPU_LUT_LO_END_LUT_LO_END__MASK;
2546}
2547
2548#define REG_DPU_LUT_LE_SLOPE_SCALE				0x00004120
2549#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__MASK	0xffff0000
2550#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__SHIFT	16
2551static inline uint32_t DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE(uint32_t val)
2552{
2553	return ((val) << DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__SHIFT) & DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__MASK;
2554}
2555#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__MASK	0x0000ffff
2556#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__SHIFT	0
2557static inline uint32_t DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE(uint32_t val)
2558{
2559	return ((val) << DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__SHIFT) & DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__MASK;
2560}
2561
2562#define REG_DPU_LUT_LE_SLOPE_SHIFT				0x00004124
2563#define DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__MASK			0xfffffc00
2564#define DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__SHIFT		10
2565static inline uint32_t DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0(uint32_t val)
2566{
2567	return ((val) << DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__SHIFT) & DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__MASK;
2568}
2569#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__MASK	0x000003e0
2570#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__SHIFT	5
2571static inline uint32_t DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT(uint32_t val)
2572{
2573	return ((val) << DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__SHIFT) & DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__MASK;
2574}
2575#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__MASK	0x0000001f
2576#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__SHIFT	0
2577static inline uint32_t DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT(uint32_t val)
2578{
2579	return ((val) << DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__SHIFT) & DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__MASK;
2580}
2581
2582#define REG_DPU_LUT_LO_SLOPE_SCALE				0x00004128
2583#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__MASK	0xffff0000
2584#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__SHIFT	16
2585static inline uint32_t DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE(uint32_t val)
2586{
2587	return ((val) << DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__SHIFT) & DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__MASK;
2588}
2589#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__MASK	0x0000ffff
2590#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__SHIFT	0
2591static inline uint32_t DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE(uint32_t val)
2592{
2593	return ((val) << DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__SHIFT) & DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__MASK;
2594}
2595
2596#define REG_DPU_LUT_LO_SLOPE_SHIFT				0x0000412c
2597#define DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__MASK			0xfffffc00
2598#define DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__SHIFT		10
2599static inline uint32_t DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0(uint32_t val)
2600{
2601	return ((val) << DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__SHIFT) & DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__MASK;
2602}
2603#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__MASK	0x000003e0
2604#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__SHIFT	5
2605static inline uint32_t DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT(uint32_t val)
2606{
2607	return ((val) << DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__SHIFT) & DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__MASK;
2608}
2609#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__MASK	0x0000001f
2610#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__SHIFT	0
2611static inline uint32_t DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT(uint32_t val)
2612{
2613	return ((val) << DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__SHIFT) & DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__MASK;
2614}
2615
2616#define REG_DPU_RDMA_RDMA_S_STATUS				0x00005000
2617#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK			0xfffc0000
2618#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT		18
2619static inline uint32_t DPU_RDMA_RDMA_S_STATUS_RESERVED_0(uint32_t val)
2620{
2621	return ((val) << DPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK;
2622}
2623#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK			0x00030000
2624#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT			16
2625static inline uint32_t DPU_RDMA_RDMA_S_STATUS_STATUS_1(uint32_t val)
2626{
2627	return ((val) << DPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT) & DPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK;
2628}
2629#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK			0x0000fffc
2630#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT		2
2631static inline uint32_t DPU_RDMA_RDMA_S_STATUS_RESERVED_1(uint32_t val)
2632{
2633	return ((val) << DPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK;
2634}
2635#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK			0x00000003
2636#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT			0
2637static inline uint32_t DPU_RDMA_RDMA_S_STATUS_STATUS_0(uint32_t val)
2638{
2639	return ((val) << DPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT) & DPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK;
2640}
2641
2642#define REG_DPU_RDMA_RDMA_S_POINTER				0x00005004
2643#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK		0xfffe0000
2644#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT		17
2645static inline uint32_t DPU_RDMA_RDMA_S_POINTER_RESERVED_0(uint32_t val)
2646{
2647	return ((val) << DPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK;
2648}
2649#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK			0x00010000
2650#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT			16
2651static inline uint32_t DPU_RDMA_RDMA_S_POINTER_EXECUTER(uint32_t val)
2652{
2653	return ((val) << DPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT) & DPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK;
2654}
2655#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK		0x0000ffc0
2656#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT		6
2657static inline uint32_t DPU_RDMA_RDMA_S_POINTER_RESERVED_1(uint32_t val)
2658{
2659	return ((val) << DPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK;
2660}
2661#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK		0x00000020
2662#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT	5
2663static inline uint32_t DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
2664{
2665	return ((val) << DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK;
2666}
2667#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK		0x00000010
2668#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT		4
2669static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
2670{
2671	return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK;
2672}
2673#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK		0x00000008
2674#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT		3
2675static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE(uint32_t val)
2676{
2677	return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK;
2678}
2679#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK		0x00000004
2680#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT		2
2681static inline uint32_t DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN(uint32_t val)
2682{
2683	return ((val) << DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT) & DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK;
2684}
2685#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK		0x00000002
2686#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT		1
2687static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN(uint32_t val)
2688{
2689	return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK;
2690}
2691#define DPU_RDMA_RDMA_S_POINTER_POINTER__MASK			0x00000001
2692#define DPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT			0
2693static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER(uint32_t val)
2694{
2695	return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER__MASK;
2696}
2697
2698#define REG_DPU_RDMA_RDMA_OPERATION_ENABLE			0x00005008
2699#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK		0xfffffffe
2700#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT	1
2701static inline uint32_t DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0(uint32_t val)
2702{
2703	return ((val) << DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK;
2704}
2705#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK		0x00000001
2706#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT		0
2707static inline uint32_t DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN(uint32_t val)
2708{
2709	return ((val) << DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT) & DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK;
2710}
2711
2712#define REG_DPU_RDMA_RDMA_DATA_CUBE_WIDTH			0x0000500c
2713#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__MASK		0xffffe000
2714#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__SHIFT		13
2715static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0(uint32_t val)
2716{
2717	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__MASK;
2718}
2719#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__MASK		0x00001fff
2720#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__SHIFT		0
2721static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH(uint32_t val)
2722{
2723	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__MASK;
2724}
2725
2726#define REG_DPU_RDMA_RDMA_DATA_CUBE_HEIGHT			0x00005010
2727#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__MASK		0xe0000000
2728#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT	29
2729static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0(uint32_t val)
2730{
2731	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__MASK;
2732}
2733#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__MASK	0x1fff0000
2734#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__SHIFT	16
2735static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR(uint32_t val)
2736{
2737	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__MASK;
2738}
2739#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__MASK		0x0000e000
2740#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT	13
2741static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1(uint32_t val)
2742{
2743	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__MASK;
2744}
2745#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__MASK		0x00001fff
2746#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__SHIFT		0
2747static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT(uint32_t val)
2748{
2749	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__MASK;
2750}
2751
2752#define REG_DPU_RDMA_RDMA_DATA_CUBE_CHANNEL			0x00005014
2753#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__MASK	0xffffe000
2754#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT	13
2755static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0(uint32_t val)
2756{
2757	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__MASK;
2758}
2759#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__MASK		0x00001fff
2760#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__SHIFT		0
2761static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL(uint32_t val)
2762{
2763	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__MASK;
2764}
2765
2766#define REG_DPU_RDMA_RDMA_SRC_BASE_ADDR				0x00005018
2767#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK		0xffffffff
2768#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT	0
2769static inline uint32_t DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR(uint32_t val)
2770{
2771	return ((val) << DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK;
2772}
2773
2774#define REG_DPU_RDMA_RDMA_BRDMA_CFG				0x0000501c
2775#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__MASK		0xffffffe0
2776#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__SHIFT		5
2777static inline uint32_t DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0(uint32_t val)
2778{
2779	return ((val) << DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__MASK;
2780}
2781#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__MASK		0x0000001e
2782#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__SHIFT		1
2783static inline uint32_t DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE(uint32_t val)
2784{
2785	return ((val) << DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__SHIFT) & DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__MASK;
2786}
2787#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__MASK		0x00000001
2788#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__SHIFT		0
2789static inline uint32_t DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1(uint32_t val)
2790{
2791	return ((val) << DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__MASK;
2792}
2793
2794#define REG_DPU_RDMA_RDMA_BS_BASE_ADDR				0x00005020
2795#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__MASK		0xffffffff
2796#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__SHIFT		0
2797static inline uint32_t DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR(uint32_t val)
2798{
2799	return ((val) << DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__MASK;
2800}
2801
2802#define REG_DPU_RDMA_RDMA_NRDMA_CFG				0x00005028
2803#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__MASK		0xffffffe0
2804#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__SHIFT		5
2805static inline uint32_t DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0(uint32_t val)
2806{
2807	return ((val) << DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__MASK;
2808}
2809#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__MASK		0x0000001e
2810#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__SHIFT		1
2811static inline uint32_t DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE(uint32_t val)
2812{
2813	return ((val) << DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__SHIFT) & DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__MASK;
2814}
2815#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__MASK		0x00000001
2816#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__SHIFT		0
2817static inline uint32_t DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1(uint32_t val)
2818{
2819	return ((val) << DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__MASK;
2820}
2821
2822#define REG_DPU_RDMA_RDMA_BN_BASE_ADDR				0x0000502c
2823#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__MASK		0xffffffff
2824#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__SHIFT		0
2825static inline uint32_t DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR(uint32_t val)
2826{
2827	return ((val) << DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__MASK;
2828}
2829
2830#define REG_DPU_RDMA_RDMA_ERDMA_CFG				0x00005034
2831#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__MASK		0xc0000000
2832#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__SHIFT		30
2833static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE(uint32_t val)
2834{
2835	return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__MASK;
2836}
2837#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__MASK		0x20000000
2838#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__SHIFT		29
2839static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE(uint32_t val)
2840{
2841	return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__MASK;
2842}
2843#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__MASK		0x10000000
2844#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__SHIFT		28
2845static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN(uint32_t val)
2846{
2847	return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__MASK;
2848}
2849#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__MASK		0x0ffffff0
2850#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__SHIFT		4
2851static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0(uint32_t val)
2852{
2853	return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__MASK;
2854}
2855#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__MASK		0x0000000c
2856#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__SHIFT		2
2857static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE(uint32_t val)
2858{
2859	return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__MASK;
2860}
2861#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__MASK		0x00000002
2862#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__SHIFT		1
2863static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS(uint32_t val)
2864{
2865	return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__MASK;
2866}
2867#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__MASK		0x00000001
2868#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__SHIFT		0
2869static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE(uint32_t val)
2870{
2871	return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__MASK;
2872}
2873
2874#define REG_DPU_RDMA_RDMA_EW_BASE_ADDR				0x00005038
2875#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__MASK		0xffffffff
2876#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__SHIFT		0
2877static inline uint32_t DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR(uint32_t val)
2878{
2879	return ((val) << DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__MASK;
2880}
2881
2882#define REG_DPU_RDMA_RDMA_EW_SURF_STRIDE			0x00005040
2883#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__MASK	0xfffffff0
2884#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__SHIFT	4
2885static inline uint32_t DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE(uint32_t val)
2886{
2887	return ((val) << DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__SHIFT) & DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__MASK;
2888}
2889#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__MASK		0x0000000f
2890#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__SHIFT		0
2891static inline uint32_t DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0(uint32_t val)
2892{
2893	return ((val) << DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__MASK;
2894}
2895
2896#define REG_DPU_RDMA_RDMA_FEATURE_MODE_CFG			0x00005044
2897#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__MASK		0xfffc0000
2898#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__SHIFT	18
2899static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0(uint32_t val)
2900{
2901	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__MASK;
2902}
2903#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__MASK	0x00038000
2904#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__SHIFT	15
2905static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION(uint32_t val)
2906{
2907	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__MASK;
2908}
2909#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__MASK		0x00007800
2910#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__SHIFT		11
2911static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN(uint32_t val)
2912{
2913	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__MASK;
2914}
2915#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__MASK		0x00000700
2916#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__SHIFT		8
2917static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE(uint32_t val)
2918{
2919	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__MASK;
2920}
2921#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__MASK	0x000000e0
2922#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__SHIFT	5
2923static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION(uint32_t val)
2924{
2925	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__MASK;
2926}
2927#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__MASK	0x00000010
2928#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__SHIFT	4
2929static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE(uint32_t val)
2930{
2931	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__MASK;
2932}
2933#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__MASK	0x00000008
2934#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__SHIFT	3
2935static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN(uint32_t val)
2936{
2937	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__MASK;
2938}
2939#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__MASK		0x00000006
2940#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__SHIFT		1
2941static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE(uint32_t val)
2942{
2943	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__MASK;
2944}
2945#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__MASK	0x00000001
2946#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__SHIFT	0
2947static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE(uint32_t val)
2948{
2949	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__MASK;
2950}
2951
2952#define REG_DPU_RDMA_RDMA_SRC_DMA_CFG				0x00005048
2953#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__MASK		0xfff80000
2954#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__SHIFT	19
2955static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR(uint32_t val)
2956{
2957	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__MASK;
2958}
2959#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__MASK		0x0007c000
2960#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__SHIFT		14
2961static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0(uint32_t val)
2962{
2963	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__MASK;
2964}
2965#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__MASK		0x00002000
2966#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__SHIFT		13
2967static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD(uint32_t val)
2968{
2969	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__MASK;
2970}
2971#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__MASK		0x00001000
2972#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__SHIFT		12
2973static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN(uint32_t val)
2974{
2975	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__MASK;
2976}
2977#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__MASK	0x00000e00
2978#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__SHIFT	9
2979static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT(uint32_t val)
2980{
2981	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__MASK;
2982}
2983#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__MASK	0x000001c0
2984#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__SHIFT	6
2985static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH(uint32_t val)
2986{
2987	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__MASK;
2988}
2989#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__MASK		0x00000038
2990#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__SHIFT		3
2991static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT(uint32_t val)
2992{
2993	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__MASK;
2994}
2995#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__MASK		0x00000007
2996#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__SHIFT		0
2997static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH(uint32_t val)
2998{
2999	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__MASK;
3000}
3001
3002#define REG_DPU_RDMA_RDMA_SURF_NOTCH				0x0000504c
3003#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__MASK		0xfffffff0
3004#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__SHIFT		4
3005static inline uint32_t DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR(uint32_t val)
3006{
3007	return ((val) << DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__SHIFT) & DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__MASK;
3008}
3009#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__MASK		0x0000000f
3010#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__SHIFT		0
3011static inline uint32_t DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0(uint32_t val)
3012{
3013	return ((val) << DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__MASK;
3014}
3015
3016#define REG_DPU_RDMA_RDMA_PAD_CFG				0x00005064
3017#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__MASK			0xffff0000
3018#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__SHIFT			16
3019static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE(uint32_t val)
3020{
3021	return ((val) << DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__MASK;
3022}
3023#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__MASK			0x0000ff80
3024#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__SHIFT			7
3025static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_RESERVED_0(uint32_t val)
3026{
3027	return ((val) << DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__MASK;
3028}
3029#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__MASK			0x00000070
3030#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__SHIFT			4
3031static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_PAD_TOP(uint32_t val)
3032{
3033	return ((val) << DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__MASK;
3034}
3035#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__MASK			0x00000008
3036#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__SHIFT			3
3037static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_RESERVED_1(uint32_t val)
3038{
3039	return ((val) << DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__MASK;
3040}
3041#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__MASK			0x00000007
3042#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__SHIFT			0
3043static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT(uint32_t val)
3044{
3045	return ((val) << DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__MASK;
3046}
3047
3048#define REG_DPU_RDMA_RDMA_WEIGHT				0x00005068
3049#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__MASK			0xff000000
3050#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__SHIFT			24
3051static inline uint32_t DPU_RDMA_RDMA_WEIGHT_E_WEIGHT(uint32_t val)
3052{
3053	return ((val) << DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__MASK;
3054}
3055#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__MASK			0x00ff0000
3056#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__SHIFT			16
3057static inline uint32_t DPU_RDMA_RDMA_WEIGHT_N_WEIGHT(uint32_t val)
3058{
3059	return ((val) << DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__MASK;
3060}
3061#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__MASK			0x0000ff00
3062#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__SHIFT			8
3063static inline uint32_t DPU_RDMA_RDMA_WEIGHT_B_WEIGHT(uint32_t val)
3064{
3065	return ((val) << DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__MASK;
3066}
3067#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__MASK			0x000000ff
3068#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__SHIFT			0
3069static inline uint32_t DPU_RDMA_RDMA_WEIGHT_M_WEIGHT(uint32_t val)
3070{
3071	return ((val) << DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__MASK;
3072}
3073
3074#define REG_DPU_RDMA_RDMA_EW_SURF_NOTCH				0x0000506c
3075#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__MASK		0xfffffff0
3076#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__SHIFT	4
3077static inline uint32_t DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH(uint32_t val)
3078{
3079	return ((val) << DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__SHIFT) & DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__MASK;
3080}
3081#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__MASK		0x0000000f
3082#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__SHIFT		0
3083static inline uint32_t DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0(uint32_t val)
3084{
3085	return ((val) << DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__MASK;
3086}
3087
3088#define REG_PPU_S_STATUS					0x00006000
3089#define PPU_S_STATUS_RESERVED_0__MASK				0xfffc0000
3090#define PPU_S_STATUS_RESERVED_0__SHIFT				18
3091static inline uint32_t PPU_S_STATUS_RESERVED_0(uint32_t val)
3092{
3093	return ((val) << PPU_S_STATUS_RESERVED_0__SHIFT) & PPU_S_STATUS_RESERVED_0__MASK;
3094}
3095#define PPU_S_STATUS_STATUS_1__MASK				0x00030000
3096#define PPU_S_STATUS_STATUS_1__SHIFT				16
3097static inline uint32_t PPU_S_STATUS_STATUS_1(uint32_t val)
3098{
3099	return ((val) << PPU_S_STATUS_STATUS_1__SHIFT) & PPU_S_STATUS_STATUS_1__MASK;
3100}
3101#define PPU_S_STATUS_RESERVED_1__MASK				0x0000fffc
3102#define PPU_S_STATUS_RESERVED_1__SHIFT				2
3103static inline uint32_t PPU_S_STATUS_RESERVED_1(uint32_t val)
3104{
3105	return ((val) << PPU_S_STATUS_RESERVED_1__SHIFT) & PPU_S_STATUS_RESERVED_1__MASK;
3106}
3107#define PPU_S_STATUS_STATUS_0__MASK				0x00000003
3108#define PPU_S_STATUS_STATUS_0__SHIFT				0
3109static inline uint32_t PPU_S_STATUS_STATUS_0(uint32_t val)
3110{
3111	return ((val) << PPU_S_STATUS_STATUS_0__SHIFT) & PPU_S_STATUS_STATUS_0__MASK;
3112}
3113
3114#define REG_PPU_S_POINTER					0x00006004
3115#define PPU_S_POINTER_RESERVED_0__MASK				0xfffe0000
3116#define PPU_S_POINTER_RESERVED_0__SHIFT				17
3117static inline uint32_t PPU_S_POINTER_RESERVED_0(uint32_t val)
3118{
3119	return ((val) << PPU_S_POINTER_RESERVED_0__SHIFT) & PPU_S_POINTER_RESERVED_0__MASK;
3120}
3121#define PPU_S_POINTER_EXECUTER__MASK				0x00010000
3122#define PPU_S_POINTER_EXECUTER__SHIFT				16
3123static inline uint32_t PPU_S_POINTER_EXECUTER(uint32_t val)
3124{
3125	return ((val) << PPU_S_POINTER_EXECUTER__SHIFT) & PPU_S_POINTER_EXECUTER__MASK;
3126}
3127#define PPU_S_POINTER_RESERVED_1__MASK				0x0000ffc0
3128#define PPU_S_POINTER_RESERVED_1__SHIFT				6
3129static inline uint32_t PPU_S_POINTER_RESERVED_1(uint32_t val)
3130{
3131	return ((val) << PPU_S_POINTER_RESERVED_1__SHIFT) & PPU_S_POINTER_RESERVED_1__MASK;
3132}
3133#define PPU_S_POINTER_EXECUTER_PP_CLEAR__MASK			0x00000020
3134#define PPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT			5
3135static inline uint32_t PPU_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
3136{
3137	return ((val) << PPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & PPU_S_POINTER_EXECUTER_PP_CLEAR__MASK;
3138}
3139#define PPU_S_POINTER_POINTER_PP_CLEAR__MASK			0x00000010
3140#define PPU_S_POINTER_POINTER_PP_CLEAR__SHIFT			4
3141static inline uint32_t PPU_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
3142{
3143	return ((val) << PPU_S_POINTER_POINTER_PP_CLEAR__SHIFT) & PPU_S_POINTER_POINTER_PP_CLEAR__MASK;
3144}
3145#define PPU_S_POINTER_POINTER_PP_MODE__MASK			0x00000008
3146#define PPU_S_POINTER_POINTER_PP_MODE__SHIFT			3
3147static inline uint32_t PPU_S_POINTER_POINTER_PP_MODE(uint32_t val)
3148{
3149	return ((val) << PPU_S_POINTER_POINTER_PP_MODE__SHIFT) & PPU_S_POINTER_POINTER_PP_MODE__MASK;
3150}
3151#define PPU_S_POINTER_EXECUTER_PP_EN__MASK			0x00000004
3152#define PPU_S_POINTER_EXECUTER_PP_EN__SHIFT			2
3153static inline uint32_t PPU_S_POINTER_EXECUTER_PP_EN(uint32_t val)
3154{
3155	return ((val) << PPU_S_POINTER_EXECUTER_PP_EN__SHIFT) & PPU_S_POINTER_EXECUTER_PP_EN__MASK;
3156}
3157#define PPU_S_POINTER_POINTER_PP_EN__MASK			0x00000002
3158#define PPU_S_POINTER_POINTER_PP_EN__SHIFT			1
3159static inline uint32_t PPU_S_POINTER_POINTER_PP_EN(uint32_t val)
3160{
3161	return ((val) << PPU_S_POINTER_POINTER_PP_EN__SHIFT) & PPU_S_POINTER_POINTER_PP_EN__MASK;
3162}
3163#define PPU_S_POINTER_POINTER__MASK				0x00000001
3164#define PPU_S_POINTER_POINTER__SHIFT				0
3165static inline uint32_t PPU_S_POINTER_POINTER(uint32_t val)
3166{
3167	return ((val) << PPU_S_POINTER_POINTER__SHIFT) & PPU_S_POINTER_POINTER__MASK;
3168}
3169
3170#define REG_PPU_OPERATION_ENABLE				0x00006008
3171#define PPU_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
3172#define PPU_OPERATION_ENABLE_RESERVED_0__SHIFT			1
3173static inline uint32_t PPU_OPERATION_ENABLE_RESERVED_0(uint32_t val)
3174{
3175	return ((val) << PPU_OPERATION_ENABLE_RESERVED_0__SHIFT) & PPU_OPERATION_ENABLE_RESERVED_0__MASK;
3176}
3177#define PPU_OPERATION_ENABLE_OP_EN__MASK			0x00000001
3178#define PPU_OPERATION_ENABLE_OP_EN__SHIFT			0
3179static inline uint32_t PPU_OPERATION_ENABLE_OP_EN(uint32_t val)
3180{
3181	return ((val) << PPU_OPERATION_ENABLE_OP_EN__SHIFT) & PPU_OPERATION_ENABLE_OP_EN__MASK;
3182}
3183
3184#define REG_PPU_DATA_CUBE_IN_WIDTH				0x0000600c
3185#define PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__MASK			0xffffe000
3186#define PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__SHIFT		13
3187static inline uint32_t PPU_DATA_CUBE_IN_WIDTH_RESERVED_0(uint32_t val)
3188{
3189	return ((val) << PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__SHIFT) & PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__MASK;
3190}
3191#define PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK		0x00001fff
3192#define PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT		0
3193static inline uint32_t PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH(uint32_t val)
3194{
3195	return ((val) << PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT) & PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK;
3196}
3197
3198#define REG_PPU_DATA_CUBE_IN_HEIGHT				0x00006010
3199#define PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__MASK		0xffffe000
3200#define PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT		13
3201static inline uint32_t PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0(uint32_t val)
3202{
3203	return ((val) << PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT) & PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__MASK;
3204}
3205#define PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK		0x00001fff
3206#define PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT		0
3207static inline uint32_t PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT(uint32_t val)
3208{
3209	return ((val) << PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT) & PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK;
3210}
3211
3212#define REG_PPU_DATA_CUBE_IN_CHANNEL				0x00006014
3213#define PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__MASK		0xffffe000
3214#define PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT		13
3215static inline uint32_t PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0(uint32_t val)
3216{
3217	return ((val) << PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT) & PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__MASK;
3218}
3219#define PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK		0x00001fff
3220#define PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT		0
3221static inline uint32_t PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL(uint32_t val)
3222{
3223	return ((val) << PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT) & PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK;
3224}
3225
3226#define REG_PPU_DATA_CUBE_OUT_WIDTH				0x00006018
3227#define PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__MASK		0xffffe000
3228#define PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__SHIFT		13
3229static inline uint32_t PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0(uint32_t val)
3230{
3231	return ((val) << PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__SHIFT) & PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__MASK;
3232}
3233#define PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__MASK		0x00001fff
3234#define PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__SHIFT		0
3235static inline uint32_t PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH(uint32_t val)
3236{
3237	return ((val) << PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__SHIFT) & PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__MASK;
3238}
3239
3240#define REG_PPU_DATA_CUBE_OUT_HEIGHT				0x0000601c
3241#define PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__MASK		0xffffe000
3242#define PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__SHIFT		13
3243static inline uint32_t PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0(uint32_t val)
3244{
3245	return ((val) << PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__SHIFT) & PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__MASK;
3246}
3247#define PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__MASK		0x00001fff
3248#define PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__SHIFT		0
3249static inline uint32_t PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT(uint32_t val)
3250{
3251	return ((val) << PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__SHIFT) & PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__MASK;
3252}
3253
3254#define REG_PPU_DATA_CUBE_OUT_CHANNEL				0x00006020
3255#define PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__MASK		0xffffe000
3256#define PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__SHIFT		13
3257static inline uint32_t PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0(uint32_t val)
3258{
3259	return ((val) << PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__SHIFT) & PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__MASK;
3260}
3261#define PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__MASK	0x00001fff
3262#define PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__SHIFT	0
3263static inline uint32_t PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL(uint32_t val)
3264{
3265	return ((val) << PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__SHIFT) & PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__MASK;
3266}
3267
3268#define REG_PPU_OPERATION_MODE_CFG				0x00006024
3269#define PPU_OPERATION_MODE_CFG_RESERVED_0__MASK			0x80000000
3270#define PPU_OPERATION_MODE_CFG_RESERVED_0__SHIFT		31
3271static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_0(uint32_t val)
3272{
3273	return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_0__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_0__MASK;
3274}
3275#define PPU_OPERATION_MODE_CFG_INDEX_EN__MASK			0x40000000
3276#define PPU_OPERATION_MODE_CFG_INDEX_EN__SHIFT			30
3277static inline uint32_t PPU_OPERATION_MODE_CFG_INDEX_EN(uint32_t val)
3278{
3279	return ((val) << PPU_OPERATION_MODE_CFG_INDEX_EN__SHIFT) & PPU_OPERATION_MODE_CFG_INDEX_EN__MASK;
3280}
3281#define PPU_OPERATION_MODE_CFG_RESERVED_1__MASK			0x20000000
3282#define PPU_OPERATION_MODE_CFG_RESERVED_1__SHIFT		29
3283static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_1(uint32_t val)
3284{
3285	return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_1__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_1__MASK;
3286}
3287#define PPU_OPERATION_MODE_CFG_NOTCH_ADDR__MASK			0x1fff0000
3288#define PPU_OPERATION_MODE_CFG_NOTCH_ADDR__SHIFT		16
3289static inline uint32_t PPU_OPERATION_MODE_CFG_NOTCH_ADDR(uint32_t val)
3290{
3291	return ((val) << PPU_OPERATION_MODE_CFG_NOTCH_ADDR__SHIFT) & PPU_OPERATION_MODE_CFG_NOTCH_ADDR__MASK;
3292}
3293#define PPU_OPERATION_MODE_CFG_RESERVED_2__MASK			0x0000ff00
3294#define PPU_OPERATION_MODE_CFG_RESERVED_2__SHIFT		8
3295static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_2(uint32_t val)
3296{
3297	return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_2__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_2__MASK;
3298}
3299#define PPU_OPERATION_MODE_CFG_USE_CNT__MASK			0x000000e0
3300#define PPU_OPERATION_MODE_CFG_USE_CNT__SHIFT			5
3301static inline uint32_t PPU_OPERATION_MODE_CFG_USE_CNT(uint32_t val)
3302{
3303	return ((val) << PPU_OPERATION_MODE_CFG_USE_CNT__SHIFT) & PPU_OPERATION_MODE_CFG_USE_CNT__MASK;
3304}
3305#define PPU_OPERATION_MODE_CFG_FLYING_MODE__MASK		0x00000010
3306#define PPU_OPERATION_MODE_CFG_FLYING_MODE__SHIFT		4
3307static inline uint32_t PPU_OPERATION_MODE_CFG_FLYING_MODE(uint32_t val)
3308{
3309	return ((val) << PPU_OPERATION_MODE_CFG_FLYING_MODE__SHIFT) & PPU_OPERATION_MODE_CFG_FLYING_MODE__MASK;
3310}
3311#define PPU_OPERATION_MODE_CFG_RESERVED_3__MASK			0x0000000c
3312#define PPU_OPERATION_MODE_CFG_RESERVED_3__SHIFT		2
3313static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_3(uint32_t val)
3314{
3315	return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_3__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_3__MASK;
3316}
3317#define PPU_OPERATION_MODE_CFG_POOLING_METHOD__MASK		0x00000003
3318#define PPU_OPERATION_MODE_CFG_POOLING_METHOD__SHIFT		0
3319static inline uint32_t PPU_OPERATION_MODE_CFG_POOLING_METHOD(uint32_t val)
3320{
3321	return ((val) << PPU_OPERATION_MODE_CFG_POOLING_METHOD__SHIFT) & PPU_OPERATION_MODE_CFG_POOLING_METHOD__MASK;
3322}
3323
3324#define REG_PPU_POOLING_KERNEL_CFG				0x00006034
3325#define PPU_POOLING_KERNEL_CFG_RESERVED_0__MASK			0xff000000
3326#define PPU_POOLING_KERNEL_CFG_RESERVED_0__SHIFT		24
3327static inline uint32_t PPU_POOLING_KERNEL_CFG_RESERVED_0(uint32_t val)
3328{
3329	return ((val) << PPU_POOLING_KERNEL_CFG_RESERVED_0__SHIFT) & PPU_POOLING_KERNEL_CFG_RESERVED_0__MASK;
3330}
3331#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__MASK	0x00f00000
3332#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__SHIFT	20
3333static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT(uint32_t val)
3334{
3335	return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__MASK;
3336}
3337#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__MASK	0x000f0000
3338#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__SHIFT	16
3339static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH(uint32_t val)
3340{
3341	return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__MASK;
3342}
3343#define PPU_POOLING_KERNEL_CFG_RESERVED_1__MASK			0x0000f000
3344#define PPU_POOLING_KERNEL_CFG_RESERVED_1__SHIFT		12
3345static inline uint32_t PPU_POOLING_KERNEL_CFG_RESERVED_1(uint32_t val)
3346{
3347	return ((val) << PPU_POOLING_KERNEL_CFG_RESERVED_1__SHIFT) & PPU_POOLING_KERNEL_CFG_RESERVED_1__MASK;
3348}
3349#define PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__MASK		0x00000f00
3350#define PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__SHIFT		8
3351static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT(uint32_t val)
3352{
3353	return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__MASK;
3354}
3355#define PPU_POOLING_KERNEL_CFG_RESERVED_2__MASK			0x000000f0
3356#define PPU_POOLING_KERNEL_CFG_RESERVED_2__SHIFT		4
3357static inline uint32_t PPU_POOLING_KERNEL_CFG_RESERVED_2(uint32_t val)
3358{
3359	return ((val) << PPU_POOLING_KERNEL_CFG_RESERVED_2__SHIFT) & PPU_POOLING_KERNEL_CFG_RESERVED_2__MASK;
3360}
3361#define PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__MASK		0x0000000f
3362#define PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__SHIFT		0
3363static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH(uint32_t val)
3364{
3365	return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__MASK;
3366}
3367
3368#define REG_PPU_RECIP_KERNEL_WIDTH				0x00006038
3369#define PPU_RECIP_KERNEL_WIDTH_RESERVED_0__MASK			0xfffe0000
3370#define PPU_RECIP_KERNEL_WIDTH_RESERVED_0__SHIFT		17
3371static inline uint32_t PPU_RECIP_KERNEL_WIDTH_RESERVED_0(uint32_t val)
3372{
3373	return ((val) << PPU_RECIP_KERNEL_WIDTH_RESERVED_0__SHIFT) & PPU_RECIP_KERNEL_WIDTH_RESERVED_0__MASK;
3374}
3375#define PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__MASK		0x0001ffff
3376#define PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__SHIFT	0
3377static inline uint32_t PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH(uint32_t val)
3378{
3379	return ((val) << PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__SHIFT) & PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__MASK;
3380}
3381
3382#define REG_PPU_RECIP_KERNEL_HEIGHT				0x0000603c
3383#define PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__MASK		0xfffe0000
3384#define PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__SHIFT		17
3385static inline uint32_t PPU_RECIP_KERNEL_HEIGHT_RESERVED_0(uint32_t val)
3386{
3387	return ((val) << PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__SHIFT) & PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__MASK;
3388}
3389#define PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__MASK	0x0001ffff
3390#define PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__SHIFT	0
3391static inline uint32_t PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT(uint32_t val)
3392{
3393	return ((val) << PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__SHIFT) & PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__MASK;
3394}
3395
3396#define REG_PPU_POOLING_PADDING_CFG				0x00006040
3397#define PPU_POOLING_PADDING_CFG_RESERVED_0__MASK		0xffff8000
3398#define PPU_POOLING_PADDING_CFG_RESERVED_0__SHIFT		15
3399static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_0(uint32_t val)
3400{
3401	return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_0__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_0__MASK;
3402}
3403#define PPU_POOLING_PADDING_CFG_PAD_BOTTOM__MASK		0x00007000
3404#define PPU_POOLING_PADDING_CFG_PAD_BOTTOM__SHIFT		12
3405static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_BOTTOM(uint32_t val)
3406{
3407	return ((val) << PPU_POOLING_PADDING_CFG_PAD_BOTTOM__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_BOTTOM__MASK;
3408}
3409#define PPU_POOLING_PADDING_CFG_RESERVED_1__MASK		0x00000800
3410#define PPU_POOLING_PADDING_CFG_RESERVED_1__SHIFT		11
3411static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_1(uint32_t val)
3412{
3413	return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_1__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_1__MASK;
3414}
3415#define PPU_POOLING_PADDING_CFG_PAD_RIGHT__MASK			0x00000700
3416#define PPU_POOLING_PADDING_CFG_PAD_RIGHT__SHIFT		8
3417static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_RIGHT(uint32_t val)
3418{
3419	return ((val) << PPU_POOLING_PADDING_CFG_PAD_RIGHT__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_RIGHT__MASK;
3420}
3421#define PPU_POOLING_PADDING_CFG_RESERVED_2__MASK		0x00000080
3422#define PPU_POOLING_PADDING_CFG_RESERVED_2__SHIFT		7
3423static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_2(uint32_t val)
3424{
3425	return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_2__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_2__MASK;
3426}
3427#define PPU_POOLING_PADDING_CFG_PAD_TOP__MASK			0x00000070
3428#define PPU_POOLING_PADDING_CFG_PAD_TOP__SHIFT			4
3429static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_TOP(uint32_t val)
3430{
3431	return ((val) << PPU_POOLING_PADDING_CFG_PAD_TOP__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_TOP__MASK;
3432}
3433#define PPU_POOLING_PADDING_CFG_RESERVED_3__MASK		0x00000008
3434#define PPU_POOLING_PADDING_CFG_RESERVED_3__SHIFT		3
3435static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_3(uint32_t val)
3436{
3437	return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_3__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_3__MASK;
3438}
3439#define PPU_POOLING_PADDING_CFG_PAD_LEFT__MASK			0x00000007
3440#define PPU_POOLING_PADDING_CFG_PAD_LEFT__SHIFT			0
3441static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_LEFT(uint32_t val)
3442{
3443	return ((val) << PPU_POOLING_PADDING_CFG_PAD_LEFT__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_LEFT__MASK;
3444}
3445
3446#define REG_PPU_PADDING_VALUE_1_CFG				0x00006044
3447#define PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__MASK		0xffffffff
3448#define PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__SHIFT		0
3449static inline uint32_t PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0(uint32_t val)
3450{
3451	return ((val) << PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__SHIFT) & PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__MASK;
3452}
3453
3454#define REG_PPU_PADDING_VALUE_2_CFG				0x00006048
3455#define PPU_PADDING_VALUE_2_CFG_RESERVED_0__MASK		0xfffffff8
3456#define PPU_PADDING_VALUE_2_CFG_RESERVED_0__SHIFT		3
3457static inline uint32_t PPU_PADDING_VALUE_2_CFG_RESERVED_0(uint32_t val)
3458{
3459	return ((val) << PPU_PADDING_VALUE_2_CFG_RESERVED_0__SHIFT) & PPU_PADDING_VALUE_2_CFG_RESERVED_0__MASK;
3460}
3461#define PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__MASK		0x00000007
3462#define PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__SHIFT		0
3463static inline uint32_t PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1(uint32_t val)
3464{
3465	return ((val) << PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__SHIFT) & PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__MASK;
3466}
3467
3468#define REG_PPU_DST_BASE_ADDR					0x00006070
3469#define PPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK			0xfffffff0
3470#define PPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT			4
3471static inline uint32_t PPU_DST_BASE_ADDR_DST_BASE_ADDR(uint32_t val)
3472{
3473	return ((val) << PPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT) & PPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK;
3474}
3475#define PPU_DST_BASE_ADDR_RESERVED_0__MASK			0x0000000f
3476#define PPU_DST_BASE_ADDR_RESERVED_0__SHIFT			0
3477static inline uint32_t PPU_DST_BASE_ADDR_RESERVED_0(uint32_t val)
3478{
3479	return ((val) << PPU_DST_BASE_ADDR_RESERVED_0__SHIFT) & PPU_DST_BASE_ADDR_RESERVED_0__MASK;
3480}
3481
3482#define REG_PPU_DST_SURF_STRIDE					0x0000607c
3483#define PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK		0xfffffff0
3484#define PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT		4
3485static inline uint32_t PPU_DST_SURF_STRIDE_DST_SURF_STRIDE(uint32_t val)
3486{
3487	return ((val) << PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT) & PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK;
3488}
3489#define PPU_DST_SURF_STRIDE_RESERVED_0__MASK			0x0000000f
3490#define PPU_DST_SURF_STRIDE_RESERVED_0__SHIFT			0
3491static inline uint32_t PPU_DST_SURF_STRIDE_RESERVED_0(uint32_t val)
3492{
3493	return ((val) << PPU_DST_SURF_STRIDE_RESERVED_0__SHIFT) & PPU_DST_SURF_STRIDE_RESERVED_0__MASK;
3494}
3495
3496#define REG_PPU_DATA_FORMAT					0x00006084
3497#define PPU_DATA_FORMAT_INDEX_ADD__MASK				0xfffffff0
3498#define PPU_DATA_FORMAT_INDEX_ADD__SHIFT			4
3499static inline uint32_t PPU_DATA_FORMAT_INDEX_ADD(uint32_t val)
3500{
3501	return ((val) << PPU_DATA_FORMAT_INDEX_ADD__SHIFT) & PPU_DATA_FORMAT_INDEX_ADD__MASK;
3502}
3503#define PPU_DATA_FORMAT_DPU_FLYIN__MASK				0x00000008
3504#define PPU_DATA_FORMAT_DPU_FLYIN__SHIFT			3
3505static inline uint32_t PPU_DATA_FORMAT_DPU_FLYIN(uint32_t val)
3506{
3507	return ((val) << PPU_DATA_FORMAT_DPU_FLYIN__SHIFT) & PPU_DATA_FORMAT_DPU_FLYIN__MASK;
3508}
3509#define PPU_DATA_FORMAT_PROC_PRECISION__MASK			0x00000007
3510#define PPU_DATA_FORMAT_PROC_PRECISION__SHIFT			0
3511static inline uint32_t PPU_DATA_FORMAT_PROC_PRECISION(uint32_t val)
3512{
3513	return ((val) << PPU_DATA_FORMAT_PROC_PRECISION__SHIFT) & PPU_DATA_FORMAT_PROC_PRECISION__MASK;
3514}
3515
3516#define REG_PPU_MISC_CTRL					0x000060dc
3517#define PPU_MISC_CTRL_SURF_LEN__MASK				0xffff0000
3518#define PPU_MISC_CTRL_SURF_LEN__SHIFT				16
3519static inline uint32_t PPU_MISC_CTRL_SURF_LEN(uint32_t val)
3520{
3521	return ((val) << PPU_MISC_CTRL_SURF_LEN__SHIFT) & PPU_MISC_CTRL_SURF_LEN__MASK;
3522}
3523#define PPU_MISC_CTRL_RESERVED_0__MASK				0x0000fe00
3524#define PPU_MISC_CTRL_RESERVED_0__SHIFT				9
3525static inline uint32_t PPU_MISC_CTRL_RESERVED_0(uint32_t val)
3526{
3527	return ((val) << PPU_MISC_CTRL_RESERVED_0__SHIFT) & PPU_MISC_CTRL_RESERVED_0__MASK;
3528}
3529#define PPU_MISC_CTRL_MC_SURF_OUT__MASK				0x00000100
3530#define PPU_MISC_CTRL_MC_SURF_OUT__SHIFT			8
3531static inline uint32_t PPU_MISC_CTRL_MC_SURF_OUT(uint32_t val)
3532{
3533	return ((val) << PPU_MISC_CTRL_MC_SURF_OUT__SHIFT) & PPU_MISC_CTRL_MC_SURF_OUT__MASK;
3534}
3535#define PPU_MISC_CTRL_NONALIGN__MASK				0x00000080
3536#define PPU_MISC_CTRL_NONALIGN__SHIFT				7
3537static inline uint32_t PPU_MISC_CTRL_NONALIGN(uint32_t val)
3538{
3539	return ((val) << PPU_MISC_CTRL_NONALIGN__SHIFT) & PPU_MISC_CTRL_NONALIGN__MASK;
3540}
3541#define PPU_MISC_CTRL_RESERVED_1__MASK				0x00000070
3542#define PPU_MISC_CTRL_RESERVED_1__SHIFT				4
3543static inline uint32_t PPU_MISC_CTRL_RESERVED_1(uint32_t val)
3544{
3545	return ((val) << PPU_MISC_CTRL_RESERVED_1__SHIFT) & PPU_MISC_CTRL_RESERVED_1__MASK;
3546}
3547#define PPU_MISC_CTRL_BURST_LEN__MASK				0x0000000f
3548#define PPU_MISC_CTRL_BURST_LEN__SHIFT				0
3549static inline uint32_t PPU_MISC_CTRL_BURST_LEN(uint32_t val)
3550{
3551	return ((val) << PPU_MISC_CTRL_BURST_LEN__SHIFT) & PPU_MISC_CTRL_BURST_LEN__MASK;
3552}
3553
3554#define REG_PPU_RDMA_RDMA_S_STATUS				0x00007000
3555#define PPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK			0xfffc0000
3556#define PPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT		18
3557static inline uint32_t PPU_RDMA_RDMA_S_STATUS_RESERVED_0(uint32_t val)
3558{
3559	return ((val) << PPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK;
3560}
3561#define PPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK			0x00030000
3562#define PPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT			16
3563static inline uint32_t PPU_RDMA_RDMA_S_STATUS_STATUS_1(uint32_t val)
3564{
3565	return ((val) << PPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT) & PPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK;
3566}
3567#define PPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK			0x0000fffc
3568#define PPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT		2
3569static inline uint32_t PPU_RDMA_RDMA_S_STATUS_RESERVED_1(uint32_t val)
3570{
3571	return ((val) << PPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT) & PPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK;
3572}
3573#define PPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK			0x00000003
3574#define PPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT			0
3575static inline uint32_t PPU_RDMA_RDMA_S_STATUS_STATUS_0(uint32_t val)
3576{
3577	return ((val) << PPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT) & PPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK;
3578}
3579
3580#define REG_PPU_RDMA_RDMA_S_POINTER				0x00007004
3581#define PPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK		0xfffe0000
3582#define PPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT		17
3583static inline uint32_t PPU_RDMA_RDMA_S_POINTER_RESERVED_0(uint32_t val)
3584{
3585	return ((val) << PPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK;
3586}
3587#define PPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK			0x00010000
3588#define PPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT			16
3589static inline uint32_t PPU_RDMA_RDMA_S_POINTER_EXECUTER(uint32_t val)
3590{
3591	return ((val) << PPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT) & PPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK;
3592}
3593#define PPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK		0x0000ffc0
3594#define PPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT		6
3595static inline uint32_t PPU_RDMA_RDMA_S_POINTER_RESERVED_1(uint32_t val)
3596{
3597	return ((val) << PPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT) & PPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK;
3598}
3599#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK		0x00000020
3600#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT	5
3601static inline uint32_t PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
3602{
3603	return ((val) << PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK;
3604}
3605#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK		0x00000010
3606#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT		4
3607static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
3608{
3609	return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK;
3610}
3611#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK		0x00000008
3612#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT		3
3613static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE(uint32_t val)
3614{
3615	return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK;
3616}
3617#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK		0x00000004
3618#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT		2
3619static inline uint32_t PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN(uint32_t val)
3620{
3621	return ((val) << PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT) & PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK;
3622}
3623#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK		0x00000002
3624#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT		1
3625static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN(uint32_t val)
3626{
3627	return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK;
3628}
3629#define PPU_RDMA_RDMA_S_POINTER_POINTER__MASK			0x00000001
3630#define PPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT			0
3631static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER(uint32_t val)
3632{
3633	return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER__MASK;
3634}
3635
3636#define REG_PPU_RDMA_RDMA_OPERATION_ENABLE			0x00007008
3637#define PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK		0xfffffffe
3638#define PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT	1
3639static inline uint32_t PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0(uint32_t val)
3640{
3641	return ((val) << PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK;
3642}
3643#define PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK		0x00000001
3644#define PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT		0
3645static inline uint32_t PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN(uint32_t val)
3646{
3647	return ((val) << PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT) & PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK;
3648}
3649
3650#define REG_PPU_RDMA_RDMA_CUBE_IN_WIDTH				0x0000700c
3651#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__MASK		0xffffe000
3652#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__SHIFT		13
3653static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0(uint32_t val)
3654{
3655	return ((val) << PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__MASK;
3656}
3657#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK		0x00001fff
3658#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT	0
3659static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH(uint32_t val)
3660{
3661	return ((val) << PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK;
3662}
3663
3664#define REG_PPU_RDMA_RDMA_CUBE_IN_HEIGHT			0x00007010
3665#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__MASK		0xffffe000
3666#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT		13
3667static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0(uint32_t val)
3668{
3669	return ((val) << PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__MASK;
3670}
3671#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK	0x00001fff
3672#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT	0
3673static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT(uint32_t val)
3674{
3675	return ((val) << PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK;
3676}
3677
3678#define REG_PPU_RDMA_RDMA_CUBE_IN_CHANNEL			0x00007014
3679#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__MASK		0xffffe000
3680#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT		13
3681static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0(uint32_t val)
3682{
3683	return ((val) << PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__MASK;
3684}
3685#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK	0x00001fff
3686#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT	0
3687static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL(uint32_t val)
3688{
3689	return ((val) << PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK;
3690}
3691
3692#define REG_PPU_RDMA_RDMA_SRC_BASE_ADDR				0x0000701c
3693#define PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK		0xffffffff
3694#define PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT	0
3695static inline uint32_t PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR(uint32_t val)
3696{
3697	return ((val) << PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT) & PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK;
3698}
3699
3700#define REG_PPU_RDMA_RDMA_SRC_LINE_STRIDE			0x00007024
3701#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__MASK	0xfffffff0
3702#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__SHIFT	4
3703static inline uint32_t PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE(uint32_t val)
3704{
3705	return ((val) << PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__SHIFT) & PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__MASK;
3706}
3707#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__MASK		0x0000000f
3708#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__SHIFT		0
3709static inline uint32_t PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0(uint32_t val)
3710{
3711	return ((val) << PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__MASK;
3712}
3713
3714#define REG_PPU_RDMA_RDMA_SRC_SURF_STRIDE			0x00007028
3715#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__MASK	0xfffffff0
3716#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__SHIFT	4
3717static inline uint32_t PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE(uint32_t val)
3718{
3719	return ((val) << PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__SHIFT) & PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__MASK;
3720}
3721#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__MASK		0x0000000f
3722#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__SHIFT		0
3723static inline uint32_t PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0(uint32_t val)
3724{
3725	return ((val) << PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__MASK;
3726}
3727
3728#define REG_PPU_RDMA_RDMA_DATA_FORMAT				0x00007030
3729#define PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__MASK		0xfffffffc
3730#define PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__SHIFT		2
3731static inline uint32_t PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0(uint32_t val)
3732{
3733	return ((val) << PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__MASK;
3734}
3735#define PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__MASK		0x00000003
3736#define PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__SHIFT		0
3737static inline uint32_t PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION(uint32_t val)
3738{
3739	return ((val) << PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__SHIFT) & PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__MASK;
3740}
3741
3742#define REG_DDMA_CFG_OUTSTANDING				0x00008000
3743#define DDMA_CFG_OUTSTANDING_RESERVED_0__MASK			0xffff0000
3744#define DDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT			16
3745static inline uint32_t DDMA_CFG_OUTSTANDING_RESERVED_0(uint32_t val)
3746{
3747	return ((val) << DDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT) & DDMA_CFG_OUTSTANDING_RESERVED_0__MASK;
3748}
3749#define DDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK			0x0000ff00
3750#define DDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT			8
3751static inline uint32_t DDMA_CFG_OUTSTANDING_WR_OS_CNT(uint32_t val)
3752{
3753	return ((val) << DDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT) & DDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK;
3754}
3755#define DDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK			0x000000ff
3756#define DDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT			0
3757static inline uint32_t DDMA_CFG_OUTSTANDING_RD_OS_CNT(uint32_t val)
3758{
3759	return ((val) << DDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT) & DDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK;
3760}
3761
3762#define REG_DDMA_RD_WEIGHT_0					0x00008004
3763#define DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK			0xff000000
3764#define DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT			24
3765static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP(uint32_t val)
3766{
3767	return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK;
3768}
3769#define DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK			0x00ff0000
3770#define DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT			16
3771static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU(uint32_t val)
3772{
3773	return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK;
3774}
3775#define DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK			0x0000ff00
3776#define DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT		8
3777static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL(uint32_t val)
3778{
3779	return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK;
3780}
3781#define DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK		0x000000ff
3782#define DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT		0
3783static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE(uint32_t val)
3784{
3785	return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK;
3786}
3787
3788#define REG_DDMA_WR_WEIGHT_0					0x00008008
3789#define DDMA_WR_WEIGHT_0_RESERVED_0__MASK			0xffff0000
3790#define DDMA_WR_WEIGHT_0_RESERVED_0__SHIFT			16
3791static inline uint32_t DDMA_WR_WEIGHT_0_RESERVED_0(uint32_t val)
3792{
3793	return ((val) << DDMA_WR_WEIGHT_0_RESERVED_0__SHIFT) & DDMA_WR_WEIGHT_0_RESERVED_0__MASK;
3794}
3795#define DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK			0x0000ff00
3796#define DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT			8
3797static inline uint32_t DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP(uint32_t val)
3798{
3799	return ((val) << DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT) & DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK;
3800}
3801#define DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK			0x000000ff
3802#define DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT			0
3803static inline uint32_t DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU(uint32_t val)
3804{
3805	return ((val) << DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT) & DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK;
3806}
3807
3808#define REG_DDMA_CFG_ID_ERROR					0x0000800c
3809#define DDMA_CFG_ID_ERROR_RESERVED_0__MASK			0xfffffc00
3810#define DDMA_CFG_ID_ERROR_RESERVED_0__SHIFT			10
3811static inline uint32_t DDMA_CFG_ID_ERROR_RESERVED_0(uint32_t val)
3812{
3813	return ((val) << DDMA_CFG_ID_ERROR_RESERVED_0__SHIFT) & DDMA_CFG_ID_ERROR_RESERVED_0__MASK;
3814}
3815#define DDMA_CFG_ID_ERROR_WR_RESP_ID__MASK			0x000003c0
3816#define DDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT			6
3817static inline uint32_t DDMA_CFG_ID_ERROR_WR_RESP_ID(uint32_t val)
3818{
3819	return ((val) << DDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT) & DDMA_CFG_ID_ERROR_WR_RESP_ID__MASK;
3820}
3821#define DDMA_CFG_ID_ERROR_RESERVED_1__MASK			0x00000020
3822#define DDMA_CFG_ID_ERROR_RESERVED_1__SHIFT			5
3823static inline uint32_t DDMA_CFG_ID_ERROR_RESERVED_1(uint32_t val)
3824{
3825	return ((val) << DDMA_CFG_ID_ERROR_RESERVED_1__SHIFT) & DDMA_CFG_ID_ERROR_RESERVED_1__MASK;
3826}
3827#define DDMA_CFG_ID_ERROR_RD_RESP_ID__MASK			0x0000001f
3828#define DDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT			0
3829static inline uint32_t DDMA_CFG_ID_ERROR_RD_RESP_ID(uint32_t val)
3830{
3831	return ((val) << DDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT) & DDMA_CFG_ID_ERROR_RD_RESP_ID__MASK;
3832}
3833
3834#define REG_DDMA_RD_WEIGHT_1					0x00008010
3835#define DDMA_RD_WEIGHT_1_RESERVED_0__MASK			0xffffff00
3836#define DDMA_RD_WEIGHT_1_RESERVED_0__SHIFT			8
3837static inline uint32_t DDMA_RD_WEIGHT_1_RESERVED_0(uint32_t val)
3838{
3839	return ((val) << DDMA_RD_WEIGHT_1_RESERVED_0__SHIFT) & DDMA_RD_WEIGHT_1_RESERVED_0__MASK;
3840}
3841#define DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK			0x000000ff
3842#define DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT			0
3843static inline uint32_t DDMA_RD_WEIGHT_1_RD_WEIGHT_PC(uint32_t val)
3844{
3845	return ((val) << DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT) & DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK;
3846}
3847
3848#define REG_DDMA_CFG_DMA_FIFO_CLR				0x00008014
3849#define DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK			0xfffffffe
3850#define DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT			1
3851static inline uint32_t DDMA_CFG_DMA_FIFO_CLR_RESERVED_0(uint32_t val)
3852{
3853	return ((val) << DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT) & DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK;
3854}
3855#define DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK		0x00000001
3856#define DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT		0
3857static inline uint32_t DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR(uint32_t val)
3858{
3859	return ((val) << DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT) & DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK;
3860}
3861
3862#define REG_DDMA_CFG_DMA_ARB					0x00008018
3863#define DDMA_CFG_DMA_ARB_RESERVED_0__MASK			0xfffffc00
3864#define DDMA_CFG_DMA_ARB_RESERVED_0__SHIFT			10
3865static inline uint32_t DDMA_CFG_DMA_ARB_RESERVED_0(uint32_t val)
3866{
3867	return ((val) << DDMA_CFG_DMA_ARB_RESERVED_0__SHIFT) & DDMA_CFG_DMA_ARB_RESERVED_0__MASK;
3868}
3869#define DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK			0x00000200
3870#define DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT			9
3871static inline uint32_t DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL(uint32_t val)
3872{
3873	return ((val) << DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT) & DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK;
3874}
3875#define DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK			0x00000100
3876#define DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT			8
3877static inline uint32_t DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL(uint32_t val)
3878{
3879	return ((val) << DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT) & DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK;
3880}
3881#define DDMA_CFG_DMA_ARB_RESERVED_1__MASK			0x00000080
3882#define DDMA_CFG_DMA_ARB_RESERVED_1__SHIFT			7
3883static inline uint32_t DDMA_CFG_DMA_ARB_RESERVED_1(uint32_t val)
3884{
3885	return ((val) << DDMA_CFG_DMA_ARB_RESERVED_1__SHIFT) & DDMA_CFG_DMA_ARB_RESERVED_1__MASK;
3886}
3887#define DDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK			0x00000070
3888#define DDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT			4
3889static inline uint32_t DDMA_CFG_DMA_ARB_WR_FIX_ARB(uint32_t val)
3890{
3891	return ((val) << DDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT) & DDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK;
3892}
3893#define DDMA_CFG_DMA_ARB_RESERVED_2__MASK			0x00000008
3894#define DDMA_CFG_DMA_ARB_RESERVED_2__SHIFT			3
3895static inline uint32_t DDMA_CFG_DMA_ARB_RESERVED_2(uint32_t val)
3896{
3897	return ((val) << DDMA_CFG_DMA_ARB_RESERVED_2__SHIFT) & DDMA_CFG_DMA_ARB_RESERVED_2__MASK;
3898}
3899#define DDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK			0x00000007
3900#define DDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT			0
3901static inline uint32_t DDMA_CFG_DMA_ARB_RD_FIX_ARB(uint32_t val)
3902{
3903	return ((val) << DDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT) & DDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK;
3904}
3905
3906#define REG_DDMA_CFG_DMA_RD_QOS					0x00008020
3907#define DDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK			0xfffffc00
3908#define DDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT			10
3909static inline uint32_t DDMA_CFG_DMA_RD_QOS_RESERVED_0(uint32_t val)
3910{
3911	return ((val) << DDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT) & DDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK;
3912}
3913#define DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK			0x00000300
3914#define DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT			8
3915static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_PC_QOS(uint32_t val)
3916{
3917	return ((val) << DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK;
3918}
3919#define DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK			0x000000c0
3920#define DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT			6
3921static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS(uint32_t val)
3922{
3923	return ((val) << DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK;
3924}
3925#define DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK			0x00000030
3926#define DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT			4
3927static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS(uint32_t val)
3928{
3929	return ((val) << DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK;
3930}
3931#define DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK			0x0000000c
3932#define DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT		2
3933static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS(uint32_t val)
3934{
3935	return ((val) << DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK;
3936}
3937#define DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK		0x00000003
3938#define DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT		0
3939static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS(uint32_t val)
3940{
3941	return ((val) << DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK;
3942}
3943
3944#define REG_DDMA_CFG_DMA_RD_CFG					0x00008024
3945#define DDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK			0xffffe000
3946#define DDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT			13
3947static inline uint32_t DDMA_CFG_DMA_RD_CFG_RESERVED_0(uint32_t val)
3948{
3949	return ((val) << DDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT) & DDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK;
3950}
3951#define DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK			0x00001000
3952#define DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT			12
3953static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARLOCK(uint32_t val)
3954{
3955	return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK;
3956}
3957#define DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK			0x00000f00
3958#define DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT			8
3959static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARCACHE(uint32_t val)
3960{
3961	return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK;
3962}
3963#define DDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK			0x000000e0
3964#define DDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT			5
3965static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARPROT(uint32_t val)
3966{
3967	return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK;
3968}
3969#define DDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK			0x00000018
3970#define DDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT			3
3971static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARBURST(uint32_t val)
3972{
3973	return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK;
3974}
3975#define DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK			0x00000007
3976#define DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT			0
3977static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARSIZE(uint32_t val)
3978{
3979	return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK;
3980}
3981
3982#define REG_DDMA_CFG_DMA_WR_CFG					0x00008028
3983#define DDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK			0xffffe000
3984#define DDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT			13
3985static inline uint32_t DDMA_CFG_DMA_WR_CFG_RESERVED_0(uint32_t val)
3986{
3987	return ((val) << DDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT) & DDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK;
3988}
3989#define DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK			0x00001000
3990#define DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT			12
3991static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWLOCK(uint32_t val)
3992{
3993	return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK;
3994}
3995#define DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK			0x00000f00
3996#define DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT			8
3997static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWCACHE(uint32_t val)
3998{
3999	return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK;
4000}
4001#define DDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK			0x000000e0
4002#define DDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT			5
4003static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWPROT(uint32_t val)
4004{
4005	return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK;
4006}
4007#define DDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK			0x00000018
4008#define DDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT			3
4009static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWBURST(uint32_t val)
4010{
4011	return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK;
4012}
4013#define DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK			0x00000007
4014#define DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT			0
4015static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWSIZE(uint32_t val)
4016{
4017	return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK;
4018}
4019
4020#define REG_DDMA_CFG_DMA_WSTRB					0x0000802c
4021#define DDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK			0xffffffff
4022#define DDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT			0
4023static inline uint32_t DDMA_CFG_DMA_WSTRB_WR_WSTRB(uint32_t val)
4024{
4025	return ((val) << DDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT) & DDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK;
4026}
4027
4028#define REG_DDMA_CFG_STATUS					0x00008030
4029#define DDMA_CFG_STATUS_RESERVED_0__MASK			0xfffffe00
4030#define DDMA_CFG_STATUS_RESERVED_0__SHIFT			9
4031static inline uint32_t DDMA_CFG_STATUS_RESERVED_0(uint32_t val)
4032{
4033	return ((val) << DDMA_CFG_STATUS_RESERVED_0__SHIFT) & DDMA_CFG_STATUS_RESERVED_0__MASK;
4034}
4035#define DDMA_CFG_STATUS_IDEL__MASK				0x00000100
4036#define DDMA_CFG_STATUS_IDEL__SHIFT				8
4037static inline uint32_t DDMA_CFG_STATUS_IDEL(uint32_t val)
4038{
4039	return ((val) << DDMA_CFG_STATUS_IDEL__SHIFT) & DDMA_CFG_STATUS_IDEL__MASK;
4040}
4041#define DDMA_CFG_STATUS_RESERVED_1__MASK			0x000000ff
4042#define DDMA_CFG_STATUS_RESERVED_1__SHIFT			0
4043static inline uint32_t DDMA_CFG_STATUS_RESERVED_1(uint32_t val)
4044{
4045	return ((val) << DDMA_CFG_STATUS_RESERVED_1__SHIFT) & DDMA_CFG_STATUS_RESERVED_1__MASK;
4046}
4047
4048#define REG_SDMA_CFG_OUTSTANDING				0x00009000
4049#define SDMA_CFG_OUTSTANDING_RESERVED_0__MASK			0xffff0000
4050#define SDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT			16
4051static inline uint32_t SDMA_CFG_OUTSTANDING_RESERVED_0(uint32_t val)
4052{
4053	return ((val) << SDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT) & SDMA_CFG_OUTSTANDING_RESERVED_0__MASK;
4054}
4055#define SDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK			0x0000ff00
4056#define SDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT			8
4057static inline uint32_t SDMA_CFG_OUTSTANDING_WR_OS_CNT(uint32_t val)
4058{
4059	return ((val) << SDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT) & SDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK;
4060}
4061#define SDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK			0x000000ff
4062#define SDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT			0
4063static inline uint32_t SDMA_CFG_OUTSTANDING_RD_OS_CNT(uint32_t val)
4064{
4065	return ((val) << SDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT) & SDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK;
4066}
4067
4068#define REG_SDMA_RD_WEIGHT_0					0x00009004
4069#define SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK			0xff000000
4070#define SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT			24
4071static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP(uint32_t val)
4072{
4073	return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK;
4074}
4075#define SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK			0x00ff0000
4076#define SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT			16
4077static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU(uint32_t val)
4078{
4079	return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK;
4080}
4081#define SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK			0x0000ff00
4082#define SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT		8
4083static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL(uint32_t val)
4084{
4085	return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK;
4086}
4087#define SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK		0x000000ff
4088#define SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT		0
4089static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE(uint32_t val)
4090{
4091	return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK;
4092}
4093
4094#define REG_SDMA_WR_WEIGHT_0					0x00009008
4095#define SDMA_WR_WEIGHT_0_RESERVED_0__MASK			0xffff0000
4096#define SDMA_WR_WEIGHT_0_RESERVED_0__SHIFT			16
4097static inline uint32_t SDMA_WR_WEIGHT_0_RESERVED_0(uint32_t val)
4098{
4099	return ((val) << SDMA_WR_WEIGHT_0_RESERVED_0__SHIFT) & SDMA_WR_WEIGHT_0_RESERVED_0__MASK;
4100}
4101#define SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK			0x0000ff00
4102#define SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT			8
4103static inline uint32_t SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP(uint32_t val)
4104{
4105	return ((val) << SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT) & SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK;
4106}
4107#define SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK			0x000000ff
4108#define SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT			0
4109static inline uint32_t SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU(uint32_t val)
4110{
4111	return ((val) << SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT) & SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK;
4112}
4113
4114#define REG_SDMA_CFG_ID_ERROR					0x0000900c
4115#define SDMA_CFG_ID_ERROR_RESERVED_0__MASK			0xfffffc00
4116#define SDMA_CFG_ID_ERROR_RESERVED_0__SHIFT			10
4117static inline uint32_t SDMA_CFG_ID_ERROR_RESERVED_0(uint32_t val)
4118{
4119	return ((val) << SDMA_CFG_ID_ERROR_RESERVED_0__SHIFT) & SDMA_CFG_ID_ERROR_RESERVED_0__MASK;
4120}
4121#define SDMA_CFG_ID_ERROR_WR_RESP_ID__MASK			0x000003c0
4122#define SDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT			6
4123static inline uint32_t SDMA_CFG_ID_ERROR_WR_RESP_ID(uint32_t val)
4124{
4125	return ((val) << SDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT) & SDMA_CFG_ID_ERROR_WR_RESP_ID__MASK;
4126}
4127#define SDMA_CFG_ID_ERROR_RESERVED_1__MASK			0x00000020
4128#define SDMA_CFG_ID_ERROR_RESERVED_1__SHIFT			5
4129static inline uint32_t SDMA_CFG_ID_ERROR_RESERVED_1(uint32_t val)
4130{
4131	return ((val) << SDMA_CFG_ID_ERROR_RESERVED_1__SHIFT) & SDMA_CFG_ID_ERROR_RESERVED_1__MASK;
4132}
4133#define SDMA_CFG_ID_ERROR_RD_RESP_ID__MASK			0x0000001f
4134#define SDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT			0
4135static inline uint32_t SDMA_CFG_ID_ERROR_RD_RESP_ID(uint32_t val)
4136{
4137	return ((val) << SDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT) & SDMA_CFG_ID_ERROR_RD_RESP_ID__MASK;
4138}
4139
4140#define REG_SDMA_RD_WEIGHT_1					0x00009010
4141#define SDMA_RD_WEIGHT_1_RESERVED_0__MASK			0xffffff00
4142#define SDMA_RD_WEIGHT_1_RESERVED_0__SHIFT			8
4143static inline uint32_t SDMA_RD_WEIGHT_1_RESERVED_0(uint32_t val)
4144{
4145	return ((val) << SDMA_RD_WEIGHT_1_RESERVED_0__SHIFT) & SDMA_RD_WEIGHT_1_RESERVED_0__MASK;
4146}
4147#define SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK			0x000000ff
4148#define SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT			0
4149static inline uint32_t SDMA_RD_WEIGHT_1_RD_WEIGHT_PC(uint32_t val)
4150{
4151	return ((val) << SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT) & SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK;
4152}
4153
4154#define REG_SDMA_CFG_DMA_FIFO_CLR				0x00009014
4155#define SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK			0xfffffffe
4156#define SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT			1
4157static inline uint32_t SDMA_CFG_DMA_FIFO_CLR_RESERVED_0(uint32_t val)
4158{
4159	return ((val) << SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT) & SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK;
4160}
4161#define SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK		0x00000001
4162#define SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT		0
4163static inline uint32_t SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR(uint32_t val)
4164{
4165	return ((val) << SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT) & SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK;
4166}
4167
4168#define REG_SDMA_CFG_DMA_ARB					0x00009018
4169#define SDMA_CFG_DMA_ARB_RESERVED_0__MASK			0xfffffc00
4170#define SDMA_CFG_DMA_ARB_RESERVED_0__SHIFT			10
4171static inline uint32_t SDMA_CFG_DMA_ARB_RESERVED_0(uint32_t val)
4172{
4173	return ((val) << SDMA_CFG_DMA_ARB_RESERVED_0__SHIFT) & SDMA_CFG_DMA_ARB_RESERVED_0__MASK;
4174}
4175#define SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK			0x00000200
4176#define SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT			9
4177static inline uint32_t SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL(uint32_t val)
4178{
4179	return ((val) << SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT) & SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK;
4180}
4181#define SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK			0x00000100
4182#define SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT			8
4183static inline uint32_t SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL(uint32_t val)
4184{
4185	return ((val) << SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT) & SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK;
4186}
4187#define SDMA_CFG_DMA_ARB_RESERVED_1__MASK			0x00000080
4188#define SDMA_CFG_DMA_ARB_RESERVED_1__SHIFT			7
4189static inline uint32_t SDMA_CFG_DMA_ARB_RESERVED_1(uint32_t val)
4190{
4191	return ((val) << SDMA_CFG_DMA_ARB_RESERVED_1__SHIFT) & SDMA_CFG_DMA_ARB_RESERVED_1__MASK;
4192}
4193#define SDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK			0x00000070
4194#define SDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT			4
4195static inline uint32_t SDMA_CFG_DMA_ARB_WR_FIX_ARB(uint32_t val)
4196{
4197	return ((val) << SDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT) & SDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK;
4198}
4199#define SDMA_CFG_DMA_ARB_RESERVED_2__MASK			0x00000008
4200#define SDMA_CFG_DMA_ARB_RESERVED_2__SHIFT			3
4201static inline uint32_t SDMA_CFG_DMA_ARB_RESERVED_2(uint32_t val)
4202{
4203	return ((val) << SDMA_CFG_DMA_ARB_RESERVED_2__SHIFT) & SDMA_CFG_DMA_ARB_RESERVED_2__MASK;
4204}
4205#define SDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK			0x00000007
4206#define SDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT			0
4207static inline uint32_t SDMA_CFG_DMA_ARB_RD_FIX_ARB(uint32_t val)
4208{
4209	return ((val) << SDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT) & SDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK;
4210}
4211
4212#define REG_SDMA_CFG_DMA_RD_QOS					0x00009020
4213#define SDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK			0xfffffc00
4214#define SDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT			10
4215static inline uint32_t SDMA_CFG_DMA_RD_QOS_RESERVED_0(uint32_t val)
4216{
4217	return ((val) << SDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT) & SDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK;
4218}
4219#define SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK			0x00000300
4220#define SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT			8
4221static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_PC_QOS(uint32_t val)
4222{
4223	return ((val) << SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK;
4224}
4225#define SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK			0x000000c0
4226#define SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT			6
4227static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS(uint32_t val)
4228{
4229	return ((val) << SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK;
4230}
4231#define SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK			0x00000030
4232#define SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT			4
4233static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS(uint32_t val)
4234{
4235	return ((val) << SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK;
4236}
4237#define SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK			0x0000000c
4238#define SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT		2
4239static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS(uint32_t val)
4240{
4241	return ((val) << SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK;
4242}
4243#define SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK		0x00000003
4244#define SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT		0
4245static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS(uint32_t val)
4246{
4247	return ((val) << SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK;
4248}
4249
4250#define REG_SDMA_CFG_DMA_RD_CFG					0x00009024
4251#define SDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK			0xffffe000
4252#define SDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT			13
4253static inline uint32_t SDMA_CFG_DMA_RD_CFG_RESERVED_0(uint32_t val)
4254{
4255	return ((val) << SDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT) & SDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK;
4256}
4257#define SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK			0x00001000
4258#define SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT			12
4259static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARLOCK(uint32_t val)
4260{
4261	return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK;
4262}
4263#define SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK			0x00000f00
4264#define SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT			8
4265static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARCACHE(uint32_t val)
4266{
4267	return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK;
4268}
4269#define SDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK			0x000000e0
4270#define SDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT			5
4271static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARPROT(uint32_t val)
4272{
4273	return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK;
4274}
4275#define SDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK			0x00000018
4276#define SDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT			3
4277static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARBURST(uint32_t val)
4278{
4279	return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK;
4280}
4281#define SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK			0x00000007
4282#define SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT			0
4283static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARSIZE(uint32_t val)
4284{
4285	return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK;
4286}
4287
4288#define REG_SDMA_CFG_DMA_WR_CFG					0x00009028
4289#define SDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK			0xffffe000
4290#define SDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT			13
4291static inline uint32_t SDMA_CFG_DMA_WR_CFG_RESERVED_0(uint32_t val)
4292{
4293	return ((val) << SDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT) & SDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK;
4294}
4295#define SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK			0x00001000
4296#define SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT			12
4297static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWLOCK(uint32_t val)
4298{
4299	return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK;
4300}
4301#define SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK			0x00000f00
4302#define SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT			8
4303static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWCACHE(uint32_t val)
4304{
4305	return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK;
4306}
4307#define SDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK			0x000000e0
4308#define SDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT			5
4309static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWPROT(uint32_t val)
4310{
4311	return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK;
4312}
4313#define SDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK			0x00000018
4314#define SDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT			3
4315static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWBURST(uint32_t val)
4316{
4317	return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK;
4318}
4319#define SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK			0x00000007
4320#define SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT			0
4321static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWSIZE(uint32_t val)
4322{
4323	return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK;
4324}
4325
4326#define REG_SDMA_CFG_DMA_WSTRB					0x0000902c
4327#define SDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK			0xffffffff
4328#define SDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT			0
4329static inline uint32_t SDMA_CFG_DMA_WSTRB_WR_WSTRB(uint32_t val)
4330{
4331	return ((val) << SDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT) & SDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK;
4332}
4333
4334#define REG_SDMA_CFG_STATUS					0x00009030
4335#define SDMA_CFG_STATUS_RESERVED_0__MASK			0xfffffe00
4336#define SDMA_CFG_STATUS_RESERVED_0__SHIFT			9
4337static inline uint32_t SDMA_CFG_STATUS_RESERVED_0(uint32_t val)
4338{
4339	return ((val) << SDMA_CFG_STATUS_RESERVED_0__SHIFT) & SDMA_CFG_STATUS_RESERVED_0__MASK;
4340}
4341#define SDMA_CFG_STATUS_IDEL__MASK				0x00000100
4342#define SDMA_CFG_STATUS_IDEL__SHIFT				8
4343static inline uint32_t SDMA_CFG_STATUS_IDEL(uint32_t val)
4344{
4345	return ((val) << SDMA_CFG_STATUS_IDEL__SHIFT) & SDMA_CFG_STATUS_IDEL__MASK;
4346}
4347#define SDMA_CFG_STATUS_RESERVED_1__MASK			0x000000ff
4348#define SDMA_CFG_STATUS_RESERVED_1__SHIFT			0
4349static inline uint32_t SDMA_CFG_STATUS_RESERVED_1(uint32_t val)
4350{
4351	return ((val) << SDMA_CFG_STATUS_RESERVED_1__SHIFT) & SDMA_CFG_STATUS_RESERVED_1__MASK;
4352}
4353
4354#define REG_GLOBAL_OPERATION_ENABLE				0x0000f008
4355#define GLOBAL_OPERATION_ENABLE_RESERVED_0__MASK		0xffffff80
4356#define GLOBAL_OPERATION_ENABLE_RESERVED_0__SHIFT		7
4357static inline uint32_t GLOBAL_OPERATION_ENABLE_RESERVED_0(uint32_t val)
4358{
4359	return ((val) << GLOBAL_OPERATION_ENABLE_RESERVED_0__SHIFT) & GLOBAL_OPERATION_ENABLE_RESERVED_0__MASK;
4360}
4361#define GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__MASK		0x00000040
4362#define GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__SHIFT		6
4363static inline uint32_t GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN(uint32_t val)
4364{
4365	return ((val) << GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__MASK;
4366}
4367#define GLOBAL_OPERATION_ENABLE_PPU_OP_EN__MASK			0x00000020
4368#define GLOBAL_OPERATION_ENABLE_PPU_OP_EN__SHIFT		5
4369static inline uint32_t GLOBAL_OPERATION_ENABLE_PPU_OP_EN(uint32_t val)
4370{
4371	return ((val) << GLOBAL_OPERATION_ENABLE_PPU_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_PPU_OP_EN__MASK;
4372}
4373#define GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__MASK		0x00000010
4374#define GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__SHIFT		4
4375static inline uint32_t GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN(uint32_t val)
4376{
4377	return ((val) << GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__MASK;
4378}
4379#define GLOBAL_OPERATION_ENABLE_DPU_OP_EN__MASK			0x00000008
4380#define GLOBAL_OPERATION_ENABLE_DPU_OP_EN__SHIFT		3
4381static inline uint32_t GLOBAL_OPERATION_ENABLE_DPU_OP_EN(uint32_t val)
4382{
4383	return ((val) << GLOBAL_OPERATION_ENABLE_DPU_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_DPU_OP_EN__MASK;
4384}
4385#define GLOBAL_OPERATION_ENABLE_CORE_OP_EN__MASK		0x00000004
4386#define GLOBAL_OPERATION_ENABLE_CORE_OP_EN__SHIFT		2
4387static inline uint32_t GLOBAL_OPERATION_ENABLE_CORE_OP_EN(uint32_t val)
4388{
4389	return ((val) << GLOBAL_OPERATION_ENABLE_CORE_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_CORE_OP_EN__MASK;
4390}
4391#define GLOBAL_OPERATION_ENABLE_RESERVED_1__MASK		0x00000002
4392#define GLOBAL_OPERATION_ENABLE_RESERVED_1__SHIFT		1
4393static inline uint32_t GLOBAL_OPERATION_ENABLE_RESERVED_1(uint32_t val)
4394{
4395	return ((val) << GLOBAL_OPERATION_ENABLE_RESERVED_1__SHIFT) & GLOBAL_OPERATION_ENABLE_RESERVED_1__MASK;
4396}
4397#define GLOBAL_OPERATION_ENABLE_CNA_OP_EN__MASK			0x00000001
4398#define GLOBAL_OPERATION_ENABLE_CNA_OP_EN__SHIFT		0
4399static inline uint32_t GLOBAL_OPERATION_ENABLE_CNA_OP_EN(uint32_t val)
4400{
4401	return ((val) << GLOBAL_OPERATION_ENABLE_CNA_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_CNA_OP_EN__MASK;
4402}
4403
4404#endif /* __ROCKET_REGISTERS_XML__ */