tpc3_cmdq_regs.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2018 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_TPC3_CMDQ_REGS_H_
 14#define ASIC_REG_TPC3_CMDQ_REGS_H_
 15
 16/*
 17 *****************************************
 18 *   TPC3_CMDQ (Prototype: CMDQ)
 19 *****************************************
 20 */
 21
 22#define mmTPC3_CMDQ_GLBL_CFG0                                        0xEC9000
 23
 24#define mmTPC3_CMDQ_GLBL_CFG1                                        0xEC9004
 25
 26#define mmTPC3_CMDQ_GLBL_PROT                                        0xEC9008
 27
 28#define mmTPC3_CMDQ_GLBL_ERR_CFG                                     0xEC900C
 29
 30#define mmTPC3_CMDQ_GLBL_ERR_ADDR_LO                                 0xEC9010
 31
 32#define mmTPC3_CMDQ_GLBL_ERR_ADDR_HI                                 0xEC9014
 33
 34#define mmTPC3_CMDQ_GLBL_ERR_WDATA                                   0xEC9018
 35
 36#define mmTPC3_CMDQ_GLBL_SECURE_PROPS                                0xEC901C
 37
 38#define mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS                            0xEC9020
 39
 40#define mmTPC3_CMDQ_GLBL_STS0                                        0xEC9024
 41
 42#define mmTPC3_CMDQ_GLBL_STS1                                        0xEC9028
 43
 44#define mmTPC3_CMDQ_CQ_CFG0                                          0xEC90B0
 45
 46#define mmTPC3_CMDQ_CQ_CFG1                                          0xEC90B4
 47
 48#define mmTPC3_CMDQ_CQ_ARUSER                                        0xEC90B8
 49
 50#define mmTPC3_CMDQ_CQ_PTR_LO                                        0xEC90C0
 51
 52#define mmTPC3_CMDQ_CQ_PTR_HI                                        0xEC90C4
 53
 54#define mmTPC3_CMDQ_CQ_TSIZE                                         0xEC90C8
 55
 56#define mmTPC3_CMDQ_CQ_CTL                                           0xEC90CC
 57
 58#define mmTPC3_CMDQ_CQ_PTR_LO_STS                                    0xEC90D4
 59
 60#define mmTPC3_CMDQ_CQ_PTR_HI_STS                                    0xEC90D8
 61
 62#define mmTPC3_CMDQ_CQ_TSIZE_STS                                     0xEC90DC
 63
 64#define mmTPC3_CMDQ_CQ_CTL_STS                                       0xEC90E0
 65
 66#define mmTPC3_CMDQ_CQ_STS0                                          0xEC90E4
 67
 68#define mmTPC3_CMDQ_CQ_STS1                                          0xEC90E8
 69
 70#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_EN                                0xEC90F0
 71
 72#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN                         0xEC90F4
 73
 74#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_SAT                               0xEC90F8
 75
 76#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_TOUT                              0xEC90FC
 77
 78#define mmTPC3_CMDQ_CQ_IFIFO_CNT                                     0xEC9108
 79
 80#define mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_LO                             0xEC9120
 81
 82#define mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_HI                             0xEC9124
 83
 84#define mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_LO                             0xEC9128
 85
 86#define mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_HI                             0xEC912C
 87
 88#define mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_LO                             0xEC9130
 89
 90#define mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_HI                             0xEC9134
 91
 92#define mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_LO                             0xEC9138
 93
 94#define mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_HI                             0xEC913C
 95
 96#define mmTPC3_CMDQ_CP_LDMA_TSIZE_OFFSET                             0xEC9140
 97
 98#define mmTPC3_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET                       0xEC9144
 99
100#define mmTPC3_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET                       0xEC9148
101
102#define mmTPC3_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET                       0xEC914C
103
104#define mmTPC3_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET                       0xEC9150
105
106#define mmTPC3_CMDQ_CP_LDMA_COMMIT_OFFSET                            0xEC9154
107
108#define mmTPC3_CMDQ_CP_FENCE0_RDATA                                  0xEC9158
109
110#define mmTPC3_CMDQ_CP_FENCE1_RDATA                                  0xEC915C
111
112#define mmTPC3_CMDQ_CP_FENCE2_RDATA                                  0xEC9160
113
114#define mmTPC3_CMDQ_CP_FENCE3_RDATA                                  0xEC9164
115
116#define mmTPC3_CMDQ_CP_FENCE0_CNT                                    0xEC9168
117
118#define mmTPC3_CMDQ_CP_FENCE1_CNT                                    0xEC916C
119
120#define mmTPC3_CMDQ_CP_FENCE2_CNT                                    0xEC9170
121
122#define mmTPC3_CMDQ_CP_FENCE3_CNT                                    0xEC9174
123
124#define mmTPC3_CMDQ_CP_STS                                           0xEC9178
125
126#define mmTPC3_CMDQ_CP_CURRENT_INST_LO                               0xEC917C
127
128#define mmTPC3_CMDQ_CP_CURRENT_INST_HI                               0xEC9180
129
130#define mmTPC3_CMDQ_CP_BARRIER_CFG                                   0xEC9184
131
132#define mmTPC3_CMDQ_CP_DBG_0                                         0xEC9188
133
134#define mmTPC3_CMDQ_CQ_BUF_ADDR                                      0xEC9308
135
136#define mmTPC3_CMDQ_CQ_BUF_RDATA                                     0xEC930C
137
138#endif /* ASIC_REG_TPC3_CMDQ_REGS_H_ */