tpc1_qm_regs.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2018 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_TPC1_QM_REGS_H_
 14#define ASIC_REG_TPC1_QM_REGS_H_
 15
 16/*
 17 *****************************************
 18 *   TPC1_QM (Prototype: QMAN)
 19 *****************************************
 20 */
 21
 22#define mmTPC1_QM_GLBL_CFG0                                          0xE48000
 23
 24#define mmTPC1_QM_GLBL_CFG1                                          0xE48004
 25
 26#define mmTPC1_QM_GLBL_PROT                                          0xE48008
 27
 28#define mmTPC1_QM_GLBL_ERR_CFG                                       0xE4800C
 29
 30#define mmTPC1_QM_GLBL_ERR_ADDR_LO                                   0xE48010
 31
 32#define mmTPC1_QM_GLBL_ERR_ADDR_HI                                   0xE48014
 33
 34#define mmTPC1_QM_GLBL_ERR_WDATA                                     0xE48018
 35
 36#define mmTPC1_QM_GLBL_SECURE_PROPS                                  0xE4801C
 37
 38#define mmTPC1_QM_GLBL_NON_SECURE_PROPS                              0xE48020
 39
 40#define mmTPC1_QM_GLBL_STS0                                          0xE48024
 41
 42#define mmTPC1_QM_GLBL_STS1                                          0xE48028
 43
 44#define mmTPC1_QM_PQ_BASE_LO                                         0xE48060
 45
 46#define mmTPC1_QM_PQ_BASE_HI                                         0xE48064
 47
 48#define mmTPC1_QM_PQ_SIZE                                            0xE48068
 49
 50#define mmTPC1_QM_PQ_PI                                              0xE4806C
 51
 52#define mmTPC1_QM_PQ_CI                                              0xE48070
 53
 54#define mmTPC1_QM_PQ_CFG0                                            0xE48074
 55
 56#define mmTPC1_QM_PQ_CFG1                                            0xE48078
 57
 58#define mmTPC1_QM_PQ_ARUSER                                          0xE4807C
 59
 60#define mmTPC1_QM_PQ_PUSH0                                           0xE48080
 61
 62#define mmTPC1_QM_PQ_PUSH1                                           0xE48084
 63
 64#define mmTPC1_QM_PQ_PUSH2                                           0xE48088
 65
 66#define mmTPC1_QM_PQ_PUSH3                                           0xE4808C
 67
 68#define mmTPC1_QM_PQ_STS0                                            0xE48090
 69
 70#define mmTPC1_QM_PQ_STS1                                            0xE48094
 71
 72#define mmTPC1_QM_PQ_RD_RATE_LIM_EN                                  0xE480A0
 73
 74#define mmTPC1_QM_PQ_RD_RATE_LIM_RST_TOKEN                           0xE480A4
 75
 76#define mmTPC1_QM_PQ_RD_RATE_LIM_SAT                                 0xE480A8
 77
 78#define mmTPC1_QM_PQ_RD_RATE_LIM_TOUT                                0xE480AC
 79
 80#define mmTPC1_QM_CQ_CFG0                                            0xE480B0
 81
 82#define mmTPC1_QM_CQ_CFG1                                            0xE480B4
 83
 84#define mmTPC1_QM_CQ_ARUSER                                          0xE480B8
 85
 86#define mmTPC1_QM_CQ_PTR_LO                                          0xE480C0
 87
 88#define mmTPC1_QM_CQ_PTR_HI                                          0xE480C4
 89
 90#define mmTPC1_QM_CQ_TSIZE                                           0xE480C8
 91
 92#define mmTPC1_QM_CQ_CTL                                             0xE480CC
 93
 94#define mmTPC1_QM_CQ_PTR_LO_STS                                      0xE480D4
 95
 96#define mmTPC1_QM_CQ_PTR_HI_STS                                      0xE480D8
 97
 98#define mmTPC1_QM_CQ_TSIZE_STS                                       0xE480DC
 99
100#define mmTPC1_QM_CQ_CTL_STS                                         0xE480E0
101
102#define mmTPC1_QM_CQ_STS0                                            0xE480E4
103
104#define mmTPC1_QM_CQ_STS1                                            0xE480E8
105
106#define mmTPC1_QM_CQ_RD_RATE_LIM_EN                                  0xE480F0
107
108#define mmTPC1_QM_CQ_RD_RATE_LIM_RST_TOKEN                           0xE480F4
109
110#define mmTPC1_QM_CQ_RD_RATE_LIM_SAT                                 0xE480F8
111
112#define mmTPC1_QM_CQ_RD_RATE_LIM_TOUT                                0xE480FC
113
114#define mmTPC1_QM_CQ_IFIFO_CNT                                       0xE48108
115
116#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO                               0xE48120
117
118#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI                               0xE48124
119
120#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO                               0xE48128
121
122#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI                               0xE4812C
123
124#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO                               0xE48130
125
126#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI                               0xE48134
127
128#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO                               0xE48138
129
130#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI                               0xE4813C
131
132#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET                               0xE48140
133
134#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET                         0xE48144
135
136#define mmTPC1_QM_CP_LDMA_SRC_BASE_HI_OFFSET                         0xE48148
137
138#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET                         0xE4814C
139
140#define mmTPC1_QM_CP_LDMA_DST_BASE_HI_OFFSET                         0xE48150
141
142#define mmTPC1_QM_CP_LDMA_COMMIT_OFFSET                              0xE48154
143
144#define mmTPC1_QM_CP_FENCE0_RDATA                                    0xE48158
145
146#define mmTPC1_QM_CP_FENCE1_RDATA                                    0xE4815C
147
148#define mmTPC1_QM_CP_FENCE2_RDATA                                    0xE48160
149
150#define mmTPC1_QM_CP_FENCE3_RDATA                                    0xE48164
151
152#define mmTPC1_QM_CP_FENCE0_CNT                                      0xE48168
153
154#define mmTPC1_QM_CP_FENCE1_CNT                                      0xE4816C
155
156#define mmTPC1_QM_CP_FENCE2_CNT                                      0xE48170
157
158#define mmTPC1_QM_CP_FENCE3_CNT                                      0xE48174
159
160#define mmTPC1_QM_CP_STS                                             0xE48178
161
162#define mmTPC1_QM_CP_CURRENT_INST_LO                                 0xE4817C
163
164#define mmTPC1_QM_CP_CURRENT_INST_HI                                 0xE48180
165
166#define mmTPC1_QM_CP_BARRIER_CFG                                     0xE48184
167
168#define mmTPC1_QM_CP_DBG_0                                           0xE48188
169
170#define mmTPC1_QM_PQ_BUF_ADDR                                        0xE48300
171
172#define mmTPC1_QM_PQ_BUF_RDATA                                       0xE48304
173
174#define mmTPC1_QM_CQ_BUF_ADDR                                        0xE48308
175
176#define mmTPC1_QM_CQ_BUF_RDATA                                       0xE4830C
177
178#endif /* ASIC_REG_TPC1_QM_REGS_H_ */