FILE
tpc0_qm_masks.h
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linux-6.19.14/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_TPC0_QM_MASKS_H_ 14#define ASIC_REG_TPC0_QM_MASKS_H_ 15 16/* 17 ***************************************** 18 * TPC0_QM (Prototype: QMAN) 19 ***************************************** 20 */ 21 22/* TPC0_QM_GLBL_CFG0 */ 23#define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 24#define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0x1 25#define TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT 1 26#define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x2 27#define TPC0_QM_GLBL_CFG0_CP_EN_SHIFT 2 28#define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x4 29#define TPC0_QM_GLBL_CFG0_DMA_EN_SHIFT 3 30#define TPC0_QM_GLBL_CFG0_DMA_EN_MASK 0x8 31 32/* TPC0_QM_GLBL_CFG1 */ 33#define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 34#define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0x1 35#define TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT 1 36#define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x2 37#define TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT 2 38#define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x4 39#define TPC0_QM_GLBL_CFG1_DMA_STOP_SHIFT 3 40#define TPC0_QM_GLBL_CFG1_DMA_STOP_MASK 0x8 41#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 8 42#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0x100 43#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 9 44#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x200 45#define TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 10 46#define TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x400 47#define TPC0_QM_GLBL_CFG1_DMA_FLUSH_SHIFT 11 48#define TPC0_QM_GLBL_CFG1_DMA_FLUSH_MASK 0x800 49 50/* TPC0_QM_GLBL_PROT */ 51#define TPC0_QM_GLBL_PROT_PQF_PROT_SHIFT 0 52#define TPC0_QM_GLBL_PROT_PQF_PROT_MASK 0x1 53#define TPC0_QM_GLBL_PROT_CQF_PROT_SHIFT 1 54#define TPC0_QM_GLBL_PROT_CQF_PROT_MASK 0x2 55#define TPC0_QM_GLBL_PROT_CP_PROT_SHIFT 2 56#define TPC0_QM_GLBL_PROT_CP_PROT_MASK 0x4 57#define TPC0_QM_GLBL_PROT_DMA_PROT_SHIFT 3 58#define TPC0_QM_GLBL_PROT_DMA_PROT_MASK 0x8 59#define TPC0_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT 4 60#define TPC0_QM_GLBL_PROT_PQF_ERR_PROT_MASK 0x10 61#define TPC0_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT 5 62#define TPC0_QM_GLBL_PROT_CQF_ERR_PROT_MASK 0x20 63#define TPC0_QM_GLBL_PROT_CP_ERR_PROT_SHIFT 6 64#define TPC0_QM_GLBL_PROT_CP_ERR_PROT_MASK 0x40 65#define TPC0_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT 7 66#define TPC0_QM_GLBL_PROT_DMA_ERR_PROT_MASK 0x80 67 68/* TPC0_QM_GLBL_ERR_CFG */ 69#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0 70#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1 71#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1 72#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2 73#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2 74#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4 75#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3 76#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8 77#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 78#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10 79#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5 80#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20 81#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6 82#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40 83#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7 84#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80 85#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8 86#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100 87#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9 88#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200 89#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10 90#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400 91#define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11 92#define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800 93 94/* TPC0_QM_GLBL_ERR_ADDR_LO */ 95#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 96#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF 97 98/* TPC0_QM_GLBL_ERR_ADDR_HI */ 99#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 100#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF 101 102/* TPC0_QM_GLBL_ERR_WDATA */ 103#define TPC0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 104#define TPC0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF 105 106/* TPC0_QM_GLBL_SECURE_PROPS */ 107#define TPC0_QM_GLBL_SECURE_PROPS_ASID_SHIFT 0 108#define TPC0_QM_GLBL_SECURE_PROPS_ASID_MASK 0x3FF 109#define TPC0_QM_GLBL_SECURE_PROPS_MMBP_SHIFT 10 110#define TPC0_QM_GLBL_SECURE_PROPS_MMBP_MASK 0x400 111 112/* TPC0_QM_GLBL_NON_SECURE_PROPS */ 113#define TPC0_QM_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0 114#define TPC0_QM_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF 115#define TPC0_QM_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10 116#define TPC0_QM_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400 117 118/* TPC0_QM_GLBL_STS0 */ 119#define TPC0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 120#define TPC0_QM_GLBL_STS0_PQF_IDLE_MASK 0x1 121#define TPC0_QM_GLBL_STS0_CQF_IDLE_SHIFT 1 122#define TPC0_QM_GLBL_STS0_CQF_IDLE_MASK 0x2 123#define TPC0_QM_GLBL_STS0_CP_IDLE_SHIFT 2 124#define TPC0_QM_GLBL_STS0_CP_IDLE_MASK 0x4 125#define TPC0_QM_GLBL_STS0_DMA_IDLE_SHIFT 3 126#define TPC0_QM_GLBL_STS0_DMA_IDLE_MASK 0x8 127#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 4 128#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0x10 129#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 5 130#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x20 131#define TPC0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 6 132#define TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x40 133#define TPC0_QM_GLBL_STS0_DMA_IS_STOP_SHIFT 7 134#define TPC0_QM_GLBL_STS0_DMA_IS_STOP_MASK 0x80 135 136/* TPC0_QM_GLBL_STS1 */ 137#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 138#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 139#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 140#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 141#define TPC0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 142#define TPC0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 143#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 144#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 145#define TPC0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 146#define TPC0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 147#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 148#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 149#define TPC0_QM_GLBL_STS1_DMA_RD_ERR_SHIFT 8 150#define TPC0_QM_GLBL_STS1_DMA_RD_ERR_MASK 0x100 151#define TPC0_QM_GLBL_STS1_DMA_WR_ERR_SHIFT 9 152#define TPC0_QM_GLBL_STS1_DMA_WR_ERR_MASK 0x200 153#define TPC0_QM_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10 154#define TPC0_QM_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400 155#define TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11 156#define TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800 157 158/* TPC0_QM_PQ_BASE_LO */ 159#define TPC0_QM_PQ_BASE_LO_VAL_SHIFT 0 160#define TPC0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF 161 162/* TPC0_QM_PQ_BASE_HI */ 163#define TPC0_QM_PQ_BASE_HI_VAL_SHIFT 0 164#define TPC0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF 165 166/* TPC0_QM_PQ_SIZE */ 167#define TPC0_QM_PQ_SIZE_VAL_SHIFT 0 168#define TPC0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF 169 170/* TPC0_QM_PQ_PI */ 171#define TPC0_QM_PQ_PI_VAL_SHIFT 0 172#define TPC0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF 173 174/* TPC0_QM_PQ_CI */ 175#define TPC0_QM_PQ_CI_VAL_SHIFT 0 176#define TPC0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF 177 178/* TPC0_QM_PQ_CFG0 */ 179#define TPC0_QM_PQ_CFG0_RESERVED_SHIFT 0 180#define TPC0_QM_PQ_CFG0_RESERVED_MASK 0x1 181 182/* TPC0_QM_PQ_CFG1 */ 183#define TPC0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 184#define TPC0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF 185#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 186#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 187 188/* TPC0_QM_PQ_ARUSER */ 189#define TPC0_QM_PQ_ARUSER_NOSNOOP_SHIFT 0 190#define TPC0_QM_PQ_ARUSER_NOSNOOP_MASK 0x1 191#define TPC0_QM_PQ_ARUSER_WORD_SHIFT 1 192#define TPC0_QM_PQ_ARUSER_WORD_MASK 0x2 193 194/* TPC0_QM_PQ_PUSH0 */ 195#define TPC0_QM_PQ_PUSH0_PTR_LO_SHIFT 0 196#define TPC0_QM_PQ_PUSH0_PTR_LO_MASK 0xFFFFFFFF 197 198/* TPC0_QM_PQ_PUSH1 */ 199#define TPC0_QM_PQ_PUSH1_PTR_HI_SHIFT 0 200#define TPC0_QM_PQ_PUSH1_PTR_HI_MASK 0xFFFFFFFF 201 202/* TPC0_QM_PQ_PUSH2 */ 203#define TPC0_QM_PQ_PUSH2_TSIZE_SHIFT 0 204#define TPC0_QM_PQ_PUSH2_TSIZE_MASK 0xFFFFFFFF 205 206/* TPC0_QM_PQ_PUSH3 */ 207#define TPC0_QM_PQ_PUSH3_RPT_SHIFT 0 208#define TPC0_QM_PQ_PUSH3_RPT_MASK 0xFFFF 209#define TPC0_QM_PQ_PUSH3_CTL_SHIFT 16 210#define TPC0_QM_PQ_PUSH3_CTL_MASK 0xFFFF0000 211 212/* TPC0_QM_PQ_STS0 */ 213#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 214#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF 215#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 216#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 217 218/* TPC0_QM_PQ_STS1 */ 219#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 220#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF 221#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 222#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 223#define TPC0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 224#define TPC0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 225 226/* TPC0_QM_PQ_RD_RATE_LIM_EN */ 227#define TPC0_QM_PQ_RD_RATE_LIM_EN_VAL_SHIFT 0 228#define TPC0_QM_PQ_RD_RATE_LIM_EN_VAL_MASK 0x1 229 230/* TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN */ 231#define TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 232#define TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF 233 234/* TPC0_QM_PQ_RD_RATE_LIM_SAT */ 235#define TPC0_QM_PQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 236#define TPC0_QM_PQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF 237 238/* TPC0_QM_PQ_RD_RATE_LIM_TOUT */ 239#define TPC0_QM_PQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 240#define TPC0_QM_PQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF 241 242/* TPC0_QM_CQ_CFG0 */ 243#define TPC0_QM_CQ_CFG0_RESERVED_SHIFT 0 244#define TPC0_QM_CQ_CFG0_RESERVED_MASK 0x1 245 246/* TPC0_QM_CQ_CFG1 */ 247#define TPC0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 248#define TPC0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF 249#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 250#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 251 252/* TPC0_QM_CQ_ARUSER */ 253#define TPC0_QM_CQ_ARUSER_NOSNOOP_SHIFT 0 254#define TPC0_QM_CQ_ARUSER_NOSNOOP_MASK 0x1 255#define TPC0_QM_CQ_ARUSER_WORD_SHIFT 1 256#define TPC0_QM_CQ_ARUSER_WORD_MASK 0x2 257 258/* TPC0_QM_CQ_PTR_LO */ 259#define TPC0_QM_CQ_PTR_LO_VAL_SHIFT 0 260#define TPC0_QM_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF 261 262/* TPC0_QM_CQ_PTR_HI */ 263#define TPC0_QM_CQ_PTR_HI_VAL_SHIFT 0 264#define TPC0_QM_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF 265 266/* TPC0_QM_CQ_TSIZE */ 267#define TPC0_QM_CQ_TSIZE_VAL_SHIFT 0 268#define TPC0_QM_CQ_TSIZE_VAL_MASK 0xFFFFFFFF 269 270/* TPC0_QM_CQ_CTL */ 271#define TPC0_QM_CQ_CTL_RPT_SHIFT 0 272#define TPC0_QM_CQ_CTL_RPT_MASK 0xFFFF 273#define TPC0_QM_CQ_CTL_CTL_SHIFT 16 274#define TPC0_QM_CQ_CTL_CTL_MASK 0xFFFF0000 275 276/* TPC0_QM_CQ_PTR_LO_STS */ 277#define TPC0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 278#define TPC0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF 279 280/* TPC0_QM_CQ_PTR_HI_STS */ 281#define TPC0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 282#define TPC0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF 283 284/* TPC0_QM_CQ_TSIZE_STS */ 285#define TPC0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 286#define TPC0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF 287 288/* TPC0_QM_CQ_CTL_STS */ 289#define TPC0_QM_CQ_CTL_STS_RPT_SHIFT 0 290#define TPC0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF 291#define TPC0_QM_CQ_CTL_STS_CTL_SHIFT 16 292#define TPC0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 293 294/* TPC0_QM_CQ_STS0 */ 295#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 296#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF 297#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 298#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 299 300/* TPC0_QM_CQ_STS1 */ 301#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 302#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF 303#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 304#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 305#define TPC0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 306#define TPC0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 307 308/* TPC0_QM_CQ_RD_RATE_LIM_EN */ 309#define TPC0_QM_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0 310#define TPC0_QM_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1 311 312/* TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN */ 313#define TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 314#define TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF 315 316/* TPC0_QM_CQ_RD_RATE_LIM_SAT */ 317#define TPC0_QM_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 318#define TPC0_QM_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF 319 320/* TPC0_QM_CQ_RD_RATE_LIM_TOUT */ 321#define TPC0_QM_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 322#define TPC0_QM_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF 323 324/* TPC0_QM_CQ_IFIFO_CNT */ 325#define TPC0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 326#define TPC0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 327 328/* TPC0_QM_CP_MSG_BASE0_ADDR_LO */ 329#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 330#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF 331 332/* TPC0_QM_CP_MSG_BASE0_ADDR_HI */ 333#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 334#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF 335 336/* TPC0_QM_CP_MSG_BASE1_ADDR_LO */ 337#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 338#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF 339 340/* TPC0_QM_CP_MSG_BASE1_ADDR_HI */ 341#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 342#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF 343 344/* TPC0_QM_CP_MSG_BASE2_ADDR_LO */ 345#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 346#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF 347 348/* TPC0_QM_CP_MSG_BASE2_ADDR_HI */ 349#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 350#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF 351 352/* TPC0_QM_CP_MSG_BASE3_ADDR_LO */ 353#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 354#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF 355 356/* TPC0_QM_CP_MSG_BASE3_ADDR_HI */ 357#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 358#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF 359 360/* TPC0_QM_CP_LDMA_TSIZE_OFFSET */ 361#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 362#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF 363 364/* TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ 365#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 366#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF 367 368/* TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET */ 369#define TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0 370#define TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF 371 372/* TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ 373#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 374#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF 375 376/* TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET */ 377#define TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0 378#define TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF 379 380/* TPC0_QM_CP_LDMA_COMMIT_OFFSET */ 381#define TPC0_QM_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0 382#define TPC0_QM_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF 383 384/* TPC0_QM_CP_FENCE0_RDATA */ 385#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 386#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF 387 388/* TPC0_QM_CP_FENCE1_RDATA */ 389#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 390#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF 391 392/* TPC0_QM_CP_FENCE2_RDATA */ 393#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 394#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF 395 396/* TPC0_QM_CP_FENCE3_RDATA */ 397#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 398#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF 399 400/* TPC0_QM_CP_FENCE0_CNT */ 401#define TPC0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 402#define TPC0_QM_CP_FENCE0_CNT_VAL_MASK 0xFF 403 404/* TPC0_QM_CP_FENCE1_CNT */ 405#define TPC0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 406#define TPC0_QM_CP_FENCE1_CNT_VAL_MASK 0xFF 407 408/* TPC0_QM_CP_FENCE2_CNT */ 409#define TPC0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 410#define TPC0_QM_CP_FENCE2_CNT_VAL_MASK 0xFF 411 412/* TPC0_QM_CP_FENCE3_CNT */ 413#define TPC0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 414#define TPC0_QM_CP_FENCE3_CNT_VAL_MASK 0xFF 415 416/* TPC0_QM_CP_STS */ 417#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 418#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF 419#define TPC0_QM_CP_STS_ERDY_SHIFT 16 420#define TPC0_QM_CP_STS_ERDY_MASK 0x10000 421#define TPC0_QM_CP_STS_RRDY_SHIFT 17 422#define TPC0_QM_CP_STS_RRDY_MASK 0x20000 423#define TPC0_QM_CP_STS_MRDY_SHIFT 18 424#define TPC0_QM_CP_STS_MRDY_MASK 0x40000 425#define TPC0_QM_CP_STS_SW_STOP_SHIFT 19 426#define TPC0_QM_CP_STS_SW_STOP_MASK 0x80000 427#define TPC0_QM_CP_STS_FENCE_ID_SHIFT 20 428#define TPC0_QM_CP_STS_FENCE_ID_MASK 0x300000 429#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 430#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 431 432/* TPC0_QM_CP_CURRENT_INST_LO */ 433#define TPC0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 434#define TPC0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF 435 436/* TPC0_QM_CP_CURRENT_INST_HI */ 437#define TPC0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 438#define TPC0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF 439 440/* TPC0_QM_CP_BARRIER_CFG */ 441#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 442#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF 443 444/* TPC0_QM_CP_DBG_0 */ 445#define TPC0_QM_CP_DBG_0_VAL_SHIFT 0 446#define TPC0_QM_CP_DBG_0_VAL_MASK 0xFF 447 448/* TPC0_QM_PQ_BUF_ADDR */ 449#define TPC0_QM_PQ_BUF_ADDR_VAL_SHIFT 0 450#define TPC0_QM_PQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF 451 452/* TPC0_QM_PQ_BUF_RDATA */ 453#define TPC0_QM_PQ_BUF_RDATA_VAL_SHIFT 0 454#define TPC0_QM_PQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF 455 456/* TPC0_QM_CQ_BUF_ADDR */ 457#define TPC0_QM_CQ_BUF_ADDR_VAL_SHIFT 0 458#define TPC0_QM_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF 459 460/* TPC0_QM_CQ_BUF_RDATA */ 461#define TPC0_QM_CQ_BUF_RDATA_VAL_SHIFT 0 462#define TPC0_QM_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF 463 464#endif /* ASIC_REG_TPC0_QM_MASKS_H_ */
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