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mme5_rtr_regs.h
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linux-6.19.14/drivers/accel/habanalabs/include/goya/asic_reg/mme5_rtr_regs.h
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_MME5_RTR_REGS_H_ 14#define ASIC_REG_MME5_RTR_REGS_H_ 15 16/* 17 ***************************************** 18 * MME5_RTR (Prototype: MME_RTR) 19 ***************************************** 20 */ 21 22#define mmMME5_RTR_HBW_RD_RQ_E_ARB 0x140100 23 24#define mmMME5_RTR_HBW_RD_RQ_W_ARB 0x140104 25 26#define mmMME5_RTR_HBW_RD_RQ_N_ARB 0x140108 27 28#define mmMME5_RTR_HBW_RD_RQ_S_ARB 0x14010C 29 30#define mmMME5_RTR_HBW_RD_RQ_L_ARB 0x140110 31 32#define mmMME5_RTR_HBW_E_ARB_MAX 0x140120 33 34#define mmMME5_RTR_HBW_W_ARB_MAX 0x140124 35 36#define mmMME5_RTR_HBW_N_ARB_MAX 0x140128 37 38#define mmMME5_RTR_HBW_S_ARB_MAX 0x14012C 39 40#define mmMME5_RTR_HBW_L_ARB_MAX 0x140130 41 42#define mmMME5_RTR_HBW_RD_RS_MAX_CREDIT 0x140140 43 44#define mmMME5_RTR_HBW_WR_RQ_MAX_CREDIT 0x140144 45 46#define mmMME5_RTR_HBW_RD_RQ_MAX_CREDIT 0x140148 47 48#define mmMME5_RTR_HBW_RD_RS_E_ARB 0x140150 49 50#define mmMME5_RTR_HBW_RD_RS_W_ARB 0x140154 51 52#define mmMME5_RTR_HBW_RD_RS_N_ARB 0x140158 53 54#define mmMME5_RTR_HBW_RD_RS_S_ARB 0x14015C 55 56#define mmMME5_RTR_HBW_RD_RS_L_ARB 0x140160 57 58#define mmMME5_RTR_HBW_WR_RQ_E_ARB 0x140170 59 60#define mmMME5_RTR_HBW_WR_RQ_W_ARB 0x140174 61 62#define mmMME5_RTR_HBW_WR_RQ_N_ARB 0x140178 63 64#define mmMME5_RTR_HBW_WR_RQ_S_ARB 0x14017C 65 66#define mmMME5_RTR_HBW_WR_RQ_L_ARB 0x140180 67 68#define mmMME5_RTR_HBW_WR_RS_E_ARB 0x140190 69 70#define mmMME5_RTR_HBW_WR_RS_W_ARB 0x140194 71 72#define mmMME5_RTR_HBW_WR_RS_N_ARB 0x140198 73 74#define mmMME5_RTR_HBW_WR_RS_S_ARB 0x14019C 75 76#define mmMME5_RTR_HBW_WR_RS_L_ARB 0x1401A0 77 78#define mmMME5_RTR_LBW_RD_RQ_E_ARB 0x140200 79 80#define mmMME5_RTR_LBW_RD_RQ_W_ARB 0x140204 81 82#define mmMME5_RTR_LBW_RD_RQ_N_ARB 0x140208 83 84#define mmMME5_RTR_LBW_RD_RQ_S_ARB 0x14020C 85 86#define mmMME5_RTR_LBW_RD_RQ_L_ARB 0x140210 87 88#define mmMME5_RTR_LBW_E_ARB_MAX 0x140220 89 90#define mmMME5_RTR_LBW_W_ARB_MAX 0x140224 91 92#define mmMME5_RTR_LBW_N_ARB_MAX 0x140228 93 94#define mmMME5_RTR_LBW_S_ARB_MAX 0x14022C 95 96#define mmMME5_RTR_LBW_L_ARB_MAX 0x140230 97 98#define mmMME5_RTR_LBW_SRAM_MAX_CREDIT 0x140240 99 100#define mmMME5_RTR_LBW_RD_RS_E_ARB 0x140250 101 102#define mmMME5_RTR_LBW_RD_RS_W_ARB 0x140254 103 104#define mmMME5_RTR_LBW_RD_RS_N_ARB 0x140258 105 106#define mmMME5_RTR_LBW_RD_RS_S_ARB 0x14025C 107 108#define mmMME5_RTR_LBW_RD_RS_L_ARB 0x140260 109 110#define mmMME5_RTR_LBW_WR_RQ_E_ARB 0x140270 111 112#define mmMME5_RTR_LBW_WR_RQ_W_ARB 0x140274 113 114#define mmMME5_RTR_LBW_WR_RQ_N_ARB 0x140278 115 116#define mmMME5_RTR_LBW_WR_RQ_S_ARB 0x14027C 117 118#define mmMME5_RTR_LBW_WR_RQ_L_ARB 0x140280 119 120#define mmMME5_RTR_LBW_WR_RS_E_ARB 0x140290 121 122#define mmMME5_RTR_LBW_WR_RS_W_ARB 0x140294 123 124#define mmMME5_RTR_LBW_WR_RS_N_ARB 0x140298 125 126#define mmMME5_RTR_LBW_WR_RS_S_ARB 0x14029C 127 128#define mmMME5_RTR_LBW_WR_RS_L_ARB 0x1402A0 129 130#define mmMME5_RTR_DBG_E_ARB 0x140300 131 132#define mmMME5_RTR_DBG_W_ARB 0x140304 133 134#define mmMME5_RTR_DBG_N_ARB 0x140308 135 136#define mmMME5_RTR_DBG_S_ARB 0x14030C 137 138#define mmMME5_RTR_DBG_L_ARB 0x140310 139 140#define mmMME5_RTR_DBG_E_ARB_MAX 0x140320 141 142#define mmMME5_RTR_DBG_W_ARB_MAX 0x140324 143 144#define mmMME5_RTR_DBG_N_ARB_MAX 0x140328 145 146#define mmMME5_RTR_DBG_S_ARB_MAX 0x14032C 147 148#define mmMME5_RTR_DBG_L_ARB_MAX 0x140330 149 150#define mmMME5_RTR_SPLIT_COEF_0 0x140400 151 152#define mmMME5_RTR_SPLIT_COEF_1 0x140404 153 154#define mmMME5_RTR_SPLIT_COEF_2 0x140408 155 156#define mmMME5_RTR_SPLIT_COEF_3 0x14040C 157 158#define mmMME5_RTR_SPLIT_COEF_4 0x140410 159 160#define mmMME5_RTR_SPLIT_COEF_5 0x140414 161 162#define mmMME5_RTR_SPLIT_COEF_6 0x140418 163 164#define mmMME5_RTR_SPLIT_COEF_7 0x14041C 165 166#define mmMME5_RTR_SPLIT_COEF_8 0x140420 167 168#define mmMME5_RTR_SPLIT_COEF_9 0x140424 169 170#define mmMME5_RTR_SPLIT_CFG 0x140440 171 172#define mmMME5_RTR_SPLIT_RD_SAT 0x140444 173 174#define mmMME5_RTR_SPLIT_RD_RST_TOKEN 0x140448 175 176#define mmMME5_RTR_SPLIT_RD_TIMEOUT_0 0x14044C 177 178#define mmMME5_RTR_SPLIT_RD_TIMEOUT_1 0x140450 179 180#define mmMME5_RTR_SPLIT_WR_SAT 0x140454 181 182#define mmMME5_RTR_WPLIT_WR_TST_TOLEN 0x140458 183 184#define mmMME5_RTR_SPLIT_WR_TIMEOUT_0 0x14045C 185 186#define mmMME5_RTR_SPLIT_WR_TIMEOUT_1 0x140460 187 188#define mmMME5_RTR_HBW_RANGE_HIT 0x140470 189 190#define mmMME5_RTR_HBW_RANGE_MASK_L_0 0x140480 191 192#define mmMME5_RTR_HBW_RANGE_MASK_L_1 0x140484 193 194#define mmMME5_RTR_HBW_RANGE_MASK_L_2 0x140488 195 196#define mmMME5_RTR_HBW_RANGE_MASK_L_3 0x14048C 197 198#define mmMME5_RTR_HBW_RANGE_MASK_L_4 0x140490 199 200#define mmMME5_RTR_HBW_RANGE_MASK_L_5 0x140494 201 202#define mmMME5_RTR_HBW_RANGE_MASK_L_6 0x140498 203 204#define mmMME5_RTR_HBW_RANGE_MASK_L_7 0x14049C 205 206#define mmMME5_RTR_HBW_RANGE_MASK_H_0 0x1404A0 207 208#define mmMME5_RTR_HBW_RANGE_MASK_H_1 0x1404A4 209 210#define mmMME5_RTR_HBW_RANGE_MASK_H_2 0x1404A8 211 212#define mmMME5_RTR_HBW_RANGE_MASK_H_3 0x1404AC 213 214#define mmMME5_RTR_HBW_RANGE_MASK_H_4 0x1404B0 215 216#define mmMME5_RTR_HBW_RANGE_MASK_H_5 0x1404B4 217 218#define mmMME5_RTR_HBW_RANGE_MASK_H_6 0x1404B8 219 220#define mmMME5_RTR_HBW_RANGE_MASK_H_7 0x1404BC 221 222#define mmMME5_RTR_HBW_RANGE_BASE_L_0 0x1404C0 223 224#define mmMME5_RTR_HBW_RANGE_BASE_L_1 0x1404C4 225 226#define mmMME5_RTR_HBW_RANGE_BASE_L_2 0x1404C8 227 228#define mmMME5_RTR_HBW_RANGE_BASE_L_3 0x1404CC 229 230#define mmMME5_RTR_HBW_RANGE_BASE_L_4 0x1404D0 231 232#define mmMME5_RTR_HBW_RANGE_BASE_L_5 0x1404D4 233 234#define mmMME5_RTR_HBW_RANGE_BASE_L_6 0x1404D8 235 236#define mmMME5_RTR_HBW_RANGE_BASE_L_7 0x1404DC 237 238#define mmMME5_RTR_HBW_RANGE_BASE_H_0 0x1404E0 239 240#define mmMME5_RTR_HBW_RANGE_BASE_H_1 0x1404E4 241 242#define mmMME5_RTR_HBW_RANGE_BASE_H_2 0x1404E8 243 244#define mmMME5_RTR_HBW_RANGE_BASE_H_3 0x1404EC 245 246#define mmMME5_RTR_HBW_RANGE_BASE_H_4 0x1404F0 247 248#define mmMME5_RTR_HBW_RANGE_BASE_H_5 0x1404F4 249 250#define mmMME5_RTR_HBW_RANGE_BASE_H_6 0x1404F8 251 252#define mmMME5_RTR_HBW_RANGE_BASE_H_7 0x1404FC 253 254#define mmMME5_RTR_LBW_RANGE_HIT 0x140500 255 256#define mmMME5_RTR_LBW_RANGE_MASK_0 0x140510 257 258#define mmMME5_RTR_LBW_RANGE_MASK_1 0x140514 259 260#define mmMME5_RTR_LBW_RANGE_MASK_2 0x140518 261 262#define mmMME5_RTR_LBW_RANGE_MASK_3 0x14051C 263 264#define mmMME5_RTR_LBW_RANGE_MASK_4 0x140520 265 266#define mmMME5_RTR_LBW_RANGE_MASK_5 0x140524 267 268#define mmMME5_RTR_LBW_RANGE_MASK_6 0x140528 269 270#define mmMME5_RTR_LBW_RANGE_MASK_7 0x14052C 271 272#define mmMME5_RTR_LBW_RANGE_MASK_8 0x140530 273 274#define mmMME5_RTR_LBW_RANGE_MASK_9 0x140534 275 276#define mmMME5_RTR_LBW_RANGE_MASK_10 0x140538 277 278#define mmMME5_RTR_LBW_RANGE_MASK_11 0x14053C 279 280#define mmMME5_RTR_LBW_RANGE_MASK_12 0x140540 281 282#define mmMME5_RTR_LBW_RANGE_MASK_13 0x140544 283 284#define mmMME5_RTR_LBW_RANGE_MASK_14 0x140548 285 286#define mmMME5_RTR_LBW_RANGE_MASK_15 0x14054C 287 288#define mmMME5_RTR_LBW_RANGE_BASE_0 0x140550 289 290#define mmMME5_RTR_LBW_RANGE_BASE_1 0x140554 291 292#define mmMME5_RTR_LBW_RANGE_BASE_2 0x140558 293 294#define mmMME5_RTR_LBW_RANGE_BASE_3 0x14055C 295 296#define mmMME5_RTR_LBW_RANGE_BASE_4 0x140560 297 298#define mmMME5_RTR_LBW_RANGE_BASE_5 0x140564 299 300#define mmMME5_RTR_LBW_RANGE_BASE_6 0x140568 301 302#define mmMME5_RTR_LBW_RANGE_BASE_7 0x14056C 303 304#define mmMME5_RTR_LBW_RANGE_BASE_8 0x140570 305 306#define mmMME5_RTR_LBW_RANGE_BASE_9 0x140574 307 308#define mmMME5_RTR_LBW_RANGE_BASE_10 0x140578 309 310#define mmMME5_RTR_LBW_RANGE_BASE_11 0x14057C 311 312#define mmMME5_RTR_LBW_RANGE_BASE_12 0x140580 313 314#define mmMME5_RTR_LBW_RANGE_BASE_13 0x140584 315 316#define mmMME5_RTR_LBW_RANGE_BASE_14 0x140588 317 318#define mmMME5_RTR_LBW_RANGE_BASE_15 0x14058C 319 320#define mmMME5_RTR_RGLTR 0x140590 321 322#define mmMME5_RTR_RGLTR_WR_RESULT 0x140594 323 324#define mmMME5_RTR_RGLTR_RD_RESULT 0x140598 325 326#define mmMME5_RTR_SCRAMB_EN 0x140600 327 328#define mmMME5_RTR_NON_LIN_SCRAMB 0x140604 329 330#endif /* ASIC_REG_MME5_RTR_REGS_H_ */
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