ic_pll_regs.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2018 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_IC_PLL_REGS_H_
 14#define ASIC_REG_IC_PLL_REGS_H_
 15
 16/*
 17 *****************************************
 18 *   IC_PLL (Prototype: PLL)
 19 *****************************************
 20 */
 21
 22#define mmIC_PLL_NR                                                  0x4A3100
 23
 24#define mmIC_PLL_NF                                                  0x4A3104
 25
 26#define mmIC_PLL_OD                                                  0x4A3108
 27
 28#define mmIC_PLL_NB                                                  0x4A310C
 29
 30#define mmIC_PLL_CFG                                                 0x4A3110
 31
 32#define mmIC_PLL_LOSE_MASK                                           0x4A3120
 33
 34#define mmIC_PLL_LOCK_INTR                                           0x4A3128
 35
 36#define mmIC_PLL_LOCK_BYPASS                                         0x4A312C
 37
 38#define mmIC_PLL_DATA_CHNG                                           0x4A3130
 39
 40#define mmIC_PLL_RST                                                 0x4A3134
 41
 42#define mmIC_PLL_SLIP_WD_CNTR                                        0x4A3150
 43
 44#define mmIC_PLL_DIV_FACTOR_0                                        0x4A3200
 45
 46#define mmIC_PLL_DIV_FACTOR_1                                        0x4A3204
 47
 48#define mmIC_PLL_DIV_FACTOR_2                                        0x4A3208
 49
 50#define mmIC_PLL_DIV_FACTOR_3                                        0x4A320C
 51
 52#define mmIC_PLL_DIV_FACTOR_CMD_0                                    0x4A3220
 53
 54#define mmIC_PLL_DIV_FACTOR_CMD_1                                    0x4A3224
 55
 56#define mmIC_PLL_DIV_FACTOR_CMD_2                                    0x4A3228
 57
 58#define mmIC_PLL_DIV_FACTOR_CMD_3                                    0x4A322C
 59
 60#define mmIC_PLL_DIV_SEL_0                                           0x4A3280
 61
 62#define mmIC_PLL_DIV_SEL_1                                           0x4A3284
 63
 64#define mmIC_PLL_DIV_SEL_2                                           0x4A3288
 65
 66#define mmIC_PLL_DIV_SEL_3                                           0x4A328C
 67
 68#define mmIC_PLL_DIV_EN_0                                            0x4A32A0
 69
 70#define mmIC_PLL_DIV_EN_1                                            0x4A32A4
 71
 72#define mmIC_PLL_DIV_EN_2                                            0x4A32A8
 73
 74#define mmIC_PLL_DIV_EN_3                                            0x4A32AC
 75
 76#define mmIC_PLL_DIV_FACTOR_BUSY_0                                   0x4A32C0
 77
 78#define mmIC_PLL_DIV_FACTOR_BUSY_1                                   0x4A32C4
 79
 80#define mmIC_PLL_DIV_FACTOR_BUSY_2                                   0x4A32C8
 81
 82#define mmIC_PLL_DIV_FACTOR_BUSY_3                                   0x4A32CC
 83
 84#define mmIC_PLL_CLK_GATER                                           0x4A3300
 85
 86#define mmIC_PLL_CLK_RLX_0                                           0x4A3310
 87
 88#define mmIC_PLL_CLK_RLX_1                                           0x4A3314
 89
 90#define mmIC_PLL_CLK_RLX_2                                           0x4A3318
 91
 92#define mmIC_PLL_CLK_RLX_3                                           0x4A331C
 93
 94#define mmIC_PLL_REF_CNTR_PERIOD                                     0x4A3400
 95
 96#define mmIC_PLL_REF_LOW_THRESHOLD                                   0x4A3410
 97
 98#define mmIC_PLL_REF_HIGH_THRESHOLD                                  0x4A3420
 99
100#define mmIC_PLL_PLL_NOT_STABLE                                      0x4A3430
101
102#define mmIC_PLL_FREQ_CALC_EN                                        0x4A3440
103
104#endif /* ASIC_REG_IC_PLL_REGS_H_ */