dma_qm_2_regs.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2018 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_DMA_QM_2_REGS_H_
 14#define ASIC_REG_DMA_QM_2_REGS_H_
 15
 16/*
 17 *****************************************
 18 *   DMA_QM_2 (Prototype: QMAN)
 19 *****************************************
 20 */
 21
 22#define mmDMA_QM_2_GLBL_CFG0                                         0x410000
 23
 24#define mmDMA_QM_2_GLBL_CFG1                                         0x410004
 25
 26#define mmDMA_QM_2_GLBL_PROT                                         0x410008
 27
 28#define mmDMA_QM_2_GLBL_ERR_CFG                                      0x41000C
 29
 30#define mmDMA_QM_2_GLBL_ERR_ADDR_LO                                  0x410010
 31
 32#define mmDMA_QM_2_GLBL_ERR_ADDR_HI                                  0x410014
 33
 34#define mmDMA_QM_2_GLBL_ERR_WDATA                                    0x410018
 35
 36#define mmDMA_QM_2_GLBL_SECURE_PROPS                                 0x41001C
 37
 38#define mmDMA_QM_2_GLBL_NON_SECURE_PROPS                             0x410020
 39
 40#define mmDMA_QM_2_GLBL_STS0                                         0x410024
 41
 42#define mmDMA_QM_2_GLBL_STS1                                         0x410028
 43
 44#define mmDMA_QM_2_PQ_BASE_LO                                        0x410060
 45
 46#define mmDMA_QM_2_PQ_BASE_HI                                        0x410064
 47
 48#define mmDMA_QM_2_PQ_SIZE                                           0x410068
 49
 50#define mmDMA_QM_2_PQ_PI                                             0x41006C
 51
 52#define mmDMA_QM_2_PQ_CI                                             0x410070
 53
 54#define mmDMA_QM_2_PQ_CFG0                                           0x410074
 55
 56#define mmDMA_QM_2_PQ_CFG1                                           0x410078
 57
 58#define mmDMA_QM_2_PQ_ARUSER                                         0x41007C
 59
 60#define mmDMA_QM_2_PQ_PUSH0                                          0x410080
 61
 62#define mmDMA_QM_2_PQ_PUSH1                                          0x410084
 63
 64#define mmDMA_QM_2_PQ_PUSH2                                          0x410088
 65
 66#define mmDMA_QM_2_PQ_PUSH3                                          0x41008C
 67
 68#define mmDMA_QM_2_PQ_STS0                                           0x410090
 69
 70#define mmDMA_QM_2_PQ_STS1                                           0x410094
 71
 72#define mmDMA_QM_2_PQ_RD_RATE_LIM_EN                                 0x4100A0
 73
 74#define mmDMA_QM_2_PQ_RD_RATE_LIM_RST_TOKEN                          0x4100A4
 75
 76#define mmDMA_QM_2_PQ_RD_RATE_LIM_SAT                                0x4100A8
 77
 78#define mmDMA_QM_2_PQ_RD_RATE_LIM_TOUT                               0x4100AC
 79
 80#define mmDMA_QM_2_CQ_CFG0                                           0x4100B0
 81
 82#define mmDMA_QM_2_CQ_CFG1                                           0x4100B4
 83
 84#define mmDMA_QM_2_CQ_ARUSER                                         0x4100B8
 85
 86#define mmDMA_QM_2_CQ_PTR_LO                                         0x4100C0
 87
 88#define mmDMA_QM_2_CQ_PTR_HI                                         0x4100C4
 89
 90#define mmDMA_QM_2_CQ_TSIZE                                          0x4100C8
 91
 92#define mmDMA_QM_2_CQ_CTL                                            0x4100CC
 93
 94#define mmDMA_QM_2_CQ_PTR_LO_STS                                     0x4100D4
 95
 96#define mmDMA_QM_2_CQ_PTR_HI_STS                                     0x4100D8
 97
 98#define mmDMA_QM_2_CQ_TSIZE_STS                                      0x4100DC
 99
100#define mmDMA_QM_2_CQ_CTL_STS                                        0x4100E0
101
102#define mmDMA_QM_2_CQ_STS0                                           0x4100E4
103
104#define mmDMA_QM_2_CQ_STS1                                           0x4100E8
105
106#define mmDMA_QM_2_CQ_RD_RATE_LIM_EN                                 0x4100F0
107
108#define mmDMA_QM_2_CQ_RD_RATE_LIM_RST_TOKEN                          0x4100F4
109
110#define mmDMA_QM_2_CQ_RD_RATE_LIM_SAT                                0x4100F8
111
112#define mmDMA_QM_2_CQ_RD_RATE_LIM_TOUT                               0x4100FC
113
114#define mmDMA_QM_2_CQ_IFIFO_CNT                                      0x410108
115
116#define mmDMA_QM_2_CP_MSG_BASE0_ADDR_LO                              0x410120
117
118#define mmDMA_QM_2_CP_MSG_BASE0_ADDR_HI                              0x410124
119
120#define mmDMA_QM_2_CP_MSG_BASE1_ADDR_LO                              0x410128
121
122#define mmDMA_QM_2_CP_MSG_BASE1_ADDR_HI                              0x41012C
123
124#define mmDMA_QM_2_CP_MSG_BASE2_ADDR_LO                              0x410130
125
126#define mmDMA_QM_2_CP_MSG_BASE2_ADDR_HI                              0x410134
127
128#define mmDMA_QM_2_CP_MSG_BASE3_ADDR_LO                              0x410138
129
130#define mmDMA_QM_2_CP_MSG_BASE3_ADDR_HI                              0x41013C
131
132#define mmDMA_QM_2_CP_LDMA_TSIZE_OFFSET                              0x410140
133
134#define mmDMA_QM_2_CP_LDMA_SRC_BASE_LO_OFFSET                        0x410144
135
136#define mmDMA_QM_2_CP_LDMA_SRC_BASE_HI_OFFSET                        0x410148
137
138#define mmDMA_QM_2_CP_LDMA_DST_BASE_LO_OFFSET                        0x41014C
139
140#define mmDMA_QM_2_CP_LDMA_DST_BASE_HI_OFFSET                        0x410150
141
142#define mmDMA_QM_2_CP_LDMA_COMMIT_OFFSET                             0x410154
143
144#define mmDMA_QM_2_CP_FENCE0_RDATA                                   0x410158
145
146#define mmDMA_QM_2_CP_FENCE1_RDATA                                   0x41015C
147
148#define mmDMA_QM_2_CP_FENCE2_RDATA                                   0x410160
149
150#define mmDMA_QM_2_CP_FENCE3_RDATA                                   0x410164
151
152#define mmDMA_QM_2_CP_FENCE0_CNT                                     0x410168
153
154#define mmDMA_QM_2_CP_FENCE1_CNT                                     0x41016C
155
156#define mmDMA_QM_2_CP_FENCE2_CNT                                     0x410170
157
158#define mmDMA_QM_2_CP_FENCE3_CNT                                     0x410174
159
160#define mmDMA_QM_2_CP_STS                                            0x410178
161
162#define mmDMA_QM_2_CP_CURRENT_INST_LO                                0x41017C
163
164#define mmDMA_QM_2_CP_CURRENT_INST_HI                                0x410180
165
166#define mmDMA_QM_2_CP_BARRIER_CFG                                    0x410184
167
168#define mmDMA_QM_2_CP_DBG_0                                          0x410188
169
170#define mmDMA_QM_2_PQ_BUF_ADDR                                       0x410300
171
172#define mmDMA_QM_2_PQ_BUF_RDATA                                      0x410304
173
174#define mmDMA_QM_2_CQ_BUF_ADDR                                       0x410308
175
176#define mmDMA_QM_2_CQ_BUF_RDATA                                      0x41030C
177
178#endif /* ASIC_REG_DMA_QM_2_REGS_H_ */