dma_macro_regs.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2018 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_DMA_MACRO_REGS_H_
 14#define ASIC_REG_DMA_MACRO_REGS_H_
 15
 16/*
 17 *****************************************
 18 *   DMA_MACRO (Prototype: DMA_MACRO)
 19 *****************************************
 20 */
 21
 22#define mmDMA_MACRO_LBW_RANGE_HIT_BLOCK                              0x4B0000
 23
 24#define mmDMA_MACRO_LBW_RANGE_MASK_0                                 0x4B0004
 25
 26#define mmDMA_MACRO_LBW_RANGE_MASK_1                                 0x4B0008
 27
 28#define mmDMA_MACRO_LBW_RANGE_MASK_2                                 0x4B000C
 29
 30#define mmDMA_MACRO_LBW_RANGE_MASK_3                                 0x4B0010
 31
 32#define mmDMA_MACRO_LBW_RANGE_MASK_4                                 0x4B0014
 33
 34#define mmDMA_MACRO_LBW_RANGE_MASK_5                                 0x4B0018
 35
 36#define mmDMA_MACRO_LBW_RANGE_MASK_6                                 0x4B001C
 37
 38#define mmDMA_MACRO_LBW_RANGE_MASK_7                                 0x4B0020
 39
 40#define mmDMA_MACRO_LBW_RANGE_MASK_8                                 0x4B0024
 41
 42#define mmDMA_MACRO_LBW_RANGE_MASK_9                                 0x4B0028
 43
 44#define mmDMA_MACRO_LBW_RANGE_MASK_10                                0x4B002C
 45
 46#define mmDMA_MACRO_LBW_RANGE_MASK_11                                0x4B0030
 47
 48#define mmDMA_MACRO_LBW_RANGE_MASK_12                                0x4B0034
 49
 50#define mmDMA_MACRO_LBW_RANGE_MASK_13                                0x4B0038
 51
 52#define mmDMA_MACRO_LBW_RANGE_MASK_14                                0x4B003C
 53
 54#define mmDMA_MACRO_LBW_RANGE_MASK_15                                0x4B0040
 55
 56#define mmDMA_MACRO_LBW_RANGE_BASE_0                                 0x4B0044
 57
 58#define mmDMA_MACRO_LBW_RANGE_BASE_1                                 0x4B0048
 59
 60#define mmDMA_MACRO_LBW_RANGE_BASE_2                                 0x4B004C
 61
 62#define mmDMA_MACRO_LBW_RANGE_BASE_3                                 0x4B0050
 63
 64#define mmDMA_MACRO_LBW_RANGE_BASE_4                                 0x4B0054
 65
 66#define mmDMA_MACRO_LBW_RANGE_BASE_5                                 0x4B0058
 67
 68#define mmDMA_MACRO_LBW_RANGE_BASE_6                                 0x4B005C
 69
 70#define mmDMA_MACRO_LBW_RANGE_BASE_7                                 0x4B0060
 71
 72#define mmDMA_MACRO_LBW_RANGE_BASE_8                                 0x4B0064
 73
 74#define mmDMA_MACRO_LBW_RANGE_BASE_9                                 0x4B0068
 75
 76#define mmDMA_MACRO_LBW_RANGE_BASE_10                                0x4B006C
 77
 78#define mmDMA_MACRO_LBW_RANGE_BASE_11                                0x4B0070
 79
 80#define mmDMA_MACRO_LBW_RANGE_BASE_12                                0x4B0074
 81
 82#define mmDMA_MACRO_LBW_RANGE_BASE_13                                0x4B0078
 83
 84#define mmDMA_MACRO_LBW_RANGE_BASE_14                                0x4B007C
 85
 86#define mmDMA_MACRO_LBW_RANGE_BASE_15                                0x4B0080
 87
 88#define mmDMA_MACRO_HBW_RANGE_HIT_BLOCK                              0x4B0084
 89
 90#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_0                           0x4B00A8
 91
 92#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_1                           0x4B00AC
 93
 94#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_2                           0x4B00B0
 95
 96#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_3                           0x4B00B4
 97
 98#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_4                           0x4B00B8
 99
100#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_5                           0x4B00BC
101
102#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_6                           0x4B00C0
103
104#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_7                           0x4B00C4
105
106#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_0                            0x4B00C8
107
108#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_1                            0x4B00CC
109
110#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_2                            0x4B00D0
111
112#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_3                            0x4B00D4
113
114#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_4                            0x4B00D8
115
116#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_5                            0x4B00DC
117
118#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_6                            0x4B00E0
119
120#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_7                            0x4B00E4
121
122#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_0                           0x4B00E8
123
124#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_1                           0x4B00EC
125
126#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_2                           0x4B00F0
127
128#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_3                           0x4B00F4
129
130#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_4                           0x4B00F8
131
132#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_5                           0x4B00FC
133
134#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_6                           0x4B0100
135
136#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_7                           0x4B0104
137
138#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_0                            0x4B0108
139
140#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_1                            0x4B010C
141
142#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_2                            0x4B0110
143
144#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_3                            0x4B0114
145
146#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_4                            0x4B0118
147
148#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_5                            0x4B011C
149
150#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_6                            0x4B0120
151
152#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_7                            0x4B0124
153
154#define mmDMA_MACRO_WRITE_EN                                         0x4B0128
155
156#define mmDMA_MACRO_WRITE_CREDIT                                     0x4B012C
157
158#define mmDMA_MACRO_READ_EN                                          0x4B0130
159
160#define mmDMA_MACRO_READ_CREDIT                                      0x4B0134
161
162#define mmDMA_MACRO_SRAM_BUSY                                        0x4B0138
163
164#define mmDMA_MACRO_RAZWI_LBW_WT_VLD                                 0x4B013C
165
166#define mmDMA_MACRO_RAZWI_LBW_WT_ID                                  0x4B0140
167
168#define mmDMA_MACRO_RAZWI_LBW_RD_VLD                                 0x4B0144
169
170#define mmDMA_MACRO_RAZWI_LBW_RD_ID                                  0x4B0148
171
172#define mmDMA_MACRO_RAZWI_HBW_WT_VLD                                 0x4B014C
173
174#define mmDMA_MACRO_RAZWI_HBW_WT_ID                                  0x4B0150
175
176#define mmDMA_MACRO_RAZWI_HBW_RD_VLD                                 0x4B0154
177
178#define mmDMA_MACRO_RAZWI_HBW_RD_ID                                  0x4B0158
179
180#endif /* ASIC_REG_DMA_MACRO_REGS_H_ */