dma_macro_masks.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2018 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_DMA_MACRO_MASKS_H_
 14#define ASIC_REG_DMA_MACRO_MASKS_H_
 15
 16/*
 17 *****************************************
 18 *   DMA_MACRO (Prototype: DMA_MACRO)
 19 *****************************************
 20 */
 21
 22/* DMA_MACRO_LBW_RANGE_HIT_BLOCK */
 23#define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_SHIFT                        0
 24#define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_MASK                         0xFFFF
 25
 26/* DMA_MACRO_LBW_RANGE_MASK */
 27#define DMA_MACRO_LBW_RANGE_MASK_R_SHIFT                             0
 28#define DMA_MACRO_LBW_RANGE_MASK_R_MASK                              0x3FFFFFF
 29
 30/* DMA_MACRO_LBW_RANGE_BASE */
 31#define DMA_MACRO_LBW_RANGE_BASE_R_SHIFT                             0
 32#define DMA_MACRO_LBW_RANGE_BASE_R_MASK                              0x3FFFFFF
 33
 34/* DMA_MACRO_HBW_RANGE_HIT_BLOCK */
 35#define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_SHIFT                        0
 36#define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_MASK                         0xFF
 37
 38/* DMA_MACRO_HBW_RANGE_MASK_49_32 */
 39#define DMA_MACRO_HBW_RANGE_MASK_49_32_R_SHIFT                       0
 40#define DMA_MACRO_HBW_RANGE_MASK_49_32_R_MASK                        0x3FFFF
 41
 42/* DMA_MACRO_HBW_RANGE_MASK_31_0 */
 43#define DMA_MACRO_HBW_RANGE_MASK_31_0_R_SHIFT                        0
 44#define DMA_MACRO_HBW_RANGE_MASK_31_0_R_MASK                         0xFFFFFFFF
 45
 46/* DMA_MACRO_HBW_RANGE_BASE_49_32 */
 47#define DMA_MACRO_HBW_RANGE_BASE_49_32_R_SHIFT                       0
 48#define DMA_MACRO_HBW_RANGE_BASE_49_32_R_MASK                        0x3FFFF
 49
 50/* DMA_MACRO_HBW_RANGE_BASE_31_0 */
 51#define DMA_MACRO_HBW_RANGE_BASE_31_0_R_SHIFT                        0
 52#define DMA_MACRO_HBW_RANGE_BASE_31_0_R_MASK                         0xFFFFFFFF
 53
 54/* DMA_MACRO_WRITE_EN */
 55#define DMA_MACRO_WRITE_EN_R_SHIFT                                   0
 56#define DMA_MACRO_WRITE_EN_R_MASK                                    0x1
 57
 58/* DMA_MACRO_WRITE_CREDIT */
 59#define DMA_MACRO_WRITE_CREDIT_R_SHIFT                               0
 60#define DMA_MACRO_WRITE_CREDIT_R_MASK                                0x3FF
 61
 62/* DMA_MACRO_READ_EN */
 63#define DMA_MACRO_READ_EN_R_SHIFT                                    0
 64#define DMA_MACRO_READ_EN_R_MASK                                     0x1
 65
 66/* DMA_MACRO_READ_CREDIT */
 67#define DMA_MACRO_READ_CREDIT_R_SHIFT                                0
 68#define DMA_MACRO_READ_CREDIT_R_MASK                                 0x3FF
 69
 70/* DMA_MACRO_SRAM_BUSY */
 71
 72/* DMA_MACRO_RAZWI_LBW_WT_VLD */
 73#define DMA_MACRO_RAZWI_LBW_WT_VLD_R_SHIFT                           0
 74#define DMA_MACRO_RAZWI_LBW_WT_VLD_R_MASK                            0x1
 75
 76/* DMA_MACRO_RAZWI_LBW_WT_ID */
 77#define DMA_MACRO_RAZWI_LBW_WT_ID_R_SHIFT                            0
 78#define DMA_MACRO_RAZWI_LBW_WT_ID_R_MASK                             0x7FFF
 79
 80/* DMA_MACRO_RAZWI_LBW_RD_VLD */
 81#define DMA_MACRO_RAZWI_LBW_RD_VLD_R_SHIFT                           0
 82#define DMA_MACRO_RAZWI_LBW_RD_VLD_R_MASK                            0x1
 83
 84/* DMA_MACRO_RAZWI_LBW_RD_ID */
 85#define DMA_MACRO_RAZWI_LBW_RD_ID_R_SHIFT                            0
 86#define DMA_MACRO_RAZWI_LBW_RD_ID_R_MASK                             0x7FFF
 87
 88/* DMA_MACRO_RAZWI_HBW_WT_VLD */
 89#define DMA_MACRO_RAZWI_HBW_WT_VLD_R_SHIFT                           0
 90#define DMA_MACRO_RAZWI_HBW_WT_VLD_R_MASK                            0x1
 91
 92/* DMA_MACRO_RAZWI_HBW_WT_ID */
 93#define DMA_MACRO_RAZWI_HBW_WT_ID_R_SHIFT                            0
 94#define DMA_MACRO_RAZWI_HBW_WT_ID_R_MASK                             0x1FFFFFFF
 95
 96/* DMA_MACRO_RAZWI_HBW_RD_VLD */
 97#define DMA_MACRO_RAZWI_HBW_RD_VLD_R_SHIFT                           0
 98#define DMA_MACRO_RAZWI_HBW_RD_VLD_R_MASK                            0x1
 99
100/* DMA_MACRO_RAZWI_HBW_RD_ID */
101#define DMA_MACRO_RAZWI_HBW_RD_ID_R_SHIFT                            0
102#define DMA_MACRO_RAZWI_HBW_RD_ID_R_MASK                             0x1FFFFFFF
103
104#endif /* ASIC_REG_DMA_MACRO_MASKS_H_ */