dma_ch_0_regs.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2018 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_DMA_CH_0_REGS_H_
 14#define ASIC_REG_DMA_CH_0_REGS_H_
 15
 16/*
 17 *****************************************
 18 *   DMA_CH_0 (Prototype: DMA_CH)
 19 *****************************************
 20 */
 21
 22#define mmDMA_CH_0_CFG0                                              0x401000
 23
 24#define mmDMA_CH_0_CFG1                                              0x401004
 25
 26#define mmDMA_CH_0_ERRMSG_ADDR_LO                                    0x401008
 27
 28#define mmDMA_CH_0_ERRMSG_ADDR_HI                                    0x40100C
 29
 30#define mmDMA_CH_0_ERRMSG_WDATA                                      0x401010
 31
 32#define mmDMA_CH_0_RD_COMP_ADDR_LO                                   0x401014
 33
 34#define mmDMA_CH_0_RD_COMP_ADDR_HI                                   0x401018
 35
 36#define mmDMA_CH_0_RD_COMP_WDATA                                     0x40101C
 37
 38#define mmDMA_CH_0_WR_COMP_ADDR_LO                                   0x401020
 39
 40#define mmDMA_CH_0_WR_COMP_ADDR_HI                                   0x401024
 41
 42#define mmDMA_CH_0_WR_COMP_WDATA                                     0x401028
 43
 44#define mmDMA_CH_0_LDMA_SRC_ADDR_LO                                  0x40102C
 45
 46#define mmDMA_CH_0_LDMA_SRC_ADDR_HI                                  0x401030
 47
 48#define mmDMA_CH_0_LDMA_DST_ADDR_LO                                  0x401034
 49
 50#define mmDMA_CH_0_LDMA_DST_ADDR_HI                                  0x401038
 51
 52#define mmDMA_CH_0_LDMA_TSIZE                                        0x40103C
 53
 54#define mmDMA_CH_0_COMIT_TRANSFER                                    0x401040
 55
 56#define mmDMA_CH_0_STS0                                              0x401044
 57
 58#define mmDMA_CH_0_STS1                                              0x401048
 59
 60#define mmDMA_CH_0_STS2                                              0x40104C
 61
 62#define mmDMA_CH_0_STS3                                              0x401050
 63
 64#define mmDMA_CH_0_STS4                                              0x401054
 65
 66#define mmDMA_CH_0_SRC_ADDR_LO_STS                                   0x401058
 67
 68#define mmDMA_CH_0_SRC_ADDR_HI_STS                                   0x40105C
 69
 70#define mmDMA_CH_0_SRC_TSIZE_STS                                     0x401060
 71
 72#define mmDMA_CH_0_DST_ADDR_LO_STS                                   0x401064
 73
 74#define mmDMA_CH_0_DST_ADDR_HI_STS                                   0x401068
 75
 76#define mmDMA_CH_0_DST_TSIZE_STS                                     0x40106C
 77
 78#define mmDMA_CH_0_RD_RATE_LIM_EN                                    0x401070
 79
 80#define mmDMA_CH_0_RD_RATE_LIM_RST_TOKEN                             0x401074
 81
 82#define mmDMA_CH_0_RD_RATE_LIM_SAT                                   0x401078
 83
 84#define mmDMA_CH_0_RD_RATE_LIM_TOUT                                  0x40107C
 85
 86#define mmDMA_CH_0_WR_RATE_LIM_EN                                    0x401080
 87
 88#define mmDMA_CH_0_WR_RATE_LIM_RST_TOKEN                             0x401084
 89
 90#define mmDMA_CH_0_WR_RATE_LIM_SAT                                   0x401088
 91
 92#define mmDMA_CH_0_WR_RATE_LIM_TOUT                                  0x40108C
 93
 94#define mmDMA_CH_0_CFG2                                              0x401090
 95
 96#define mmDMA_CH_0_TDMA_CTL                                          0x401100
 97
 98#define mmDMA_CH_0_TDMA_SRC_BASE_ADDR_LO                             0x401104
 99
100#define mmDMA_CH_0_TDMA_SRC_BASE_ADDR_HI                             0x401108
101
102#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_0                               0x40110C
103
104#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_0                               0x401110
105
106#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0                         0x401114
107
108#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_0                           0x401118
109
110#define mmDMA_CH_0_TDMA_SRC_STRIDE_0                                 0x40111C
111
112#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_1                               0x401120
113
114#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_1                               0x401124
115
116#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1                         0x401128
117
118#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_1                           0x40112C
119
120#define mmDMA_CH_0_TDMA_SRC_STRIDE_1                                 0x401130
121
122#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_2                               0x401134
123
124#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_2                               0x401138
125
126#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2                         0x40113C
127
128#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_2                           0x401140
129
130#define mmDMA_CH_0_TDMA_SRC_STRIDE_2                                 0x401144
131
132#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_3                               0x401148
133
134#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_3                               0x40114C
135
136#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3                         0x401150
137
138#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_3                           0x401154
139
140#define mmDMA_CH_0_TDMA_SRC_STRIDE_3                                 0x401158
141
142#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_4                               0x40115C
143
144#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_4                               0x401160
145
146#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4                         0x401164
147
148#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_4                           0x401168
149
150#define mmDMA_CH_0_TDMA_SRC_STRIDE_4                                 0x40116C
151
152#define mmDMA_CH_0_TDMA_DST_BASE_ADDR_LO                             0x401170
153
154#define mmDMA_CH_0_TDMA_DST_BASE_ADDR_HI                             0x401174
155
156#define mmDMA_CH_0_TDMA_DST_ROI_BASE_0                               0x401178
157
158#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_0                               0x40117C
159
160#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_0                         0x401180
161
162#define mmDMA_CH_0_TDMA_DST_START_OFFSET_0                           0x401184
163
164#define mmDMA_CH_0_TDMA_DST_STRIDE_0                                 0x401188
165
166#define mmDMA_CH_0_TDMA_DST_ROI_BASE_1                               0x40118C
167
168#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_1                               0x401190
169
170#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_1                         0x401194
171
172#define mmDMA_CH_0_TDMA_DST_START_OFFSET_1                           0x401198
173
174#define mmDMA_CH_0_TDMA_DST_STRIDE_1                                 0x40119C
175
176#define mmDMA_CH_0_TDMA_DST_ROI_BASE_2                               0x4011A0
177
178#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_2                               0x4011A4
179
180#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_2                         0x4011A8
181
182#define mmDMA_CH_0_TDMA_DST_START_OFFSET_2                           0x4011AC
183
184#define mmDMA_CH_0_TDMA_DST_STRIDE_2                                 0x4011B0
185
186#define mmDMA_CH_0_TDMA_DST_ROI_BASE_3                               0x4011B4
187
188#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_3                               0x4011B8
189
190#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_3                         0x4011BC
191
192#define mmDMA_CH_0_TDMA_DST_START_OFFSET_3                           0x4011C0
193
194#define mmDMA_CH_0_TDMA_DST_STRIDE_3                                 0x4011C4
195
196#define mmDMA_CH_0_TDMA_DST_ROI_BASE_4                               0x4011C8
197
198#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_4                               0x4011CC
199
200#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_4                         0x4011D0
201
202#define mmDMA_CH_0_TDMA_DST_START_OFFSET_4                           0x4011D4
203
204#define mmDMA_CH_0_TDMA_DST_STRIDE_4                                 0x4011D8
205
206#define mmDMA_CH_0_MEM_INIT_BUSY                                     0x4011FC
207
208#endif /* ASIC_REG_DMA_CH_0_REGS_H_ */