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cpu_ca53_cfg_regs.h

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linux-6.19.14/drivers/accel/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h C
 1/* SPDX-License-Identifier: GPL-2.0
 2 *
 3 * Copyright 2016-2018 HabanaLabs, Ltd.
 4 * All Rights Reserved.
 5 *
 6 */
 7
 8/************************************
 9 ** This is an auto-generated file **
10 **       DO NOT EDIT BELOW        **
11 ************************************/
12
13#ifndef ASIC_REG_CPU_CA53_CFG_REGS_H_
14#define ASIC_REG_CPU_CA53_CFG_REGS_H_
15
16/*
17 *****************************************
18 *   CPU_CA53_CFG (Prototype: CA53_CFG)
19 *****************************************
20 */
21
22#define mmCPU_CA53_CFG_ARM_CFG                                       0x441100
23
24#define mmCPU_CA53_CFG_RST_ADDR_LSB_0                                0x441104
25
26#define mmCPU_CA53_CFG_RST_ADDR_LSB_1                                0x441108
27
28#define mmCPU_CA53_CFG_RST_ADDR_MSB_0                                0x441114
29
30#define mmCPU_CA53_CFG_RST_ADDR_MSB_1                                0x441118
31
32#define mmCPU_CA53_CFG_ARM_RST_CONTROL                               0x441124
33
34#define mmCPU_CA53_CFG_ARM_AFFINITY                                  0x441128
35
36#define mmCPU_CA53_CFG_ARM_DISABLE                                   0x44112C
37
38#define mmCPU_CA53_CFG_ARM_GIC_PERIPHBASE                            0x441130
39
40#define mmCPU_CA53_CFG_ARM_GIC_IRQ_CFG                               0x441134
41
42#define mmCPU_CA53_CFG_ARM_PWR_MNG                                   0x441138
43
44#define mmCPU_CA53_CFG_ARB_DBG_ROM_ADDR                              0x44113C
45
46#define mmCPU_CA53_CFG_ARM_DBG_MODES                                 0x441140
47
48#define mmCPU_CA53_CFG_ARM_PWR_STAT_0                                0x441200
49
50#define mmCPU_CA53_CFG_ARM_PWR_STAT_1                                0x441204
51
52#define mmCPU_CA53_CFG_ARM_DBG_STATUS                                0x441208
53
54#define mmCPU_CA53_CFG_ARM_MEM_ATTR                                  0x44120C
55
56#define mmCPU_CA53_CFG_ARM_PMU_0                                     0x441210
57
58#define mmCPU_CA53_CFG_ARM_PMU_1                                     0x441214
59
60#endif /* ASIC_REG_CPU_CA53_CFG_REGS_H_ */
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