xbar_edge_0_regs.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2020 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_XBAR_EDGE_0_REGS_H_
 14#define ASIC_REG_XBAR_EDGE_0_REGS_H_
 15
 16/*
 17 *****************************************
 18 *   XBAR_EDGE_0
 19 *   (Prototype: XBAR)
 20 *****************************************
 21 */
 22
 23#define mmXBAR_EDGE_0_LBW_HIF0_BASE_ADDR 0x4D48000
 24
 25#define mmXBAR_EDGE_0_LBW_HIF0_ADDR_MASK 0x4D48004
 26
 27#define mmXBAR_EDGE_0_LBW_HIF1_BASE_ADDR 0x4D48008
 28
 29#define mmXBAR_EDGE_0_LBW_HIF1_ADDR_MASK 0x4D4800C
 30
 31#define mmXBAR_EDGE_0_LBW_HMMU0_BASE_ADDR 0x4D48010
 32
 33#define mmXBAR_EDGE_0_LBW_HMMU0_ADDR_MASK 0x4D48014
 34
 35#define mmXBAR_EDGE_0_LBW_HMMU1_BASE_ADDR 0x4D48018
 36
 37#define mmXBAR_EDGE_0_LBW_HMMU1_ADDR_MASK 0x4D4801C
 38
 39#define mmXBAR_EDGE_0_LBW_EDMA_BASE_ADDR0 0x4D48020
 40
 41#define mmXBAR_EDGE_0_LBW_EDMA_ADDR_MASK0 0x4D48024
 42
 43#define mmXBAR_EDGE_0_LBW_EDMA_BASE_ADDR1 0x4D48028
 44
 45#define mmXBAR_EDGE_0_LBW_EDMA_ADDR_MASK1 0x4D4802C
 46
 47#define mmXBAR_EDGE_0_LBW_HBM_BASE_ADDR0 0x4D48030
 48
 49#define mmXBAR_EDGE_0_LBW_HBM_ADDR_MASK0 0x4D48034
 50
 51#define mmXBAR_EDGE_0_LBW_HBM_BASE_ADDR1 0x4D48038
 52
 53#define mmXBAR_EDGE_0_LBW_HBM_ADDR_MASK1 0x4D4803C
 54
 55#define mmXBAR_EDGE_0_LBW_XBAR_BASE_ADDR0 0x4D48040
 56
 57#define mmXBAR_EDGE_0_LBW_XBAR_ADDR_MASK0 0x4D48044
 58
 59#define mmXBAR_EDGE_0_LBW_XBAR_BASE_ADDR1 0x4D48048
 60
 61#define mmXBAR_EDGE_0_LBW_XBAR_ADDR_MASK1 0x4D4804C
 62
 63#define mmXBAR_EDGE_0_DBG_HIF0_BASE_ADDR 0x4D48080
 64
 65#define mmXBAR_EDGE_0_DBG_HIF0_ADDR_MASK 0x4D48084
 66
 67#define mmXBAR_EDGE_0_DBG_HIF1_BASE_ADDR 0x4D48088
 68
 69#define mmXBAR_EDGE_0_DBG_HIF1_ADDR_MASK 0x4D4808C
 70
 71#define mmXBAR_EDGE_0_DBG_HMMU0_BASE_ADDR 0x4D48090
 72
 73#define mmXBAR_EDGE_0_DBG_HMMU0_ADDR_MASK 0x4D48094
 74
 75#define mmXBAR_EDGE_0_DBG_HMMU1_BASE_ADDR 0x4D48098
 76
 77#define mmXBAR_EDGE_0_DBG_HMMU1_ADDR_MASK 0x4D4809C
 78
 79#define mmXBAR_EDGE_0_DBG_EDMA_BASE_ADDR0 0x4D480A0
 80
 81#define mmXBAR_EDGE_0_DBG_EDMA_ADDR_MASK0 0x4D480A4
 82
 83#define mmXBAR_EDGE_0_DBG_EDMA_BASE_ADDR1 0x4D480A8
 84
 85#define mmXBAR_EDGE_0_DBG_EDMA_ADDR_MASK1 0x4D480AC
 86
 87#define mmXBAR_EDGE_0_DBG_HBM_BASE_ADDR0 0x4D480B0
 88
 89#define mmXBAR_EDGE_0_DBG_HBM_ADDR_MASK0 0x4D480B4
 90
 91#define mmXBAR_EDGE_0_DBG_HBM_BASE_ADDR1 0x4D480B8
 92
 93#define mmXBAR_EDGE_0_DBG_HBM_ADDR_MASK1 0x4D480BC
 94
 95#define mmXBAR_EDGE_0_DBG_XBAR_BASE_ADDR0 0x4D480C0
 96
 97#define mmXBAR_EDGE_0_DBG_XBAR_ADDR_MASK0 0x4D480C4
 98
 99#define mmXBAR_EDGE_0_DBG_XBAR_BASE_ADDR1 0x4D480C8
100
101#define mmXBAR_EDGE_0_DBG_XBAR_ADDR_MASK1 0x4D480CC
102
103#define mmXBAR_EDGE_0_LBW_INTERNAL_ADDR_RGF 0x4D480D0
104
105#define mmXBAR_EDGE_0_DBG_INTERNAL_ADDR_FUN 0x4D480D4
106
107#define mmXBAR_EDGE_0_EMEM_HBM_BIT_LOCATION 0x4D48100
108
109#define mmXBAR_EDGE_0_EMEM_PC_BIT_LOCATION 0x4D48104
110
111#define mmXBAR_EDGE_0_HIF_WR_RS_CH_LOCATION 0x4D48108
112
113#define mmXBAR_EDGE_0_HBW_MST_ARB_WEIGHT 0x4D4810C
114
115#define mmXBAR_EDGE_0_MMU_PC_IDX_MAP_0 0x4D48110
116
117#define mmXBAR_EDGE_0_MMU_PC_IDX_MAP_1 0x4D48114
118
119#define mmXBAR_EDGE_0_MMU_RD_LL_ARB_0 0x4D48120
120
121#define mmXBAR_EDGE_0_MMU_RD_LL_ARB_1 0x4D48124
122
123#define mmXBAR_EDGE_0_MMU_WR_LL_ARB_0 0x4D48128
124
125#define mmXBAR_EDGE_0_MMU_WR_LL_ARB_1 0x4D4812C
126
127#define mmXBAR_EDGE_0_HBM_USER_RESP_OVR_0 0x4D48130
128
129#define mmXBAR_EDGE_0_HBM_USER_RESP_OVR_1 0x4D48134
130
131#define mmXBAR_EDGE_0_RL_RD_0 0x4D48140
132
133#define mmXBAR_EDGE_0_RL_RD_1 0x4D48144
134
135#define mmXBAR_EDGE_0_RL_RD_2 0x4D48148
136
137#define mmXBAR_EDGE_0_RL_RD_3 0x4D4814C
138
139#define mmXBAR_EDGE_0_RL_RD_4 0x4D48150
140
141#define mmXBAR_EDGE_0_RL_RD_5 0x4D48154
142
143#define mmXBAR_EDGE_0_RL_RD_6 0x4D48158
144
145#define mmXBAR_EDGE_0_RL_RD_7 0x4D4815C
146
147#define mmXBAR_EDGE_0_RL_RD_8 0x4D48160
148
149#define mmXBAR_EDGE_0_RL_RD_9 0x4D48164
150
151#define mmXBAR_EDGE_0_RL_RD_10 0x4D48168
152
153#define mmXBAR_EDGE_0_RL_RD_11 0x4D4816C
154
155#define mmXBAR_EDGE_0_RL_WR_0 0x4D48180
156
157#define mmXBAR_EDGE_0_RL_WR_1 0x4D48184
158
159#define mmXBAR_EDGE_0_RL_WR_2 0x4D48188
160
161#define mmXBAR_EDGE_0_RL_WR_3 0x4D4818C
162
163#define mmXBAR_EDGE_0_RL_WR_4 0x4D48190
164
165#define mmXBAR_EDGE_0_RL_WR_5 0x4D48194
166
167#define mmXBAR_EDGE_0_RL_WR_6 0x4D48198
168
169#define mmXBAR_EDGE_0_RL_WR_7 0x4D4819C
170
171#define mmXBAR_EDGE_0_RL_WR_8 0x4D481A0
172
173#define mmXBAR_EDGE_0_RL_WR_9 0x4D481A4
174
175#define mmXBAR_EDGE_0_RL_WR_10 0x4D481A8
176
177#define mmXBAR_EDGE_0_RL_WR_11 0x4D481AC
178
179#define mmXBAR_EDGE_0_E2E_CRDT_SLV_0 0x4D481B0
180
181#define mmXBAR_EDGE_0_E2E_CRDT_SLV_1 0x4D481B4
182
183#define mmXBAR_EDGE_0_E2E_CRDT_SLV_2 0x4D481B8
184
185#define mmXBAR_EDGE_0_E2E_CRDT_DEBUG 0x4D481BC
186
187#define mmXBAR_EDGE_0_UPSCALE 0x4D481C0
188
189#define mmXBAR_EDGE_0_DOWN_CONV 0x4D481C4
190
191#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN 0x4D481D0
192
193#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD 0x4D481D4
194
195#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE 0x4D481D8
196
197#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY 0x4D481DC
198
199#endif /* ASIC_REG_XBAR_EDGE_0_REGS_H_ */