FILE
rot0_qm_regs.h
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linux-6.19.14/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_regs.h
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_ROT0_QM_REGS_H_ 14#define ASIC_REG_ROT0_QM_REGS_H_ 15 16/* 17 ***************************************** 18 * ROT0_QM 19 * (Prototype: QMAN) 20 ***************************************** 21 */ 22 23#define mmROT0_QM_GLBL_CFG0 0x4E0A000 24 25#define mmROT0_QM_GLBL_CFG1 0x4E0A004 26 27#define mmROT0_QM_GLBL_CFG2 0x4E0A008 28 29#define mmROT0_QM_GLBL_ERR_CFG 0x4E0A00C 30 31#define mmROT0_QM_GLBL_ERR_CFG1 0x4E0A010 32 33#define mmROT0_QM_GLBL_ERR_ARC_HALT_EN 0x4E0A014 34 35#define mmROT0_QM_GLBL_AXCACHE 0x4E0A018 36 37#define mmROT0_QM_GLBL_STS0 0x4E0A01C 38 39#define mmROT0_QM_GLBL_STS1 0x4E0A020 40 41#define mmROT0_QM_GLBL_ERR_STS_0 0x4E0A024 42 43#define mmROT0_QM_GLBL_ERR_STS_1 0x4E0A028 44 45#define mmROT0_QM_GLBL_ERR_STS_2 0x4E0A02C 46 47#define mmROT0_QM_GLBL_ERR_STS_3 0x4E0A030 48 49#define mmROT0_QM_GLBL_ERR_STS_4 0x4E0A034 50 51#define mmROT0_QM_GLBL_ERR_MSG_EN_0 0x4E0A038 52 53#define mmROT0_QM_GLBL_ERR_MSG_EN_1 0x4E0A03C 54 55#define mmROT0_QM_GLBL_ERR_MSG_EN_2 0x4E0A040 56 57#define mmROT0_QM_GLBL_ERR_MSG_EN_3 0x4E0A044 58 59#define mmROT0_QM_GLBL_ERR_MSG_EN_4 0x4E0A048 60 61#define mmROT0_QM_GLBL_PROT 0x4E0A04C 62 63#define mmROT0_QM_PQ_BASE_LO_0 0x4E0A050 64 65#define mmROT0_QM_PQ_BASE_LO_1 0x4E0A054 66 67#define mmROT0_QM_PQ_BASE_LO_2 0x4E0A058 68 69#define mmROT0_QM_PQ_BASE_LO_3 0x4E0A05C 70 71#define mmROT0_QM_PQ_BASE_HI_0 0x4E0A060 72 73#define mmROT0_QM_PQ_BASE_HI_1 0x4E0A064 74 75#define mmROT0_QM_PQ_BASE_HI_2 0x4E0A068 76 77#define mmROT0_QM_PQ_BASE_HI_3 0x4E0A06C 78 79#define mmROT0_QM_PQ_SIZE_0 0x4E0A070 80 81#define mmROT0_QM_PQ_SIZE_1 0x4E0A074 82 83#define mmROT0_QM_PQ_SIZE_2 0x4E0A078 84 85#define mmROT0_QM_PQ_SIZE_3 0x4E0A07C 86 87#define mmROT0_QM_PQ_PI_0 0x4E0A080 88 89#define mmROT0_QM_PQ_PI_1 0x4E0A084 90 91#define mmROT0_QM_PQ_PI_2 0x4E0A088 92 93#define mmROT0_QM_PQ_PI_3 0x4E0A08C 94 95#define mmROT0_QM_PQ_CI_0 0x4E0A090 96 97#define mmROT0_QM_PQ_CI_1 0x4E0A094 98 99#define mmROT0_QM_PQ_CI_2 0x4E0A098 100 101#define mmROT0_QM_PQ_CI_3 0x4E0A09C 102 103#define mmROT0_QM_PQ_CFG0_0 0x4E0A0A0 104 105#define mmROT0_QM_PQ_CFG0_1 0x4E0A0A4 106 107#define mmROT0_QM_PQ_CFG0_2 0x4E0A0A8 108 109#define mmROT0_QM_PQ_CFG0_3 0x4E0A0AC 110 111#define mmROT0_QM_PQ_CFG1_0 0x4E0A0B0 112 113#define mmROT0_QM_PQ_CFG1_1 0x4E0A0B4 114 115#define mmROT0_QM_PQ_CFG1_2 0x4E0A0B8 116 117#define mmROT0_QM_PQ_CFG1_3 0x4E0A0BC 118 119#define mmROT0_QM_PQ_STS0_0 0x4E0A0C0 120 121#define mmROT0_QM_PQ_STS0_1 0x4E0A0C4 122 123#define mmROT0_QM_PQ_STS0_2 0x4E0A0C8 124 125#define mmROT0_QM_PQ_STS0_3 0x4E0A0CC 126 127#define mmROT0_QM_PQ_STS1_0 0x4E0A0D0 128 129#define mmROT0_QM_PQ_STS1_1 0x4E0A0D4 130 131#define mmROT0_QM_PQ_STS1_2 0x4E0A0D8 132 133#define mmROT0_QM_PQ_STS1_3 0x4E0A0DC 134 135#define mmROT0_QM_CQ_CFG0_0 0x4E0A0E0 136 137#define mmROT0_QM_CQ_CFG0_1 0x4E0A0E4 138 139#define mmROT0_QM_CQ_CFG0_2 0x4E0A0E8 140 141#define mmROT0_QM_CQ_CFG0_3 0x4E0A0EC 142 143#define mmROT0_QM_CQ_CFG0_4 0x4E0A0F0 144 145#define mmROT0_QM_CQ_STS0_0 0x4E0A0F4 146 147#define mmROT0_QM_CQ_STS0_1 0x4E0A0F8 148 149#define mmROT0_QM_CQ_STS0_2 0x4E0A0FC 150 151#define mmROT0_QM_CQ_STS0_3 0x4E0A100 152 153#define mmROT0_QM_CQ_STS0_4 0x4E0A104 154 155#define mmROT0_QM_CQ_CFG1_0 0x4E0A108 156 157#define mmROT0_QM_CQ_CFG1_1 0x4E0A10C 158 159#define mmROT0_QM_CQ_CFG1_2 0x4E0A110 160 161#define mmROT0_QM_CQ_CFG1_3 0x4E0A114 162 163#define mmROT0_QM_CQ_CFG1_4 0x4E0A118 164 165#define mmROT0_QM_CQ_STS1_0 0x4E0A11C 166 167#define mmROT0_QM_CQ_STS1_1 0x4E0A120 168 169#define mmROT0_QM_CQ_STS1_2 0x4E0A124 170 171#define mmROT0_QM_CQ_STS1_3 0x4E0A128 172 173#define mmROT0_QM_CQ_STS1_4 0x4E0A12C 174 175#define mmROT0_QM_CQ_PTR_LO_0 0x4E0A150 176 177#define mmROT0_QM_CQ_PTR_HI_0 0x4E0A154 178 179#define mmROT0_QM_CQ_TSIZE_0 0x4E0A158 180 181#define mmROT0_QM_CQ_CTL_0 0x4E0A15C 182 183#define mmROT0_QM_CQ_PTR_LO_1 0x4E0A160 184 185#define mmROT0_QM_CQ_PTR_HI_1 0x4E0A164 186 187#define mmROT0_QM_CQ_TSIZE_1 0x4E0A168 188 189#define mmROT0_QM_CQ_CTL_1 0x4E0A16C 190 191#define mmROT0_QM_CQ_PTR_LO_2 0x4E0A170 192 193#define mmROT0_QM_CQ_PTR_HI_2 0x4E0A174 194 195#define mmROT0_QM_CQ_TSIZE_2 0x4E0A178 196 197#define mmROT0_QM_CQ_CTL_2 0x4E0A17C 198 199#define mmROT0_QM_CQ_PTR_LO_3 0x4E0A180 200 201#define mmROT0_QM_CQ_PTR_HI_3 0x4E0A184 202 203#define mmROT0_QM_CQ_TSIZE_3 0x4E0A188 204 205#define mmROT0_QM_CQ_CTL_3 0x4E0A18C 206 207#define mmROT0_QM_CQ_PTR_LO_4 0x4E0A190 208 209#define mmROT0_QM_CQ_PTR_HI_4 0x4E0A194 210 211#define mmROT0_QM_CQ_TSIZE_4 0x4E0A198 212 213#define mmROT0_QM_CQ_CTL_4 0x4E0A19C 214 215#define mmROT0_QM_CQ_TSIZE_STS_0 0x4E0A1A0 216 217#define mmROT0_QM_CQ_TSIZE_STS_1 0x4E0A1A4 218 219#define mmROT0_QM_CQ_TSIZE_STS_2 0x4E0A1A8 220 221#define mmROT0_QM_CQ_TSIZE_STS_3 0x4E0A1AC 222 223#define mmROT0_QM_CQ_TSIZE_STS_4 0x4E0A1B0 224 225#define mmROT0_QM_CQ_PTR_LO_STS_0 0x4E0A1B4 226 227#define mmROT0_QM_CQ_PTR_LO_STS_1 0x4E0A1B8 228 229#define mmROT0_QM_CQ_PTR_LO_STS_2 0x4E0A1BC 230 231#define mmROT0_QM_CQ_PTR_LO_STS_3 0x4E0A1C0 232 233#define mmROT0_QM_CQ_PTR_LO_STS_4 0x4E0A1C4 234 235#define mmROT0_QM_CQ_PTR_HI_STS_0 0x4E0A1C8 236 237#define mmROT0_QM_CQ_PTR_HI_STS_1 0x4E0A1CC 238 239#define mmROT0_QM_CQ_PTR_HI_STS_2 0x4E0A1D0 240 241#define mmROT0_QM_CQ_PTR_HI_STS_3 0x4E0A1D4 242 243#define mmROT0_QM_CQ_PTR_HI_STS_4 0x4E0A1D8 244 245#define mmROT0_QM_CQ_IFIFO_STS_0 0x4E0A1DC 246 247#define mmROT0_QM_CQ_IFIFO_STS_1 0x4E0A1E0 248 249#define mmROT0_QM_CQ_IFIFO_STS_2 0x4E0A1E4 250 251#define mmROT0_QM_CQ_IFIFO_STS_3 0x4E0A1E8 252 253#define mmROT0_QM_CQ_IFIFO_STS_4 0x4E0A1EC 254 255#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_0 0x4E0A1F0 256 257#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_1 0x4E0A1F4 258 259#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_2 0x4E0A1F8 260 261#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_3 0x4E0A1FC 262 263#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_4 0x4E0A200 264 265#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_0 0x4E0A204 266 267#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_1 0x4E0A208 268 269#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_2 0x4E0A20C 270 271#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_3 0x4E0A210 272 273#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_4 0x4E0A214 274 275#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_0 0x4E0A218 276 277#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_1 0x4E0A21C 278 279#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_2 0x4E0A220 280 281#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_3 0x4E0A224 282 283#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_4 0x4E0A228 284 285#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_0 0x4E0A22C 286 287#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_1 0x4E0A230 288 289#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_2 0x4E0A234 290 291#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_3 0x4E0A238 292 293#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_4 0x4E0A23C 294 295#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_0 0x4E0A240 296 297#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_1 0x4E0A244 298 299#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_2 0x4E0A248 300 301#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_3 0x4E0A24C 302 303#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_4 0x4E0A250 304 305#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_0 0x4E0A254 306 307#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_1 0x4E0A258 308 309#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_2 0x4E0A25C 310 311#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_3 0x4E0A260 312 313#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_4 0x4E0A264 314 315#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_0 0x4E0A268 316 317#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_1 0x4E0A26C 318 319#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_2 0x4E0A270 320 321#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_3 0x4E0A274 322 323#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_4 0x4E0A278 324 325#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_0 0x4E0A27C 326 327#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_1 0x4E0A280 328 329#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_2 0x4E0A284 330 331#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_3 0x4E0A288 332 333#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_4 0x4E0A28C 334 335#define mmROT0_QM_CP_FENCE0_RDATA_0 0x4E0A290 336 337#define mmROT0_QM_CP_FENCE0_RDATA_1 0x4E0A294 338 339#define mmROT0_QM_CP_FENCE0_RDATA_2 0x4E0A298 340 341#define mmROT0_QM_CP_FENCE0_RDATA_3 0x4E0A29C 342 343#define mmROT0_QM_CP_FENCE0_RDATA_4 0x4E0A2A0 344 345#define mmROT0_QM_CP_FENCE1_RDATA_0 0x4E0A2A4 346 347#define mmROT0_QM_CP_FENCE1_RDATA_1 0x4E0A2A8 348 349#define mmROT0_QM_CP_FENCE1_RDATA_2 0x4E0A2AC 350 351#define mmROT0_QM_CP_FENCE1_RDATA_3 0x4E0A2B0 352 353#define mmROT0_QM_CP_FENCE1_RDATA_4 0x4E0A2B4 354 355#define mmROT0_QM_CP_FENCE2_RDATA_0 0x4E0A2B8 356 357#define mmROT0_QM_CP_FENCE2_RDATA_1 0x4E0A2BC 358 359#define mmROT0_QM_CP_FENCE2_RDATA_2 0x4E0A2C0 360 361#define mmROT0_QM_CP_FENCE2_RDATA_3 0x4E0A2C4 362 363#define mmROT0_QM_CP_FENCE2_RDATA_4 0x4E0A2C8 364 365#define mmROT0_QM_CP_FENCE3_RDATA_0 0x4E0A2CC 366 367#define mmROT0_QM_CP_FENCE3_RDATA_1 0x4E0A2D0 368 369#define mmROT0_QM_CP_FENCE3_RDATA_2 0x4E0A2D4 370 371#define mmROT0_QM_CP_FENCE3_RDATA_3 0x4E0A2D8 372 373#define mmROT0_QM_CP_FENCE3_RDATA_4 0x4E0A2DC 374 375#define mmROT0_QM_CP_FENCE0_CNT_0 0x4E0A2E0 376 377#define mmROT0_QM_CP_FENCE0_CNT_1 0x4E0A2E4 378 379#define mmROT0_QM_CP_FENCE0_CNT_2 0x4E0A2E8 380 381#define mmROT0_QM_CP_FENCE0_CNT_3 0x4E0A2EC 382 383#define mmROT0_QM_CP_FENCE0_CNT_4 0x4E0A2F0 384 385#define mmROT0_QM_CP_FENCE1_CNT_0 0x4E0A2F4 386 387#define mmROT0_QM_CP_FENCE1_CNT_1 0x4E0A2F8 388 389#define mmROT0_QM_CP_FENCE1_CNT_2 0x4E0A2FC 390 391#define mmROT0_QM_CP_FENCE1_CNT_3 0x4E0A300 392 393#define mmROT0_QM_CP_FENCE1_CNT_4 0x4E0A304 394 395#define mmROT0_QM_CP_FENCE2_CNT_0 0x4E0A308 396 397#define mmROT0_QM_CP_FENCE2_CNT_1 0x4E0A30C 398 399#define mmROT0_QM_CP_FENCE2_CNT_2 0x4E0A310 400 401#define mmROT0_QM_CP_FENCE2_CNT_3 0x4E0A314 402 403#define mmROT0_QM_CP_FENCE2_CNT_4 0x4E0A318 404 405#define mmROT0_QM_CP_FENCE3_CNT_0 0x4E0A31C 406 407#define mmROT0_QM_CP_FENCE3_CNT_1 0x4E0A320 408 409#define mmROT0_QM_CP_FENCE3_CNT_2 0x4E0A324 410 411#define mmROT0_QM_CP_FENCE3_CNT_3 0x4E0A328 412 413#define mmROT0_QM_CP_FENCE3_CNT_4 0x4E0A32C 414 415#define mmROT0_QM_CP_BARRIER_CFG 0x4E0A330 416 417#define mmROT0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x4E0A334 418 419#define mmROT0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x4E0A338 420 421#define mmROT0_QM_CP_LDMA_TSIZE_OFFSET 0x4E0A33C 422 423#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_0 0x4E0A340 424 425#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_1 0x4E0A344 426 427#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_2 0x4E0A348 428 429#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_3 0x4E0A34C 430 431#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_4 0x4E0A350 432 433#define mmROT0_QM_CP_STS_0 0x4E0A368 434 435#define mmROT0_QM_CP_STS_1 0x4E0A36C 436 437#define mmROT0_QM_CP_STS_2 0x4E0A370 438 439#define mmROT0_QM_CP_STS_3 0x4E0A374 440 441#define mmROT0_QM_CP_STS_4 0x4E0A378 442 443#define mmROT0_QM_CP_CURRENT_INST_LO_0 0x4E0A37C 444 445#define mmROT0_QM_CP_CURRENT_INST_LO_1 0x4E0A380 446 447#define mmROT0_QM_CP_CURRENT_INST_LO_2 0x4E0A384 448 449#define mmROT0_QM_CP_CURRENT_INST_LO_3 0x4E0A388 450 451#define mmROT0_QM_CP_CURRENT_INST_LO_4 0x4E0A38C 452 453#define mmROT0_QM_CP_CURRENT_INST_HI_0 0x4E0A390 454 455#define mmROT0_QM_CP_CURRENT_INST_HI_1 0x4E0A394 456 457#define mmROT0_QM_CP_CURRENT_INST_HI_2 0x4E0A398 458 459#define mmROT0_QM_CP_CURRENT_INST_HI_3 0x4E0A39C 460 461#define mmROT0_QM_CP_CURRENT_INST_HI_4 0x4E0A3A0 462 463#define mmROT0_QM_CP_PRED_0 0x4E0A3A4 464 465#define mmROT0_QM_CP_PRED_1 0x4E0A3A8 466 467#define mmROT0_QM_CP_PRED_2 0x4E0A3AC 468 469#define mmROT0_QM_CP_PRED_3 0x4E0A3B0 470 471#define mmROT0_QM_CP_PRED_4 0x4E0A3B4 472 473#define mmROT0_QM_CP_PRED_UPEN_0 0x4E0A3B8 474 475#define mmROT0_QM_CP_PRED_UPEN_1 0x4E0A3BC 476 477#define mmROT0_QM_CP_PRED_UPEN_2 0x4E0A3C0 478 479#define mmROT0_QM_CP_PRED_UPEN_3 0x4E0A3C4 480 481#define mmROT0_QM_CP_PRED_UPEN_4 0x4E0A3C8 482 483#define mmROT0_QM_CP_DBG_0_0 0x4E0A3CC 484 485#define mmROT0_QM_CP_DBG_0_1 0x4E0A3D0 486 487#define mmROT0_QM_CP_DBG_0_2 0x4E0A3D4 488 489#define mmROT0_QM_CP_DBG_0_3 0x4E0A3D8 490 491#define mmROT0_QM_CP_DBG_0_4 0x4E0A3DC 492 493#define mmROT0_QM_CP_CPDMA_UP_CRED_0 0x4E0A3E0 494 495#define mmROT0_QM_CP_CPDMA_UP_CRED_1 0x4E0A3E4 496 497#define mmROT0_QM_CP_CPDMA_UP_CRED_2 0x4E0A3E8 498 499#define mmROT0_QM_CP_CPDMA_UP_CRED_3 0x4E0A3EC 500 501#define mmROT0_QM_CP_CPDMA_UP_CRED_4 0x4E0A3F0 502 503#define mmROT0_QM_CP_IN_DATA_LO_0 0x4E0A3F4 504 505#define mmROT0_QM_CP_IN_DATA_LO_1 0x4E0A3F8 506 507#define mmROT0_QM_CP_IN_DATA_LO_2 0x4E0A3FC 508 509#define mmROT0_QM_CP_IN_DATA_LO_3 0x4E0A400 510 511#define mmROT0_QM_CP_IN_DATA_LO_4 0x4E0A404 512 513#define mmROT0_QM_CP_IN_DATA_HI_0 0x4E0A408 514 515#define mmROT0_QM_CP_IN_DATA_HI_1 0x4E0A40C 516 517#define mmROT0_QM_CP_IN_DATA_HI_2 0x4E0A410 518 519#define mmROT0_QM_CP_IN_DATA_HI_3 0x4E0A414 520 521#define mmROT0_QM_CP_IN_DATA_HI_4 0x4E0A418 522 523#define mmROT0_QM_PQC_HBW_BASE_LO_0 0x4E0A41C 524 525#define mmROT0_QM_PQC_HBW_BASE_LO_1 0x4E0A420 526 527#define mmROT0_QM_PQC_HBW_BASE_LO_2 0x4E0A424 528 529#define mmROT0_QM_PQC_HBW_BASE_LO_3 0x4E0A428 530 531#define mmROT0_QM_PQC_HBW_BASE_HI_0 0x4E0A42C 532 533#define mmROT0_QM_PQC_HBW_BASE_HI_1 0x4E0A430 534 535#define mmROT0_QM_PQC_HBW_BASE_HI_2 0x4E0A434 536 537#define mmROT0_QM_PQC_HBW_BASE_HI_3 0x4E0A438 538 539#define mmROT0_QM_PQC_SIZE_0 0x4E0A43C 540 541#define mmROT0_QM_PQC_SIZE_1 0x4E0A440 542 543#define mmROT0_QM_PQC_SIZE_2 0x4E0A444 544 545#define mmROT0_QM_PQC_SIZE_3 0x4E0A448 546 547#define mmROT0_QM_PQC_PI_0 0x4E0A44C 548 549#define mmROT0_QM_PQC_PI_1 0x4E0A450 550 551#define mmROT0_QM_PQC_PI_2 0x4E0A454 552 553#define mmROT0_QM_PQC_PI_3 0x4E0A458 554 555#define mmROT0_QM_PQC_LBW_WDATA_0 0x4E0A45C 556 557#define mmROT0_QM_PQC_LBW_WDATA_1 0x4E0A460 558 559#define mmROT0_QM_PQC_LBW_WDATA_2 0x4E0A464 560 561#define mmROT0_QM_PQC_LBW_WDATA_3 0x4E0A468 562 563#define mmROT0_QM_PQC_LBW_BASE_LO_0 0x4E0A46C 564 565#define mmROT0_QM_PQC_LBW_BASE_LO_1 0x4E0A470 566 567#define mmROT0_QM_PQC_LBW_BASE_LO_2 0x4E0A474 568 569#define mmROT0_QM_PQC_LBW_BASE_LO_3 0x4E0A478 570 571#define mmROT0_QM_PQC_LBW_BASE_HI_0 0x4E0A47C 572 573#define mmROT0_QM_PQC_LBW_BASE_HI_1 0x4E0A480 574 575#define mmROT0_QM_PQC_LBW_BASE_HI_2 0x4E0A484 576 577#define mmROT0_QM_PQC_LBW_BASE_HI_3 0x4E0A488 578 579#define mmROT0_QM_PQC_CFG 0x4E0A48C 580 581#define mmROT0_QM_PQC_SECURE_PUSH_IND 0x4E0A490 582 583#define mmROT0_QM_ARB_MASK 0x4E0A4A0 584 585#define mmROT0_QM_ARB_CFG_0 0x4E0A4A4 586 587#define mmROT0_QM_ARB_CHOICE_Q_PUSH 0x4E0A4A8 588 589#define mmROT0_QM_ARB_WRR_WEIGHT_0 0x4E0A4AC 590 591#define mmROT0_QM_ARB_WRR_WEIGHT_1 0x4E0A4B0 592 593#define mmROT0_QM_ARB_WRR_WEIGHT_2 0x4E0A4B4 594 595#define mmROT0_QM_ARB_WRR_WEIGHT_3 0x4E0A4B8 596 597#define mmROT0_QM_ARB_CFG_1 0x4E0A4BC 598 599#define mmROT0_QM_ARB_MST_AVAIL_CRED_0 0x4E0A4C0 600 601#define mmROT0_QM_ARB_MST_AVAIL_CRED_1 0x4E0A4C4 602 603#define mmROT0_QM_ARB_MST_AVAIL_CRED_2 0x4E0A4C8 604 605#define mmROT0_QM_ARB_MST_AVAIL_CRED_3 0x4E0A4CC 606 607#define mmROT0_QM_ARB_MST_AVAIL_CRED_4 0x4E0A4D0 608 609#define mmROT0_QM_ARB_MST_AVAIL_CRED_5 0x4E0A4D4 610 611#define mmROT0_QM_ARB_MST_AVAIL_CRED_6 0x4E0A4D8 612 613#define mmROT0_QM_ARB_MST_AVAIL_CRED_7 0x4E0A4DC 614 615#define mmROT0_QM_ARB_MST_AVAIL_CRED_8 0x4E0A4E0 616 617#define mmROT0_QM_ARB_MST_AVAIL_CRED_9 0x4E0A4E4 618 619#define mmROT0_QM_ARB_MST_AVAIL_CRED_10 0x4E0A4E8 620 621#define mmROT0_QM_ARB_MST_AVAIL_CRED_11 0x4E0A4EC 622 623#define mmROT0_QM_ARB_MST_AVAIL_CRED_12 0x4E0A4F0 624 625#define mmROT0_QM_ARB_MST_AVAIL_CRED_13 0x4E0A4F4 626 627#define mmROT0_QM_ARB_MST_AVAIL_CRED_14 0x4E0A4F8 628 629#define mmROT0_QM_ARB_MST_AVAIL_CRED_15 0x4E0A4FC 630 631#define mmROT0_QM_ARB_MST_AVAIL_CRED_16 0x4E0A500 632 633#define mmROT0_QM_ARB_MST_AVAIL_CRED_17 0x4E0A504 634 635#define mmROT0_QM_ARB_MST_AVAIL_CRED_18 0x4E0A508 636 637#define mmROT0_QM_ARB_MST_AVAIL_CRED_19 0x4E0A50C 638 639#define mmROT0_QM_ARB_MST_AVAIL_CRED_20 0x4E0A510 640 641#define mmROT0_QM_ARB_MST_AVAIL_CRED_21 0x4E0A514 642 643#define mmROT0_QM_ARB_MST_AVAIL_CRED_22 0x4E0A518 644 645#define mmROT0_QM_ARB_MST_AVAIL_CRED_23 0x4E0A51C 646 647#define mmROT0_QM_ARB_MST_AVAIL_CRED_24 0x4E0A520 648 649#define mmROT0_QM_ARB_MST_AVAIL_CRED_25 0x4E0A524 650 651#define mmROT0_QM_ARB_MST_AVAIL_CRED_26 0x4E0A528 652 653#define mmROT0_QM_ARB_MST_AVAIL_CRED_27 0x4E0A52C 654 655#define mmROT0_QM_ARB_MST_AVAIL_CRED_28 0x4E0A530 656 657#define mmROT0_QM_ARB_MST_AVAIL_CRED_29 0x4E0A534 658 659#define mmROT0_QM_ARB_MST_AVAIL_CRED_30 0x4E0A538 660 661#define mmROT0_QM_ARB_MST_AVAIL_CRED_31 0x4E0A53C 662 663#define mmROT0_QM_ARB_MST_AVAIL_CRED_32 0x4E0A540 664 665#define mmROT0_QM_ARB_MST_AVAIL_CRED_33 0x4E0A544 666 667#define mmROT0_QM_ARB_MST_AVAIL_CRED_34 0x4E0A548 668 669#define mmROT0_QM_ARB_MST_AVAIL_CRED_35 0x4E0A54C 670 671#define mmROT0_QM_ARB_MST_AVAIL_CRED_36 0x4E0A550 672 673#define mmROT0_QM_ARB_MST_AVAIL_CRED_37 0x4E0A554 674 675#define mmROT0_QM_ARB_MST_AVAIL_CRED_38 0x4E0A558 676 677#define mmROT0_QM_ARB_MST_AVAIL_CRED_39 0x4E0A55C 678 679#define mmROT0_QM_ARB_MST_AVAIL_CRED_40 0x4E0A560 680 681#define mmROT0_QM_ARB_MST_AVAIL_CRED_41 0x4E0A564 682 683#define mmROT0_QM_ARB_MST_AVAIL_CRED_42 0x4E0A568 684 685#define mmROT0_QM_ARB_MST_AVAIL_CRED_43 0x4E0A56C 686 687#define mmROT0_QM_ARB_MST_AVAIL_CRED_44 0x4E0A570 688 689#define mmROT0_QM_ARB_MST_AVAIL_CRED_45 0x4E0A574 690 691#define mmROT0_QM_ARB_MST_AVAIL_CRED_46 0x4E0A578 692 693#define mmROT0_QM_ARB_MST_AVAIL_CRED_47 0x4E0A57C 694 695#define mmROT0_QM_ARB_MST_AVAIL_CRED_48 0x4E0A580 696 697#define mmROT0_QM_ARB_MST_AVAIL_CRED_49 0x4E0A584 698 699#define mmROT0_QM_ARB_MST_AVAIL_CRED_50 0x4E0A588 700 701#define mmROT0_QM_ARB_MST_AVAIL_CRED_51 0x4E0A58C 702 703#define mmROT0_QM_ARB_MST_AVAIL_CRED_52 0x4E0A590 704 705#define mmROT0_QM_ARB_MST_AVAIL_CRED_53 0x4E0A594 706 707#define mmROT0_QM_ARB_MST_AVAIL_CRED_54 0x4E0A598 708 709#define mmROT0_QM_ARB_MST_AVAIL_CRED_55 0x4E0A59C 710 711#define mmROT0_QM_ARB_MST_AVAIL_CRED_56 0x4E0A5A0 712 713#define mmROT0_QM_ARB_MST_AVAIL_CRED_57 0x4E0A5A4 714 715#define mmROT0_QM_ARB_MST_AVAIL_CRED_58 0x4E0A5A8 716 717#define mmROT0_QM_ARB_MST_AVAIL_CRED_59 0x4E0A5AC 718 719#define mmROT0_QM_ARB_MST_AVAIL_CRED_60 0x4E0A5B0 720 721#define mmROT0_QM_ARB_MST_AVAIL_CRED_61 0x4E0A5B4 722 723#define mmROT0_QM_ARB_MST_AVAIL_CRED_62 0x4E0A5B8 724 725#define mmROT0_QM_ARB_MST_AVAIL_CRED_63 0x4E0A5BC 726 727#define mmROT0_QM_ARB_MST_CRED_INC 0x4E0A5E0 728 729#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x4E0A5E4 730 731#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x4E0A5E8 732 733#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x4E0A5EC 734 735#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x4E0A5F0 736 737#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x4E0A5F4 738 739#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x4E0A5F8 740 741#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x4E0A5FC 742 743#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x4E0A600 744 745#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x4E0A604 746 747#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x4E0A608 748 749#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x4E0A60C 750 751#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x4E0A610 752 753#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x4E0A614 754 755#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x4E0A618 756 757#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x4E0A61C 758 759#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x4E0A620 760 761#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x4E0A624 762 763#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x4E0A628 764 765#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x4E0A62C 766 767#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x4E0A630 768 769#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x4E0A634 770 771#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x4E0A638 772 773#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x4E0A63C 774 775#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x4E0A640 776 777#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x4E0A644 778 779#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x4E0A648 780 781#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x4E0A64C 782 783#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x4E0A650 784 785#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x4E0A654 786 787#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x4E0A658 788 789#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x4E0A65C 790 791#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x4E0A660 792 793#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x4E0A664 794 795#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x4E0A668 796 797#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x4E0A66C 798 799#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x4E0A670 800 801#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x4E0A674 802 803#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x4E0A678 804 805#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x4E0A67C 806 807#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x4E0A680 808 809#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x4E0A684 810 811#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x4E0A688 812 813#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x4E0A68C 814 815#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x4E0A690 816 817#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x4E0A694 818 819#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x4E0A698 820 821#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x4E0A69C 822 823#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x4E0A6A0 824 825#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x4E0A6A4 826 827#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x4E0A6A8 828 829#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x4E0A6AC 830 831#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x4E0A6B0 832 833#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x4E0A6B4 834 835#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x4E0A6B8 836 837#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x4E0A6BC 838 839#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x4E0A6C0 840 841#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x4E0A6C4 842 843#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x4E0A6C8 844 845#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x4E0A6CC 846 847#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x4E0A6D0 848 849#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x4E0A6D4 850 851#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x4E0A6D8 852 853#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x4E0A6DC 854 855#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x4E0A6E0 856 857#define mmROT0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x4E0A704 858 859#define mmROT0_QM_ARB_MST_SLAVE_EN 0x4E0A708 860 861#define mmROT0_QM_ARB_MST_SLAVE_EN_1 0x4E0A70C 862 863#define mmROT0_QM_ARB_SLV_CHOICE_WDT 0x4E0A710 864 865#define mmROT0_QM_ARB_SLV_ID 0x4E0A714 866 867#define mmROT0_QM_ARB_MST_QUIET_PER 0x4E0A718 868 869#define mmROT0_QM_ARB_MSG_MAX_INFLIGHT 0x4E0A744 870 871#define mmROT0_QM_ARB_BASE_LO 0x4E0A754 872 873#define mmROT0_QM_ARB_BASE_HI 0x4E0A758 874 875#define mmROT0_QM_ARB_STATE_STS 0x4E0A780 876 877#define mmROT0_QM_ARB_CHOICE_FULLNESS_STS 0x4E0A784 878 879#define mmROT0_QM_ARB_MSG_STS 0x4E0A788 880 881#define mmROT0_QM_ARB_SLV_CHOICE_Q_HEAD 0x4E0A78C 882 883#define mmROT0_QM_ARB_ERR_CAUSE 0x4E0A79C 884 885#define mmROT0_QM_ARB_ERR_MSG_EN 0x4E0A7A0 886 887#define mmROT0_QM_ARB_ERR_STS_DRP 0x4E0A7A8 888 889#define mmROT0_QM_ARB_MST_CRED_STS 0x4E0A7B0 890 891#define mmROT0_QM_ARB_MST_CRED_STS_1 0x4E0A7B4 892 893#define mmROT0_QM_CSMR_STRICT_PRIO_CFG 0x4E0A7FC 894 895#define mmROT0_QM_ARC_CQ_CFG0 0x4E0A800 896 897#define mmROT0_QM_ARC_CQ_CFG1 0x4E0A804 898 899#define mmROT0_QM_ARC_CQ_PTR_LO 0x4E0A808 900 901#define mmROT0_QM_ARC_CQ_PTR_HI 0x4E0A80C 902 903#define mmROT0_QM_ARC_CQ_TSIZE 0x4E0A810 904 905#define mmROT0_QM_ARC_CQ_CTL 0x4E0A814 906 907#define mmROT0_QM_ARC_CQ_IFIFO_STS 0x4E0A81C 908 909#define mmROT0_QM_ARC_CQ_STS0 0x4E0A820 910 911#define mmROT0_QM_ARC_CQ_STS1 0x4E0A824 912 913#define mmROT0_QM_ARC_CQ_TSIZE_STS 0x4E0A828 914 915#define mmROT0_QM_ARC_CQ_PTR_LO_STS 0x4E0A82C 916 917#define mmROT0_QM_ARC_CQ_PTR_HI_STS 0x4E0A830 918 919#define mmROT0_QM_CP_WR_ARC_ADDR_HI 0x4E0A834 920 921#define mmROT0_QM_CP_WR_ARC_ADDR_LO 0x4E0A838 922 923#define mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x4E0A83C 924 925#define mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x4E0A840 926 927#define mmROT0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x4E0A844 928 929#define mmROT0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x4E0A848 930 931#define mmROT0_QM_CQ_IFIFO_MSG_BASE_HI 0x4E0A84C 932 933#define mmROT0_QM_CQ_IFIFO_MSG_BASE_LO 0x4E0A850 934 935#define mmROT0_QM_CQ_CTL_MSG_BASE_HI 0x4E0A854 936 937#define mmROT0_QM_CQ_CTL_MSG_BASE_LO 0x4E0A858 938 939#define mmROT0_QM_ADDR_OVRD 0x4E0A85C 940 941#define mmROT0_QM_CQ_IFIFO_CI_0 0x4E0A860 942 943#define mmROT0_QM_CQ_IFIFO_CI_1 0x4E0A864 944 945#define mmROT0_QM_CQ_IFIFO_CI_2 0x4E0A868 946 947#define mmROT0_QM_CQ_IFIFO_CI_3 0x4E0A86C 948 949#define mmROT0_QM_CQ_IFIFO_CI_4 0x4E0A870 950 951#define mmROT0_QM_ARC_CQ_IFIFO_CI 0x4E0A874 952 953#define mmROT0_QM_CQ_CTL_CI_0 0x4E0A878 954 955#define mmROT0_QM_CQ_CTL_CI_1 0x4E0A87C 956 957#define mmROT0_QM_CQ_CTL_CI_2 0x4E0A880 958 959#define mmROT0_QM_CQ_CTL_CI_3 0x4E0A884 960 961#define mmROT0_QM_CQ_CTL_CI_4 0x4E0A888 962 963#define mmROT0_QM_ARC_CQ_CTL_CI 0x4E0A88C 964 965#define mmROT0_QM_CP_CFG 0x4E0A890 966 967#define mmROT0_QM_CP_EXT_SWITCH 0x4E0A894 968 969#define mmROT0_QM_CP_SWITCH_WD_SET 0x4E0A898 970 971#define mmROT0_QM_CP_SWITCH_WD 0x4E0A89C 972 973#define mmROT0_QM_ARC_LB_ADDR_BASE_LO 0x4E0A8A4 974 975#define mmROT0_QM_ARC_LB_ADDR_BASE_HI 0x4E0A8A8 976 977#define mmROT0_QM_ENGINE_BASE_ADDR_HI 0x4E0A8AC 978 979#define mmROT0_QM_ENGINE_BASE_ADDR_LO 0x4E0A8B0 980 981#define mmROT0_QM_ENGINE_ADDR_RANGE_SIZE 0x4E0A8B4 982 983#define mmROT0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x4E0A8B8 984 985#define mmROT0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x4E0A8BC 986 987#define mmROT0_QM_QM_BASE_ADDR_HI 0x4E0A8C0 988 989#define mmROT0_QM_QM_BASE_ADDR_LO 0x4E0A8C4 990 991#define mmROT0_QM_ARC_PQC_SECURE_PUSH_IND 0x4E0A8C8 992 993#define mmROT0_QM_PQC_STS_0_0 0x4E0A8D0 994 995#define mmROT0_QM_PQC_STS_0_1 0x4E0A8D4 996 997#define mmROT0_QM_PQC_STS_0_2 0x4E0A8D8 998 999#define mmROT0_QM_PQC_STS_0_3 0x4E0A8DC 1000 1001#define mmROT0_QM_PQC_STS_1_0 0x4E0A8E0 1002 1003#define mmROT0_QM_PQC_STS_1_1 0x4E0A8E4 1004 1005#define mmROT0_QM_PQC_STS_1_2 0x4E0A8E8 1006 1007#define mmROT0_QM_PQC_STS_1_3 0x4E0A8EC 1008 1009#define mmROT0_QM_SEI_STATUS 0x4E0A8F0 1010 1011#define mmROT0_QM_SEI_MASK 0x4E0A8F4 1012 1013#define mmROT0_QM_GLBL_ERR_ADDR_LO 0x4E0AD00 1014 1015#define mmROT0_QM_GLBL_ERR_ADDR_HI 0x4E0AD04 1016 1017#define mmROT0_QM_GLBL_ERR_WDATA 0x4E0AD08 1018 1019#define mmROT0_QM_L2H_MASK_LO 0x4E0AD14 1020 1021#define mmROT0_QM_L2H_MASK_HI 0x4E0AD18 1022 1023#define mmROT0_QM_L2H_CMPR_LO 0x4E0AD1C 1024 1025#define mmROT0_QM_L2H_CMPR_HI 0x4E0AD20 1026 1027#define mmROT0_QM_LOCAL_RANGE_BASE 0x4E0AD24 1028 1029#define mmROT0_QM_LOCAL_RANGE_SIZE 0x4E0AD28 1030 1031#define mmROT0_QM_HBW_RD_RATE_LIM_CFG_1 0x4E0AD30 1032 1033#define mmROT0_QM_LBW_WR_RATE_LIM_CFG_0 0x4E0AD34 1034 1035#define mmROT0_QM_LBW_WR_RATE_LIM_CFG_1 0x4E0AD38 1036 1037#define mmROT0_QM_HBW_RD_RATE_LIM_CFG_0 0x4E0AD3C 1038 1039#define mmROT0_QM_IND_GW_APB_CFG 0x4E0AD40 1040 1041#define mmROT0_QM_IND_GW_APB_WDATA 0x4E0AD44 1042 1043#define mmROT0_QM_IND_GW_APB_RDATA 0x4E0AD48 1044 1045#define mmROT0_QM_IND_GW_APB_STATUS 0x4E0AD4C 1046 1047#define mmROT0_QM_PERF_CNT_FREE_LO 0x4E0AD60 1048 1049#define mmROT0_QM_PERF_CNT_FREE_HI 0x4E0AD64 1050 1051#define mmROT0_QM_PERF_CNT_IDLE_LO 0x4E0AD68 1052 1053#define mmROT0_QM_PERF_CNT_IDLE_HI 0x4E0AD6C 1054 1055#define mmROT0_QM_PERF_CNT_CFG 0x4E0AD70 1056 1057#endif /* ASIC_REG_ROT0_QM_REGS_H_ */
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