rot0_qm_arc_aux_regs.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2020 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_
 14#define ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_
 15
 16/*
 17 *****************************************
 18 *   ROT0_QM_ARC_AUX
 19 *   (Prototype: QMAN_ARC_AUX)
 20 *****************************************
 21 */
 22
 23#define mmROT0_QM_ARC_AUX_RUN_HALT_REQ 0x4E08100
 24
 25#define mmROT0_QM_ARC_AUX_RUN_HALT_ACK 0x4E08104
 26
 27#define mmROT0_QM_ARC_AUX_RST_VEC_ADDR 0x4E08108
 28
 29#define mmROT0_QM_ARC_AUX_DBG_MODE 0x4E0810C
 30
 31#define mmROT0_QM_ARC_AUX_CLUSTER_NUM 0x4E08110
 32
 33#define mmROT0_QM_ARC_AUX_ARC_NUM 0x4E08114
 34
 35#define mmROT0_QM_ARC_AUX_WAKE_UP_EVENT 0x4E08118
 36
 37#define mmROT0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x4E0811C
 38
 39#define mmROT0_QM_ARC_AUX_CTI_AP_STS 0x4E08120
 40
 41#define mmROT0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4E08124
 42
 43#define mmROT0_QM_ARC_AUX_ARC_RST 0x4E08128
 44
 45#define mmROT0_QM_ARC_AUX_ARC_RST_REQ 0x4E0812C
 46
 47#define mmROT0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4E08130
 48
 49#define mmROT0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4E08134
 50
 51#define mmROT0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4E08138
 52
 53#define mmROT0_QM_ARC_AUX_PCIE_MSB_ADDR 0x4E0813C
 54
 55#define mmROT0_QM_ARC_AUX_CFG_LSB_ADDR 0x4E08140
 56
 57#define mmROT0_QM_ARC_AUX_CFG_MSB_ADDR 0x4E08144
 58
 59#define mmROT0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4E08150
 60
 61#define mmROT0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4E08154
 62
 63#define mmROT0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4E08158
 64
 65#define mmROT0_QM_ARC_AUX_HBM1_MSB_ADDR 0x4E0815C
 66
 67#define mmROT0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4E08160
 68
 69#define mmROT0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4E08164
 70
 71#define mmROT0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4E08168
 72
 73#define mmROT0_QM_ARC_AUX_HBM3_MSB_ADDR 0x4E0816C
 74
 75#define mmROT0_QM_ARC_AUX_HBM0_OFFSET 0x4E08170
 76
 77#define mmROT0_QM_ARC_AUX_HBM1_OFFSET 0x4E08174
 78
 79#define mmROT0_QM_ARC_AUX_HBM2_OFFSET 0x4E08178
 80
 81#define mmROT0_QM_ARC_AUX_HBM3_OFFSET 0x4E0817C
 82
 83#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4E08180
 84
 85#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4E08184
 86
 87#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4E08188
 88
 89#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x4E0818C
 90
 91#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4E08190
 92
 93#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4E08194
 94
 95#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4E08198
 96
 97#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x4E0819C
 98
 99#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x4E081A0
100
101#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x4E081A4
102
103#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x4E081A8
104
105#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x4E081AC
106
107#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x4E081B0
108
109#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x4E081B4
110
111#define mmROT0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x4E081B8
112
113#define mmROT0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x4E081BC
114
115#define mmROT0_QM_ARC_AUX_CONTEXT_ID_0 0x4E081C0
116
117#define mmROT0_QM_ARC_AUX_CONTEXT_ID_1 0x4E081C4
118
119#define mmROT0_QM_ARC_AUX_CONTEXT_ID_2 0x4E081C8
120
121#define mmROT0_QM_ARC_AUX_CONTEXT_ID_3 0x4E081CC
122
123#define mmROT0_QM_ARC_AUX_CONTEXT_ID_4 0x4E081D0
124
125#define mmROT0_QM_ARC_AUX_CONTEXT_ID_5 0x4E081D4
126
127#define mmROT0_QM_ARC_AUX_CONTEXT_ID_6 0x4E081D8
128
129#define mmROT0_QM_ARC_AUX_CONTEXT_ID_7 0x4E081DC
130
131#define mmROT0_QM_ARC_AUX_CID_OFFSET_0 0x4E081E0
132
133#define mmROT0_QM_ARC_AUX_CID_OFFSET_1 0x4E081E4
134
135#define mmROT0_QM_ARC_AUX_CID_OFFSET_2 0x4E081E8
136
137#define mmROT0_QM_ARC_AUX_CID_OFFSET_3 0x4E081EC
138
139#define mmROT0_QM_ARC_AUX_CID_OFFSET_4 0x4E081F0
140
141#define mmROT0_QM_ARC_AUX_CID_OFFSET_5 0x4E081F4
142
143#define mmROT0_QM_ARC_AUX_CID_OFFSET_6 0x4E081F8
144
145#define mmROT0_QM_ARC_AUX_CID_OFFSET_7 0x4E081FC
146
147#define mmROT0_QM_ARC_AUX_SW_INTR_0 0x4E08200
148
149#define mmROT0_QM_ARC_AUX_SW_INTR_1 0x4E08204
150
151#define mmROT0_QM_ARC_AUX_SW_INTR_2 0x4E08208
152
153#define mmROT0_QM_ARC_AUX_SW_INTR_3 0x4E0820C
154
155#define mmROT0_QM_ARC_AUX_SW_INTR_4 0x4E08210
156
157#define mmROT0_QM_ARC_AUX_SW_INTR_5 0x4E08214
158
159#define mmROT0_QM_ARC_AUX_SW_INTR_6 0x4E08218
160
161#define mmROT0_QM_ARC_AUX_SW_INTR_7 0x4E0821C
162
163#define mmROT0_QM_ARC_AUX_SW_INTR_8 0x4E08220
164
165#define mmROT0_QM_ARC_AUX_SW_INTR_9 0x4E08224
166
167#define mmROT0_QM_ARC_AUX_SW_INTR_10 0x4E08228
168
169#define mmROT0_QM_ARC_AUX_SW_INTR_11 0x4E0822C
170
171#define mmROT0_QM_ARC_AUX_SW_INTR_12 0x4E08230
172
173#define mmROT0_QM_ARC_AUX_SW_INTR_13 0x4E08234
174
175#define mmROT0_QM_ARC_AUX_SW_INTR_14 0x4E08238
176
177#define mmROT0_QM_ARC_AUX_SW_INTR_15 0x4E0823C
178
179#define mmROT0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4E08280
180
181#define mmROT0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4E08284
182
183#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4E08290
184
185#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4E08294
186
187#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4E08298
188
189#define mmROT0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x4E0829C
190
191#define mmROT0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x4E082A0
192
193#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x4E082A4
194
195#define mmROT0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x4E082A8
196
197#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_STS 0x4E082B0
198
199#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x4E082B4
200
201#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x4E082B8
202
203#define mmROT0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x4E082BC
204
205#define mmROT0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x4E082C0
206
207#define mmROT0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x4E082C4
208
209#define mmROT0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x4E082C8
210
211#define mmROT0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x4E082CC
212
213#define mmROT0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x4E082D0
214
215#define mmROT0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x4E082E0
216
217#define mmROT0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x4E082E4
218
219#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x4E082E8
220
221#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x4E082EC
222
223#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x4E082F0
224
225#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x4E082F4
226
227#define mmROT0_QM_ARC_AUX_SCRATCHPAD_0 0x4E08300
228
229#define mmROT0_QM_ARC_AUX_SCRATCHPAD_1 0x4E08304
230
231#define mmROT0_QM_ARC_AUX_SCRATCHPAD_2 0x4E08308
232
233#define mmROT0_QM_ARC_AUX_SCRATCHPAD_3 0x4E0830C
234
235#define mmROT0_QM_ARC_AUX_SCRATCHPAD_4 0x4E08310
236
237#define mmROT0_QM_ARC_AUX_SCRATCHPAD_5 0x4E08314
238
239#define mmROT0_QM_ARC_AUX_SCRATCHPAD_6 0x4E08318
240
241#define mmROT0_QM_ARC_AUX_SCRATCHPAD_7 0x4E0831C
242
243#define mmROT0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4E08320
244
245#define mmROT0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4E08324
246
247#define mmROT0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4E08328
248
249#define mmROT0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x4E0832C
250
251#define mmROT0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4E08330
252
253#define mmROT0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4E08334
254
255#define mmROT0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4E08338
256
257#define mmROT0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x4E0833C
258
259#define mmROT0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4E08350
260
261#define mmROT0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4E08354
262
263#define mmROT0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4E08358
264
265#define mmROT0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x4E0835C
266
267#define mmROT0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4E08360
268
269#define mmROT0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4E08364
270
271#define mmROT0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4E08368
272
273#define mmROT0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x4E0836C
274
275#define mmROT0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4E08370
276
277#define mmROT0_QM_ARC_AUX_CBU_LOCK_OVR 0x4E08374
278
279#define mmROT0_QM_ARC_AUX_CBU_PROT_OVR 0x4E08378
280
281#define mmROT0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x4E0837C
282
283#define mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4E08380
284
285#define mmROT0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4E08384
286
287#define mmROT0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x4E0838C
288
289#define mmROT0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4E08390
290
291#define mmROT0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4E08400
292
293#define mmROT0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4E08404
294
295#define mmROT0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4E08408
296
297#define mmROT0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x4E0840C
298
299#define mmROT0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4E08420
300
301#define mmROT0_QM_ARC_AUX_LBU_LOCK_OVR 0x4E08424
302
303#define mmROT0_QM_ARC_AUX_LBU_PROT_OVR 0x4E08428
304
305#define mmROT0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x4E0842C
306
307#define mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4E08430
308
309#define mmROT0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4E08434
310
311#define mmROT0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x4E0843C
312
313#define mmROT0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4E08440
314
315#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4E08500
316
317#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4E08504
318
319#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4E08508
320
321#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x4E0850C
322
323#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4E08510
324
325#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4E08514
326
327#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4E08518
328
329#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x4E0851C
330
331#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4E08520
332
333#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4E08524
334
335#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4E08528
336
337#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x4E0852C
338
339#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4E08530
340
341#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4E08534
342
343#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4E08538
344
345#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x4E0853C
346
347#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4E08540
348
349#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4E08544
350
351#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4E08548
352
353#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x4E0854C
354
355#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4E08550
356
357#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4E08554
358
359#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4E08558
360
361#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x4E0855C
362
363#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4E08560
364
365#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4E08564
366
367#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4E08568
368
369#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x4E0856C
370
371#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4E08570
372
373#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4E08574
374
375#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4E08578
376
377#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x4E0857C
378
379#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4E08580
380
381#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4E08584
382
383#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4E08588
384
385#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x4E0858C
386
387#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4E08590
388
389#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4E08594
390
391#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4E08598
392
393#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x4E0859C
394
395#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x4E085A0
396
397#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x4E085A4
398
399#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x4E085A8
400
401#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x4E085AC
402
403#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x4E085B0
404
405#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x4E085B4
406
407#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x4E085B8
408
409#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x4E085BC
410
411#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x4E085C0
412
413#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x4E085C4
414
415#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x4E085C8
416
417#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x4E085CC
418
419#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x4E085D0
420
421#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x4E085D4
422
423#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x4E085D8
424
425#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x4E085DC
426
427#define mmROT0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x4E085E0
428
429#define mmROT0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x4E085E4
430
431#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4E08620
432
433#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4E08624
434
435#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4E08628
436
437#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4E08630
438
439#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4E08634
440
441#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4E08638
442
443#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x4E0863C
444
445#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4E08640
446
447#define mmROT0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4E08644
448
449#define mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4E08648
450
451#define mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x4E0864C
452
453#define mmROT0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4E08650
454
455#define mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4E08654
456
457#define mmROT0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4E08658
458
459#define mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x4E0865C
460
461#define mmROT0_QM_ARC_AUX_AUX2APB_PROT 0x4E08700
462
463#define mmROT0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4E08704
464
465#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4E08708
466
467#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x4E0870C
468
469#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4E08710
470
471#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4E08714
472
473#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4E08718
474
475#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x4E0871C
476
477#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4E08720
478
479#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4E08724
480
481#define mmROT0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4E08728
482
483#define mmROT0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x4E0872C
484
485#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4E08730
486
487#define mmROT0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4E08734
488
489#define mmROT0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4E08738
490
491#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x4E0873C
492
493#define mmROT0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4E08740
494
495#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4E08750
496
497#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4E08754
498
499#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4E08758
500
501#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x4E0875C
502
503#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4E08760
504
505#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4E08764
506
507#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4E08768
508
509#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x4E0876C
510
511#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4E08770
512
513#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4E08774
514
515#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4E08778
516
517#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x4E0877C
518
519#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4E08780
520
521#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4E08784
522
523#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4E08788
524
525#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x4E0878C
526
527#define mmROT0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4E08790
528
529#define mmROT0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4E08794
530
531#define mmROT0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4E08798
532
533#define mmROT0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x4E0879C
534
535#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4E08800
536
537#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4E08804
538
539#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4E08808
540
541#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_3 0x4E0880C
542
543#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4E08810
544
545#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4E08814
546
547#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4E08818
548
549#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_7 0x4E0881C
550
551#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4E08820
552
553#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4E08824
554
555#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4E08828
556
557#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_11 0x4E0882C
558
559#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4E08830
560
561#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4E08834
562
563#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4E08838
564
565#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_15 0x4E0883C
566
567#define mmROT0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4E08840
568
569#define mmROT0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4E08844
570
571#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4E08848
572
573#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x4E0884C
574
575#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4E08850
576
577#define mmROT0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4E08854
578
579#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4E08900
580
581#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4E08904
582
583#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4E08908
584
585#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x4E0890C
586
587#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4E08910
588
589#define mmROT0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4E08920
590
591#endif /* ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_ */