rot0_masks.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2020 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_ROT0_MASKS_H_
 14#define ASIC_REG_ROT0_MASKS_H_
 15
 16/*
 17 *****************************************
 18 *   ROT0
 19 *   (Prototype: ROTATOR)
 20 *****************************************
 21 */
 22
 23/* ROT0_KMD_MODE */
 24#define ROT0_KMD_MODE_EN_SHIFT 0
 25#define ROT0_KMD_MODE_EN_MASK 0x1
 26
 27/* ROT0_CPL_QUEUE_EN */
 28#define ROT0_CPL_QUEUE_EN_Q_EN_SHIFT 0
 29#define ROT0_CPL_QUEUE_EN_Q_EN_MASK 0x1
 30
 31/* ROT0_CPL_QUEUE_ADDR_L */
 32#define ROT0_CPL_QUEUE_ADDR_L_VAL_SHIFT 0
 33#define ROT0_CPL_QUEUE_ADDR_L_VAL_MASK 0xFFFFFFFF
 34
 35/* ROT0_CPL_QUEUE_ADDR_H */
 36#define ROT0_CPL_QUEUE_ADDR_H_VAL_SHIFT 0
 37#define ROT0_CPL_QUEUE_ADDR_H_VAL_MASK 0xFFFFFFFF
 38
 39/* ROT0_CPL_QUEUE_DATA */
 40#define ROT0_CPL_QUEUE_DATA_VAL_SHIFT 0
 41#define ROT0_CPL_QUEUE_DATA_VAL_MASK 0xFFFFFFFF
 42
 43/* ROT0_CPL_QUEUE_AWUSER */
 44#define ROT0_CPL_QUEUE_AWUSER_VAL_SHIFT 0
 45#define ROT0_CPL_QUEUE_AWUSER_VAL_MASK 0xFFFFFFFF
 46
 47/* ROT0_CPL_QUEUE_AXI */
 48#define ROT0_CPL_QUEUE_AXI_CACHE_SHIFT 0
 49#define ROT0_CPL_QUEUE_AXI_CACHE_MASK 0xF
 50#define ROT0_CPL_QUEUE_AXI_PROT_SHIFT 4
 51#define ROT0_CPL_QUEUE_AXI_PROT_MASK 0x70
 52
 53/* ROT0_CPL_MSG_THRESHOLD */
 54#define ROT0_CPL_MSG_THRESHOLD_VAL_SHIFT 0
 55#define ROT0_CPL_MSG_THRESHOLD_VAL_MASK 0x3F
 56
 57/* ROT0_CPL_MSG_AXI */
 58#define ROT0_CPL_MSG_AXI_CACHE_SHIFT 0
 59#define ROT0_CPL_MSG_AXI_CACHE_MASK 0xF
 60#define ROT0_CPL_MSG_AXI_PROT_SHIFT 4
 61#define ROT0_CPL_MSG_AXI_PROT_MASK 0x70
 62
 63/* ROT0_AXI_WB */
 64#define ROT0_AXI_WB_CACHE_SHIFT 0
 65#define ROT0_AXI_WB_CACHE_MASK 0xF
 66#define ROT0_AXI_WB_PROT_SHIFT 4
 67#define ROT0_AXI_WB_PROT_MASK 0x70
 68
 69/* ROT0_ERR_CFG */
 70#define ROT0_ERR_CFG_STOP_ON_ERR_SHIFT 0
 71#define ROT0_ERR_CFG_STOP_ON_ERR_MASK 0x1
 72
 73/* ROT0_ERR_STATUS */
 74#define ROT0_ERR_STATUS_ROT_HBW_RD_SHIFT 0
 75#define ROT0_ERR_STATUS_ROT_HBW_RD_MASK 0x1
 76#define ROT0_ERR_STATUS_ROT_HBW_WR_SHIFT 1
 77#define ROT0_ERR_STATUS_ROT_HBW_WR_MASK 0x2
 78#define ROT0_ERR_STATUS_QMAN_HBW_RD_SHIFT 2
 79#define ROT0_ERR_STATUS_QMAN_HBW_RD_MASK 0x4
 80#define ROT0_ERR_STATUS_QMAN_HBW_WR_SHIFT 3
 81#define ROT0_ERR_STATUS_QMAN_HBW_WR_MASK 0x8
 82#define ROT0_ERR_STATUS_ROT_LBW_WR_SHIFT 4
 83#define ROT0_ERR_STATUS_ROT_LBW_WR_MASK 0x10
 84
 85/* ROT0_WBC_MAX_OUTSTANDING */
 86#define ROT0_WBC_MAX_OUTSTANDING_VAL_SHIFT 0
 87#define ROT0_WBC_MAX_OUTSTANDING_VAL_MASK 0xFFFF
 88
 89/* ROT0_WBC_RL */
 90#define ROT0_WBC_RL_SATURATION_SHIFT 0
 91#define ROT0_WBC_RL_SATURATION_MASK 0xFF
 92#define ROT0_WBC_RL_TIMEOUT_SHIFT 8
 93#define ROT0_WBC_RL_TIMEOUT_MASK 0xFF00
 94#define ROT0_WBC_RL_RST_TOKEN_SHIFT 16
 95#define ROT0_WBC_RL_RST_TOKEN_MASK 0xFF0000
 96#define ROT0_WBC_RL_RATE_LIMITER_EN_SHIFT 24
 97#define ROT0_WBC_RL_RATE_LIMITER_EN_MASK 0x1000000
 98
 99/* ROT0_WBC_INFLIGHTS */
100#define ROT0_WBC_INFLIGHTS_VAL_SHIFT 0
101#define ROT0_WBC_INFLIGHTS_VAL_MASK 0xFFFF
102
103/* ROT0_WBC_INFO */
104#define ROT0_WBC_INFO_EMPTY_SHIFT 0
105#define ROT0_WBC_INFO_EMPTY_MASK 0x1
106#define ROT0_WBC_INFO_AXI_IDLE_SHIFT 1
107#define ROT0_WBC_INFO_AXI_IDLE_MASK 0x2
108
109/* ROT0_WBC_MON */
110#define ROT0_WBC_MON_CNT_SHIFT 0
111#define ROT0_WBC_MON_CNT_MASK 0x1
112#define ROT0_WBC_MON_TS_SHIFT 8
113#define ROT0_WBC_MON_TS_MASK 0x300
114#define ROT0_WBC_MON_CONTEXT_ID_SHIFT 16
115#define ROT0_WBC_MON_CONTEXT_ID_MASK 0xFFFF0000
116
117/* ROT0_RSB_CAM_MAX_SIZE */
118#define ROT0_RSB_CAM_MAX_SIZE_DATA_SHIFT 0
119#define ROT0_RSB_CAM_MAX_SIZE_DATA_MASK 0xFFFF
120#define ROT0_RSB_CAM_MAX_SIZE_MD_SHIFT 16
121#define ROT0_RSB_CAM_MAX_SIZE_MD_MASK 0xFFFF0000
122
123/* ROT0_RSB_CFG */
124#define ROT0_RSB_CFG_CACHE_DISABLE_SHIFT 0
125#define ROT0_RSB_CFG_CACHE_DISABLE_MASK 0x1
126#define ROT0_RSB_CFG_ENABLE_CGATE_SHIFT 1
127#define ROT0_RSB_CFG_ENABLE_CGATE_MASK 0x2
128
129/* ROT0_RSB_MAX_OS */
130#define ROT0_RSB_MAX_OS_VAL_SHIFT 0
131#define ROT0_RSB_MAX_OS_VAL_MASK 0xFFFF
132
133/* ROT0_RSB_RL */
134#define ROT0_RSB_RL_SATURATION_SHIFT 0
135#define ROT0_RSB_RL_SATURATION_MASK 0xFF
136#define ROT0_RSB_RL_TIMEOUT_SHIFT 8
137#define ROT0_RSB_RL_TIMEOUT_MASK 0xFF00
138#define ROT0_RSB_RL_RST_TOKEN_SHIFT 16
139#define ROT0_RSB_RL_RST_TOKEN_MASK 0xFF0000
140#define ROT0_RSB_RL_RATE_LIMITER_EN_SHIFT 24
141#define ROT0_RSB_RL_RATE_LIMITER_EN_MASK 0x1000000
142
143/* ROT0_RSB_INFLIGHTS */
144#define ROT0_RSB_INFLIGHTS_VAL_SHIFT 0
145#define ROT0_RSB_INFLIGHTS_VAL_MASK 0xFFFFFFFF
146
147/* ROT0_RSB_OCCUPANCY */
148#define ROT0_RSB_OCCUPANCY_VAL_SHIFT 0
149#define ROT0_RSB_OCCUPANCY_VAL_MASK 0xFFFFFFFF
150
151/* ROT0_RSB_INFO */
152#define ROT0_RSB_INFO_EMPTY_SHIFT 0
153#define ROT0_RSB_INFO_EMPTY_MASK 0x1
154#define ROT0_RSB_INFO_AXI_IDLE_SHIFT 1
155#define ROT0_RSB_INFO_AXI_IDLE_MASK 0x2
156
157/* ROT0_RSB_MON */
158#define ROT0_RSB_MON_CNT_SHIFT 0
159#define ROT0_RSB_MON_CNT_MASK 0x1FFF
160#define ROT0_RSB_MON_TS_SHIFT 16
161#define ROT0_RSB_MON_TS_MASK 0x30000
162
163/* ROT0_RSB_MON_CONTEXT_ID */
164#define ROT0_RSB_MON_CONTEXT_ID_VAL_SHIFT 0
165#define ROT0_RSB_MON_CONTEXT_ID_VAL_MASK 0xFFFFFFFF
166
167/* ROT0_MSS_HALT */
168#define ROT0_MSS_HALT_VAL_SHIFT 0
169#define ROT0_MSS_HALT_VAL_MASK 0x7
170
171/* ROT0_MSS_SEI_STATUS */
172#define ROT0_MSS_SEI_STATUS_I0_SHIFT 0
173#define ROT0_MSS_SEI_STATUS_I0_MASK 0x1
174#define ROT0_MSS_SEI_STATUS_I1_SHIFT 1
175#define ROT0_MSS_SEI_STATUS_I1_MASK 0x2
176#define ROT0_MSS_SEI_STATUS_I2_SHIFT 2
177#define ROT0_MSS_SEI_STATUS_I2_MASK 0x4
178#define ROT0_MSS_SEI_STATUS_I3_SHIFT 3
179#define ROT0_MSS_SEI_STATUS_I3_MASK 0x8
180#define ROT0_MSS_SEI_STATUS_I4_SHIFT 4
181#define ROT0_MSS_SEI_STATUS_I4_MASK 0x10
182#define ROT0_MSS_SEI_STATUS_I5_SHIFT 5
183#define ROT0_MSS_SEI_STATUS_I5_MASK 0x20
184#define ROT0_MSS_SEI_STATUS_I6_SHIFT 6
185#define ROT0_MSS_SEI_STATUS_I6_MASK 0x40
186#define ROT0_MSS_SEI_STATUS_I7_SHIFT 7
187#define ROT0_MSS_SEI_STATUS_I7_MASK 0x80
188#define ROT0_MSS_SEI_STATUS_I8_SHIFT 8
189#define ROT0_MSS_SEI_STATUS_I8_MASK 0x100
190#define ROT0_MSS_SEI_STATUS_I9_SHIFT 9
191#define ROT0_MSS_SEI_STATUS_I9_MASK 0x200
192#define ROT0_MSS_SEI_STATUS_I10_SHIFT 10
193#define ROT0_MSS_SEI_STATUS_I10_MASK 0x400
194#define ROT0_MSS_SEI_STATUS_I11_SHIFT 11
195#define ROT0_MSS_SEI_STATUS_I11_MASK 0x800
196#define ROT0_MSS_SEI_STATUS_I12_SHIFT 12
197#define ROT0_MSS_SEI_STATUS_I12_MASK 0x1000
198#define ROT0_MSS_SEI_STATUS_I13_SHIFT 13
199#define ROT0_MSS_SEI_STATUS_I13_MASK 0x2000
200#define ROT0_MSS_SEI_STATUS_I14_SHIFT 14
201#define ROT0_MSS_SEI_STATUS_I14_MASK 0x4000
202#define ROT0_MSS_SEI_STATUS_I15_SHIFT 15
203#define ROT0_MSS_SEI_STATUS_I15_MASK 0x8000
204#define ROT0_MSS_SEI_STATUS_I16_SHIFT 16
205#define ROT0_MSS_SEI_STATUS_I16_MASK 0x10000
206#define ROT0_MSS_SEI_STATUS_I17_SHIFT 17
207#define ROT0_MSS_SEI_STATUS_I17_MASK 0x20000
208#define ROT0_MSS_SEI_STATUS_I18_SHIFT 18
209#define ROT0_MSS_SEI_STATUS_I18_MASK 0x40000
210#define ROT0_MSS_SEI_STATUS_I19_SHIFT 19
211#define ROT0_MSS_SEI_STATUS_I19_MASK 0x80000
212#define ROT0_MSS_SEI_STATUS_I20_SHIFT 20
213#define ROT0_MSS_SEI_STATUS_I20_MASK 0x100000
214#define ROT0_MSS_SEI_STATUS_I21_SHIFT 21
215#define ROT0_MSS_SEI_STATUS_I21_MASK 0x200000
216
217/* ROT0_MSS_SEI_MASK */
218#define ROT0_MSS_SEI_MASK_VAL_SHIFT 0
219#define ROT0_MSS_SEI_MASK_VAL_MASK 0x3FFFFF
220
221/* ROT0_MSS_SPI_STATUS */
222#define ROT0_MSS_SPI_STATUS_I0_SHIFT 0
223#define ROT0_MSS_SPI_STATUS_I0_MASK 0x1
224#define ROT0_MSS_SPI_STATUS_I1_SHIFT 1
225#define ROT0_MSS_SPI_STATUS_I1_MASK 0x2
226#define ROT0_MSS_SPI_STATUS_I2_SHIFT 2
227#define ROT0_MSS_SPI_STATUS_I2_MASK 0x4
228#define ROT0_MSS_SPI_STATUS_I3_SHIFT 3
229#define ROT0_MSS_SPI_STATUS_I3_MASK 0x8
230#define ROT0_MSS_SPI_STATUS_I4_SHIFT 4
231#define ROT0_MSS_SPI_STATUS_I4_MASK 0x10
232#define ROT0_MSS_SPI_STATUS_I5_SHIFT 5
233#define ROT0_MSS_SPI_STATUS_I5_MASK 0x20
234#define ROT0_MSS_SPI_STATUS_I6_SHIFT 6
235#define ROT0_MSS_SPI_STATUS_I6_MASK 0x40
236#define ROT0_MSS_SPI_STATUS_I7_SHIFT 7
237#define ROT0_MSS_SPI_STATUS_I7_MASK 0x80
238
239/* ROT0_MSS_SPI_MASK */
240#define ROT0_MSS_SPI_MASK_VAL_SHIFT 0
241#define ROT0_MSS_SPI_MASK_VAL_MASK 0xFF
242
243/* ROT0_DISABLE_PAD_CALC */
244#define ROT0_DISABLE_PAD_CALC_VAL_SHIFT 0
245#define ROT0_DISABLE_PAD_CALC_VAL_MASK 0x3
246
247/* ROT0_QMAN_CFG */
248#define ROT0_QMAN_CFG_FORCE_STOP_SHIFT 0
249#define ROT0_QMAN_CFG_FORCE_STOP_MASK 0x1
250
251/* ROT0_CLK_EN */
252#define ROT0_CLK_EN_LBW_CFG_DIS_SHIFT 0
253#define ROT0_CLK_EN_LBW_CFG_DIS_MASK 0x1
254#define ROT0_CLK_EN_DBG_CFG_DIS_SHIFT 4
255#define ROT0_CLK_EN_DBG_CFG_DIS_MASK 0x10
256#define ROT0_CLK_EN_SB_EMPTY_MASK_SHIFT 5
257#define ROT0_CLK_EN_SB_EMPTY_MASK_MASK 0x20
258
259/* ROT0_MRSB_CAM_MAX_SIZE */
260#define ROT0_MRSB_CAM_MAX_SIZE_DATA_SHIFT 0
261#define ROT0_MRSB_CAM_MAX_SIZE_DATA_MASK 0xFFFF
262#define ROT0_MRSB_CAM_MAX_SIZE_MD_SHIFT 16
263#define ROT0_MRSB_CAM_MAX_SIZE_MD_MASK 0xFFFF0000
264
265/* ROT0_MRSB_CFG */
266#define ROT0_MRSB_CFG_CACHE_DISABLE_SHIFT 0
267#define ROT0_MRSB_CFG_CACHE_DISABLE_MASK 0x1
268#define ROT0_MRSB_CFG_ENABLE_CGATE_SHIFT 1
269#define ROT0_MRSB_CFG_ENABLE_CGATE_MASK 0x2
270
271/* ROT0_MRSB_MAX_OS */
272#define ROT0_MRSB_MAX_OS_VAL_SHIFT 0
273#define ROT0_MRSB_MAX_OS_VAL_MASK 0xFFFF
274
275/* ROT0_MRSB_RL */
276#define ROT0_MRSB_RL_SATURATION_SHIFT 0
277#define ROT0_MRSB_RL_SATURATION_MASK 0xFF
278#define ROT0_MRSB_RL_TIMEOUT_SHIFT 8
279#define ROT0_MRSB_RL_TIMEOUT_MASK 0xFF00
280#define ROT0_MRSB_RL_RST_TOKEN_SHIFT 16
281#define ROT0_MRSB_RL_RST_TOKEN_MASK 0xFF0000
282#define ROT0_MRSB_RL_RATE_LIMITER_EN_SHIFT 24
283#define ROT0_MRSB_RL_RATE_LIMITER_EN_MASK 0x1000000
284
285/* ROT0_MRSB_INFLIGHTS */
286#define ROT0_MRSB_INFLIGHTS_VAL_SHIFT 0
287#define ROT0_MRSB_INFLIGHTS_VAL_MASK 0xFFFFFFFF
288
289/* ROT0_MRSB_OCCUPANCY */
290#define ROT0_MRSB_OCCUPANCY_VAL_SHIFT 0
291#define ROT0_MRSB_OCCUPANCY_VAL_MASK 0xFFFFFFFF
292
293/* ROT0_MRSB_INFO */
294#define ROT0_MRSB_INFO_EMPTY_SHIFT 0
295#define ROT0_MRSB_INFO_EMPTY_MASK 0x1
296#define ROT0_MRSB_INFO_AXI_IDLE_SHIFT 1
297#define ROT0_MRSB_INFO_AXI_IDLE_MASK 0x2
298
299/* ROT0_MRSB_MON */
300#define ROT0_MRSB_MON_CNT_SHIFT 0
301#define ROT0_MRSB_MON_CNT_MASK 0x1FFF
302#define ROT0_MRSB_MON_TS_SHIFT 16
303#define ROT0_MRSB_MON_TS_MASK 0x30000
304
305/* ROT0_MRSB_MON_CONTEXT_ID */
306#define ROT0_MRSB_MON_CONTEXT_ID_VAL_SHIFT 0
307#define ROT0_MRSB_MON_CONTEXT_ID_VAL_MASK 0xFFFFFFFF
308
309/* ROT0_MSS_STS */
310#define ROT0_MSS_STS_IS_HALT_SHIFT 0
311#define ROT0_MSS_STS_IS_HALT_MASK 0x1
312
313#endif /* ASIC_REG_ROT0_MASKS_H_ */