FILE
psoc_global_conf_regs.h
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linux-6.19.14/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_regs.h
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ 14#define ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ 15 16/* 17 ***************************************** 18 * PSOC_GLOBAL_CONF 19 * (Prototype: GLOBAL_CONF) 20 ***************************************** 21 */ 22 23#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0 0x4C4B000 24 25#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_1 0x4C4B004 26 27#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_2 0x4C4B008 28 29#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 0x4C4B00C 30 31#define mmPSOC_GLOBAL_CONF_PCI_FW_FSM 0x4C4B020 32 33#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START 0x4C4B024 34 35#define mmPSOC_GLOBAL_CONF_BTM_FSM 0x4C4B028 36 37#define mmPSOC_GLOBAL_CONF_BTL_ROM_DELAY 0x4C4B02C 38 39#define mmPSOC_GLOBAL_CONF_SW_BTM_FSM 0x4C4B030 40 41#define mmPSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM 0x4C4B034 42 43#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT 0x4C4B038 44 45#define mmPSOC_GLOBAL_CONF_QSPI_SPI 0x4C4B03C 46 47#define mmPSOC_GLOBAL_CONF_SPI_MEM_EN 0x4C4B040 48 49#define mmPSOC_GLOBAL_CONF_PRSTN 0x4C4B044 50 51#define mmPSOC_GLOBAL_CONF_PCIE_EN 0x4C4B048 52 53#define mmPSOC_GLOBAL_CONF_PCIE_PRSTN_INTR 0x4C4B04C 54 55#define mmPSOC_GLOBAL_CONF_SPI_IMG_STS 0x4C4B050 56 57#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_FSM 0x4C4B054 58 59#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD 0x4C4B058 60 61#define mmPSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST 0x4C4B05C 62 63#define mmPSOC_GLOBAL_CONF_PHY_STABLE 0x4C4B060 64 65#define mmPSOC_GLOBAL_CONF_PRSTN_OVR 0x4C4B064 66 67#define mmPSOC_GLOBAL_CONF_ETR_FLUSH 0x4C4B068 68 69#define mmPSOC_GLOBAL_CONF_ANY_RST 0x4C4B06C 70 71#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0 0x4C4B070 72 73#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 0x4C4B074 74 75#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 0x4C4B078 76 77#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 0x4C4B07C 78 79#define mmPSOC_GLOBAL_CONF_DIS_RAZWI_ERR 0x4C4B080 80 81#define mmPSOC_GLOBAL_CONF_PCIE_PHY_RST_N 0x4C4B084 82 83#define mmPSOC_GLOBAL_CONF_RAZWI_INTERRUPT 0x4C4B088 84 85#define mmPSOC_GLOBAL_CONF_RAZWI_MASK_INFO 0x4C4B08C 86 87#define mmPSOC_GLOBAL_CONF_BTL_PROT 0x4C4B090 88 89#define mmPSOC_GLOBAL_CONF_BTL_ADDR_EXT 0x4C4B094 90 91#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TO 0x4C4B098 92 93#define mmPSOC_GLOBAL_CONF_RESET_DELAYS 0x4C4B09C 94 95#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 0x4C4B100 96 97#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 0x4C4B104 98 99#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 0x4C4B108 100 101#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 0x4C4B10C 102 103#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 0x4C4B110 104 105#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 0x4C4B114 106 107#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 0x4C4B118 108 109#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 0x4C4B11C 110 111#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 0x4C4B120 112 113#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 0x4C4B124 114 115#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 0x4C4B128 116 117#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 0x4C4B12C 118 119#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 0x4C4B130 120 121#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 0x4C4B134 122 123#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 0x4C4B138 124 125#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 0x4C4B13C 126 127#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_16 0x4C4B140 128 129#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_17 0x4C4B144 130 131#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 0x4C4B148 132 133#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 0x4C4B14C 134 135#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 0x4C4B150 136 137#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 0x4C4B154 138 139#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 0x4C4B158 140 141#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 0x4C4B15C 142 143#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 0x4C4B160 144 145#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 0x4C4B164 146 147#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 0x4C4B168 148 149#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 0x4C4B16C 150 151#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 0x4C4B170 152 153#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 0x4C4B174 154 155#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 0x4C4B178 156 157#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 0x4C4B17C 158 159#define mmPSOC_GLOBAL_CONF_SEMAPHORE_0 0x4C4B200 160 161#define mmPSOC_GLOBAL_CONF_SEMAPHORE_1 0x4C4B204 162 163#define mmPSOC_GLOBAL_CONF_SEMAPHORE_2 0x4C4B208 164 165#define mmPSOC_GLOBAL_CONF_SEMAPHORE_3 0x4C4B20C 166 167#define mmPSOC_GLOBAL_CONF_SEMAPHORE_4 0x4C4B210 168 169#define mmPSOC_GLOBAL_CONF_SEMAPHORE_5 0x4C4B214 170 171#define mmPSOC_GLOBAL_CONF_SEMAPHORE_6 0x4C4B218 172 173#define mmPSOC_GLOBAL_CONF_SEMAPHORE_7 0x4C4B21C 174 175#define mmPSOC_GLOBAL_CONF_SEMAPHORE_8 0x4C4B220 176 177#define mmPSOC_GLOBAL_CONF_SEMAPHORE_9 0x4C4B224 178 179#define mmPSOC_GLOBAL_CONF_SEMAPHORE_10 0x4C4B228 180 181#define mmPSOC_GLOBAL_CONF_SEMAPHORE_11 0x4C4B22C 182 183#define mmPSOC_GLOBAL_CONF_SEMAPHORE_12 0x4C4B230 184 185#define mmPSOC_GLOBAL_CONF_SEMAPHORE_13 0x4C4B234 186 187#define mmPSOC_GLOBAL_CONF_SEMAPHORE_14 0x4C4B238 188 189#define mmPSOC_GLOBAL_CONF_SEMAPHORE_15 0x4C4B23C 190 191#define mmPSOC_GLOBAL_CONF_SEMAPHORE_16 0x4C4B240 192 193#define mmPSOC_GLOBAL_CONF_SEMAPHORE_17 0x4C4B244 194 195#define mmPSOC_GLOBAL_CONF_SEMAPHORE_18 0x4C4B248 196 197#define mmPSOC_GLOBAL_CONF_SEMAPHORE_19 0x4C4B24C 198 199#define mmPSOC_GLOBAL_CONF_SEMAPHORE_20 0x4C4B250 200 201#define mmPSOC_GLOBAL_CONF_SEMAPHORE_21 0x4C4B254 202 203#define mmPSOC_GLOBAL_CONF_SEMAPHORE_22 0x4C4B258 204 205#define mmPSOC_GLOBAL_CONF_SEMAPHORE_23 0x4C4B25C 206 207#define mmPSOC_GLOBAL_CONF_SEMAPHORE_24 0x4C4B260 208 209#define mmPSOC_GLOBAL_CONF_SEMAPHORE_25 0x4C4B264 210 211#define mmPSOC_GLOBAL_CONF_SEMAPHORE_26 0x4C4B268 212 213#define mmPSOC_GLOBAL_CONF_SEMAPHORE_27 0x4C4B26C 214 215#define mmPSOC_GLOBAL_CONF_SEMAPHORE_28 0x4C4B270 216 217#define mmPSOC_GLOBAL_CONF_SEMAPHORE_29 0x4C4B274 218 219#define mmPSOC_GLOBAL_CONF_SEMAPHORE_30 0x4C4B278 220 221#define mmPSOC_GLOBAL_CONF_SEMAPHORE_31 0x4C4B27C 222 223#define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS 0x4C4B300 224 225#define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU 0x4C4B304 226 227#define mmPSOC_GLOBAL_CONF_SPL_SOURCE 0x4C4B308 228 229#define mmPSOC_GLOBAL_CONF_I2C_MSTR1_DBG 0x4C4B30C 230 231#define mmPSOC_GLOBAL_CONF_I2C_SLV 0x4C4B310 232 233#define mmPSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK 0x4C4B314 234 235#define mmPSOC_GLOBAL_CONF_TRACE_ADDR 0x4C4B320 236 237#define mmPSOC_GLOBAL_CONF_SMB_ALERT_CTRL 0x4C4B324 238 239#define mmPSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE 0x4C4B328 240 241#define mmPSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR 0x4C4B32C 242 243#define mmPSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL 0x4C4B330 244 245#define mmPSOC_GLOBAL_CONF_TRACE_AXPROT 0x4C4B334 246 247#define mmPSOC_GLOBAL_CONF_TRACE_AWUSER 0x4C4B338 248 249#define mmPSOC_GLOBAL_CONF_TRACE_ARUSER 0x4C4B33C 250 251#define mmPSOC_GLOBAL_CONF_BTL_STS 0x4C4B340 252 253#define mmPSOC_GLOBAL_CONF_TIMEOUT_INTR 0x4C4B350 254 255#define mmPSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR 0x4C4B354 256 257#define mmPSOC_GLOBAL_CONF_PERIPH_INTR 0x4C4B358 258 259#define mmPSOC_GLOBAL_CONF_COMB_PERIPH_INTR 0x4C4B35C 260 261#define mmPSOC_GLOBAL_CONF_AXI_ERR_INTR 0x4C4B360 262 263#define mmPSOC_GLOBAL_CONF_ARC_WD_INTR 0x4C4B368 264 265#define mmPSOC_GLOBAL_CONF_ARC_WD_INTR_MASK 0x4C4B36C 266 267#define mmPSOC_GLOBAL_CONF_DBG_APB_CTRL 0x4C4B370 268 269#define mmPSOC_GLOBAL_CONF_SPI_DMA_BAUDR 0x4C4B374 270 271#define mmPSOC_GLOBAL_CONF_SPI_DMA_AWPROT 0x4C4B378 272 273#define mmPSOC_GLOBAL_CONF_SPI_DMA_AWUSER 0x4C4B37C 274 275#define mmPSOC_GLOBAL_CONF_SPI_DMA_CTRL 0x4C4B380 276 277#define mmPSOC_GLOBAL_CONF_SPI_DMA_STATUS 0x4C4B384 278 279#define mmPSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L 0x4C4B388 280 281#define mmPSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H 0x4C4B38C 282 283#define mmPSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL 0x4C4B3A0 284 285#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_CTRL 0x4C4B3B0 286 287#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L 0x4C4B3B4 288 289#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H 0x4C4B3B8 290 291#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L 0x4C4B3BC 292 293#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H 0x4C4B3C0 294 295#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L 0x4C4B3C4 296 297#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H 0x4C4B3CC 298 299#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS 0x4C4B3D0 300 301#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS 0x4C4B3D4 302 303#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR 0x4C4B3D8 304 305#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR 0x4C4B3DC 306 307#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK 0x4C4B3E0 308 309#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE 0x4C4B3E4 310 311#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR 0x4C4B3E8 312 313#define mmPSOC_GLOBAL_CONF_MSTR_IF 0x4C4B3F0 314 315#define mmPSOC_GLOBAL_CONF_TARGETID 0x4C4B400 316 317#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_0 0x4C4B404 318 319#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_1 0x4C4B408 320 321#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_0 0x4C4B40C 322 323#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_1 0x4C4B410 324 325#define mmPSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE 0x4C4B420 326 327#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L 0x4C4B430 328 329#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H 0x4C4B434 330 331#define mmPSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS 0x4C4B438 332 333#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_DIV 0x4C4B44C 334 335#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_CTRL 0x4C4B450 336 337#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_STS 0x4C4B454 338 339#define mmPSOC_GLOBAL_CONF_OUTSTANT_TRANS 0x4C4B458 340 341#define mmPSOC_GLOBAL_CONF_MASK_REQ 0x4C4B45C 342 343#define mmPSOC_GLOBAL_CONF_BSAC_CTRL 0x4C4B4C0 344 345#define mmPSOC_GLOBAL_CONF_BSAC_ADDR 0x4C4B4C4 346 347#define mmPSOC_GLOBAL_CONF_BSAC_DATA 0x4C4B4C8 348 349#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_CTRL 0x4C4B4CC 350 351#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_DATA 0x4C4B4D0 352 353#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_MASK 0x4C4B4D4 354 355#define mmPSOC_GLOBAL_CONF_BTL_IMG 0x4C4B4E0 356 357#define mmPSOC_GLOBAL_CONF_PRSTN_MASK 0x4C4B4E4 358 359#define mmPSOC_GLOBAL_CONF_WD_MASK 0x4C4B4E8 360 361#define mmPSOC_GLOBAL_CONF_RST_SRC 0x4C4B4F0 362 363#define mmPSOC_GLOBAL_CONF_BOOT_STATE 0x4C4B4F4 364 365#define mmPSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL 0x4C4B4F8 366 367#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_0 0x4C4B500 368 369#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_1 0x4C4B504 370 371#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_2 0x4C4B508 372 373#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_3 0x4C4B50C 374 375#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_4 0x4C4B510 376 377#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_5 0x4C4B514 378 379#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_6 0x4C4B518 380 381#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_7 0x4C4B51C 382 383#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_8 0x4C4B520 384 385#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_9 0x4C4B524 386 387#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_10 0x4C4B528 388 389#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_11 0x4C4B52C 390 391#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_12 0x4C4B530 392 393#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_13 0x4C4B534 394 395#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_14 0x4C4B538 396 397#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_15 0x4C4B53C 398 399#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_16 0x4C4B540 400 401#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_17 0x4C4B544 402 403#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_18 0x4C4B548 404 405#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_19 0x4C4B54C 406 407#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_20 0x4C4B550 408 409#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_21 0x4C4B554 410 411#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_22 0x4C4B558 412 413#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_23 0x4C4B55C 414 415#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_24 0x4C4B560 416 417#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_25 0x4C4B564 418 419#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_26 0x4C4B568 420 421#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_27 0x4C4B56C 422 423#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_28 0x4C4B570 424 425#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_29 0x4C4B574 426 427#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_30 0x4C4B578 428 429#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_31 0x4C4B57C 430 431#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_32 0x4C4B580 432 433#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_33 0x4C4B584 434 435#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_34 0x4C4B588 436 437#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_35 0x4C4B58C 438 439#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_36 0x4C4B590 440 441#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_37 0x4C4B594 442 443#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_38 0x4C4B598 444 445#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_39 0x4C4B59C 446 447#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_40 0x4C4B5A0 448 449#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_41 0x4C4B5A4 450 451#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_42 0x4C4B5A8 452 453#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_43 0x4C4B5AC 454 455#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_44 0x4C4B5B0 456 457#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_45 0x4C4B5B4 458 459#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_46 0x4C4B5B8 460 461#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_47 0x4C4B5BC 462 463#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_48 0x4C4B5C0 464 465#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_49 0x4C4B5C4 466 467#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_50 0x4C4B5C8 468 469#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_51 0x4C4B5CC 470 471#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_52 0x4C4B5D0 472 473#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_53 0x4C4B5D4 474 475#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_54 0x4C4B5D8 476 477#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_55 0x4C4B5DC 478 479#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_56 0x4C4B5E0 480 481#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_57 0x4C4B5E4 482 483#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_58 0x4C4B5E8 484 485#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_59 0x4C4B5EC 486 487#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_60 0x4C4B5F0 488 489#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_61 0x4C4B5F4 490 491#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_62 0x4C4B5F8 492 493#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_63 0x4C4B5FC 494 495#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_64 0x4C4B600 496 497#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_65 0x4C4B604 498 499#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_66 0x4C4B608 500 501#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_67 0x4C4B60C 502 503#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_68 0x4C4B610 504 505#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_69 0x4C4B614 506 507#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_70 0x4C4B618 508 509#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_71 0x4C4B61C 510 511#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_72 0x4C4B620 512 513#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_73 0x4C4B624 514 515#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_74 0x4C4B628 516 517#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_75 0x4C4B62C 518 519#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_76 0x4C4B630 520 521#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_77 0x4C4B634 522 523#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_78 0x4C4B638 524 525#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_79 0x4C4B63C 526 527#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_80 0x4C4B640 528 529#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_81 0x4C4B644 530 531#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_82 0x4C4B648 532 533#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_83 0x4C4B64C 534 535#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_84 0x4C4B650 536 537#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_85 0x4C4B654 538 539#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_86 0x4C4B658 540 541#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_87 0x4C4B65C 542 543#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_88 0x4C4B660 544 545#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_89 0x4C4B664 546 547#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_90 0x4C4B668 548 549#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_91 0x4C4B66C 550 551#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_92 0x4C4B670 552 553#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_93 0x4C4B674 554 555#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_0 0x4C4B690 556 557#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_1 0x4C4B694 558 559#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_2 0x4C4B698 560 561#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_3 0x4C4B69C 562 563#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_4 0x4C4B6A0 564 565#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_5 0x4C4B6A4 566 567#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_6 0x4C4B6A8 568 569#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_7 0x4C4B6AC 570 571#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_8 0x4C4B6B0 572 573#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_9 0x4C4B6B4 574 575#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_10 0x4C4B6B8 576 577#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_11 0x4C4B6BC 578 579#define mmPSOC_GLOBAL_CONF_BNK3V3_MS 0x4C4B710 580 581#define mmPSOC_GLOBAL_CONF_TPC_ISO 0x4C4B760 582 583#define mmPSOC_GLOBAL_CONF_VDEC_ISO 0x4C4B764 584 585#define mmPSOC_GLOBAL_CONF_NIC_ISO 0x4C4B768 586 587#define mmPSOC_GLOBAL_CONF_MME_ISO 0x4C4B76C 588 589#define mmPSOC_GLOBAL_CONF_EDMA_ISO 0x4C4B770 590 591#define mmPSOC_GLOBAL_CONF_HBM_ISO 0x4C4B774 592 593#define mmPSOC_GLOBAL_CONF_XBAR_EDGE_ISO 0x4C4B778 594 595#define mmPSOC_GLOBAL_CONF_HIF_HMMU_ISO 0x4C4B77C 596 597#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_0 0x4C4B780 598 599#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_1 0x4C4B784 600 601#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_0 0x4C4B788 602 603#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_1 0x4C4B78C 604 605#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_0 0x4C4B790 606 607#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_1 0x4C4B794 608 609#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_0 0x4C4B798 610 611#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_1 0x4C4B79C 612 613#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_0 0x4C4B7A0 614 615#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_1 0x4C4B7A4 616 617#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_0 0x4C4B7A8 618 619#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_1 0x4C4B7AC 620 621#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_0 0x4C4B7B0 622 623#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_1 0x4C4B7B4 624 625#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_STATUS 0x4C4B7B8 626 627#define mmPSOC_GLOBAL_CONF_ASIF_CORE_CFG 0x4C4B7C0 628 629#define mmPSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT 0x4C4B7C4 630 631#define mmPSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR 0x4C4B7C8 632 633#define mmPSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG 0x4C4B7CC 634 635#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_0 0x4C4B7D0 636 637#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_1 0x4C4B7D4 638 639#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_0 0x4C4B7D8 640 641#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_1 0x4C4B7DC 642 643#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_0 0x4C4B7E0 644 645#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_1 0x4C4B7E4 646 647#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_0 0x4C4B7E8 648 649#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_1 0x4C4B7EC 650 651#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_0 0x4C4B7F0 652 653#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_1 0x4C4B7F4 654 655#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_0 0x4C4B7F8 656 657#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_1 0x4C4B7FC 658 659#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_0 0x4C4B800 660 661#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_1 0x4C4B804 662 663#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_2 0x4C4B808 664 665#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_3 0x4C4B80C 666 667#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_4 0x4C4B810 668 669#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_5 0x4C4B814 670 671#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_6 0x4C4B818 672 673#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_7 0x4C4B81C 674 675#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_8 0x4C4B820 676 677#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_9 0x4C4B824 678 679#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_10 0x4C4B828 680 681#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_11 0x4C4B82C 682 683#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_12 0x4C4B830 684 685#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_13 0x4C4B834 686 687#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_14 0x4C4B838 688 689#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_15 0x4C4B83C 690 691#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_16 0x4C4B840 692 693#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_17 0x4C4B844 694 695#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_18 0x4C4B848 696 697#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_19 0x4C4B84C 698 699#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_20 0x4C4B850 700 701#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_21 0x4C4B854 702 703#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_22 0x4C4B858 704 705#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_23 0x4C4B85C 706 707#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_24 0x4C4B860 708 709#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_25 0x4C4B864 710 711#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_26 0x4C4B868 712 713#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_27 0x4C4B86C 714 715#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_28 0x4C4B870 716 717#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_29 0x4C4B874 718 719#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_30 0x4C4B878 720 721#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_31 0x4C4B87C 722 723#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_32 0x4C4B880 724 725#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_33 0x4C4B884 726 727#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_34 0x4C4B888 728 729#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_35 0x4C4B88C 730 731#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_36 0x4C4B890 732 733#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_37 0x4C4B894 734 735#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_38 0x4C4B898 736 737#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_39 0x4C4B89C 738 739#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_40 0x4C4B8A0 740 741#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_41 0x4C4B8A4 742 743#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_42 0x4C4B8A8 744 745#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_43 0x4C4B8AC 746 747#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_44 0x4C4B8B0 748 749#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_45 0x4C4B8B4 750 751#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_46 0x4C4B8B8 752 753#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_47 0x4C4B8BC 754 755#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_48 0x4C4B8C0 756 757#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_49 0x4C4B8C4 758 759#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_50 0x4C4B8C8 760 761#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_51 0x4C4B8CC 762 763#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_52 0x4C4B8D0 764 765#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_53 0x4C4B8D4 766 767#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_54 0x4C4B8D8 768 769#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_55 0x4C4B8DC 770 771#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_56 0x4C4B8E0 772 773#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_57 0x4C4B8E4 774 775#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_58 0x4C4B8E8 776 777#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_59 0x4C4B8EC 778 779#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_60 0x4C4B8F0 780 781#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_61 0x4C4B8F4 782 783#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_62 0x4C4B8F8 784 785#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_63 0x4C4B8FC 786 787#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_64 0x4C4B900 788 789#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_65 0x4C4B904 790 791#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_66 0x4C4B908 792 793#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_67 0x4C4B90C 794 795#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_68 0x4C4B910 796 797#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_69 0x4C4B914 798 799#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_70 0x4C4B918 800 801#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_71 0x4C4B91C 802 803#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_72 0x4C4B920 804 805#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_73 0x4C4B924 806 807#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_74 0x4C4B928 808 809#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_75 0x4C4B92C 810 811#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_76 0x4C4B930 812 813#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_77 0x4C4B934 814 815#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_78 0x4C4B938 816 817#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_79 0x4C4B93C 818 819#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_80 0x4C4B940 820 821#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_81 0x4C4B944 822 823#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_82 0x4C4B948 824 825#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_83 0x4C4B94C 826 827#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_84 0x4C4B950 828 829#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_85 0x4C4B954 830 831#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_86 0x4C4B958 832 833#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_87 0x4C4B95C 834 835#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_88 0x4C4B960 836 837#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_89 0x4C4B964 838 839#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_90 0x4C4B968 840 841#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_91 0x4C4B96C 842 843#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_92 0x4C4B970 844 845#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_93 0x4C4B974 846 847#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_94 0x4C4B978 848 849#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_95 0x4C4B97C 850 851#define mmPSOC_GLOBAL_CONF_PAD_SEL_0 0x4C4B980 852 853#define mmPSOC_GLOBAL_CONF_PAD_SEL_1 0x4C4B984 854 855#define mmPSOC_GLOBAL_CONF_PAD_SEL_2 0x4C4B988 856 857#define mmPSOC_GLOBAL_CONF_PAD_SEL_3 0x4C4B98C 858 859#define mmPSOC_GLOBAL_CONF_PAD_SEL_4 0x4C4B990 860 861#define mmPSOC_GLOBAL_CONF_PAD_SEL_5 0x4C4B994 862 863#define mmPSOC_GLOBAL_CONF_PAD_SEL_6 0x4C4B998 864 865#define mmPSOC_GLOBAL_CONF_PAD_SEL_7 0x4C4B99C 866 867#define mmPSOC_GLOBAL_CONF_PAD_SEL_8 0x4C4B9A0 868 869#define mmPSOC_GLOBAL_CONF_PAD_SEL_9 0x4C4B9A4 870 871#define mmPSOC_GLOBAL_CONF_PAD_SEL_10 0x4C4B9A8 872 873#define mmPSOC_GLOBAL_CONF_PAD_SEL_11 0x4C4B9AC 874 875#define mmPSOC_GLOBAL_CONF_PAD_SEL_12 0x4C4B9B0 876 877#define mmPSOC_GLOBAL_CONF_PAD_SEL_13 0x4C4B9B4 878 879#define mmPSOC_GLOBAL_CONF_PAD_SEL_14 0x4C4B9B8 880 881#define mmPSOC_GLOBAL_CONF_PAD_SEL_15 0x4C4B9BC 882 883#define mmPSOC_GLOBAL_CONF_PAD_SEL_16 0x4C4B9C0 884 885#define mmPSOC_GLOBAL_CONF_PAD_SEL_17 0x4C4B9C4 886 887#define mmPSOC_GLOBAL_CONF_PAD_SEL_18 0x4C4B9C8 888 889#define mmPSOC_GLOBAL_CONF_PAD_SEL_19 0x4C4B9CC 890 891#define mmPSOC_GLOBAL_CONF_PAD_SEL_20 0x4C4B9D0 892 893#define mmPSOC_GLOBAL_CONF_PAD_SEL_21 0x4C4B9D4 894 895#define mmPSOC_GLOBAL_CONF_PAD_SEL_22 0x4C4B9D8 896 897#define mmPSOC_GLOBAL_CONF_PAD_SEL_23 0x4C4B9DC 898 899#define mmPSOC_GLOBAL_CONF_PAD_SEL_24 0x4C4B9E0 900 901#define mmPSOC_GLOBAL_CONF_PAD_SEL_25 0x4C4B9E4 902 903#define mmPSOC_GLOBAL_CONF_PAD_SEL_26 0x4C4B9E8 904 905#define mmPSOC_GLOBAL_CONF_PAD_SEL_27 0x4C4B9EC 906 907#define mmPSOC_GLOBAL_CONF_PAD_SEL_28 0x4C4B9F0 908 909#define mmPSOC_GLOBAL_CONF_PAD_SEL_29 0x4C4B9F4 910 911#define mmPSOC_GLOBAL_CONF_PAD_SEL_30 0x4C4B9F8 912 913#define mmPSOC_GLOBAL_CONF_PAD_SEL_31 0x4C4B9FC 914 915#define mmPSOC_GLOBAL_CONF_PAD_SEL_32 0x4C4BA00 916 917#define mmPSOC_GLOBAL_CONF_PAD_SEL_33 0x4C4BA04 918 919#define mmPSOC_GLOBAL_CONF_PAD_SEL_34 0x4C4BA08 920 921#define mmPSOC_GLOBAL_CONF_PAD_SEL_35 0x4C4BA0C 922 923#define mmPSOC_GLOBAL_CONF_PAD_SEL_36 0x4C4BA10 924 925#define mmPSOC_GLOBAL_CONF_PAD_SEL_37 0x4C4BA14 926 927#define mmPSOC_GLOBAL_CONF_PAD_SEL_38 0x4C4BA18 928 929#define mmPSOC_GLOBAL_CONF_PAD_SEL_39 0x4C4BA1C 930 931#define mmPSOC_GLOBAL_CONF_PAD_SEL_40 0x4C4BA20 932 933#define mmPSOC_GLOBAL_CONF_PAD_SEL_41 0x4C4BA24 934 935#define mmPSOC_GLOBAL_CONF_PAD_SEL_42 0x4C4BA28 936 937#define mmPSOC_GLOBAL_CONF_PAD_SEL_43 0x4C4BA2C 938 939#define mmPSOC_GLOBAL_CONF_PAD_SEL_44 0x4C4BA30 940 941#define mmPSOC_GLOBAL_CONF_PAD_SEL_45 0x4C4BA34 942 943#define mmPSOC_GLOBAL_CONF_PAD_SEL_46 0x4C4BA38 944 945#define mmPSOC_GLOBAL_CONF_PAD_SEL_47 0x4C4BA3C 946 947#define mmPSOC_GLOBAL_CONF_PAD_SEL_48 0x4C4BA40 948 949#define mmPSOC_GLOBAL_CONF_PAD_SEL_49 0x4C4BA44 950 951#define mmPSOC_GLOBAL_CONF_PAD_SEL_50 0x4C4BA48 952 953#define mmPSOC_GLOBAL_CONF_PAD_SEL_51 0x4C4BA4C 954 955#define mmPSOC_GLOBAL_CONF_PAD_SEL_52 0x4C4BA50 956 957#define mmPSOC_GLOBAL_CONF_PAD_SEL_53 0x4C4BA54 958 959#define mmPSOC_GLOBAL_CONF_PAD_SEL_54 0x4C4BA58 960 961#define mmPSOC_GLOBAL_CONF_PAD_SEL_55 0x4C4BA5C 962 963#define mmPSOC_GLOBAL_CONF_PAD_SEL_56 0x4C4BA60 964 965#define mmPSOC_GLOBAL_CONF_PAD_SEL_57 0x4C4BA64 966 967#define mmPSOC_GLOBAL_CONF_PAD_SEL_58 0x4C4BA68 968 969#define mmPSOC_GLOBAL_CONF_PAD_SEL_59 0x4C4BA6C 970 971#define mmPSOC_GLOBAL_CONF_PAD_SEL_60 0x4C4BA70 972 973#define mmPSOC_GLOBAL_CONF_PAD_SEL_61 0x4C4BA74 974 975#define mmPSOC_GLOBAL_CONF_PAD_SEL_62 0x4C4BA78 976 977#define mmPSOC_GLOBAL_CONF_PAD_SEL_63 0x4C4BA7C 978 979#define mmPSOC_GLOBAL_CONF_PAD_SEL_64 0x4C4BA80 980 981#define mmPSOC_GLOBAL_CONF_PAD_SEL_65 0x4C4BA84 982 983#define mmPSOC_GLOBAL_CONF_PAD_SEL_66 0x4C4BA88 984 985#define mmPSOC_GLOBAL_CONF_PAD_SEL_67 0x4C4BA8C 986 987#define mmPSOC_GLOBAL_CONF_PAD_SEL_68 0x4C4BA90 988 989#define mmPSOC_GLOBAL_CONF_PAD_SEL_69 0x4C4BA94 990 991#define mmPSOC_GLOBAL_CONF_PAD_SEL_70 0x4C4BA98 992 993#define mmPSOC_GLOBAL_CONF_PAD_SEL_71 0x4C4BA9C 994 995#define mmPSOC_GLOBAL_CONF_PAD_SEL_72 0x4C4BAA0 996 997#define mmPSOC_GLOBAL_CONF_PAD_SEL_73 0x4C4BAA4 998 999#define mmPSOC_GLOBAL_CONF_PAD_SEL_74 0x4C4BAA8 1000 1001#define mmPSOC_GLOBAL_CONF_PAD_SEL_75 0x4C4BAAC 1002 1003#define mmPSOC_GLOBAL_CONF_PAD_SEL_76 0x4C4BAB0 1004 1005#define mmPSOC_GLOBAL_CONF_PAD_SEL_77 0x4C4BAB4 1006 1007#define mmPSOC_GLOBAL_CONF_PAD_SEL_78 0x4C4BAB8 1008 1009#define mmPSOC_GLOBAL_CONF_PAD_SEL_79 0x4C4BABC 1010 1011#define mmPSOC_GLOBAL_CONF_PAD_SEL_80 0x4C4BAC0 1012 1013#define mmPSOC_GLOBAL_CONF_PAD_SEL_81 0x4C4BAC4 1014 1015#define mmPSOC_GLOBAL_CONF_PAD_SEL_82 0x4C4BAC8 1016 1017#define mmPSOC_GLOBAL_CONF_PAD_SEL_83 0x4C4BACC 1018 1019#define mmPSOC_GLOBAL_CONF_PAD_SEL_84 0x4C4BAD0 1020 1021#define mmPSOC_GLOBAL_CONF_PAD_SEL_85 0x4C4BAD4 1022 1023#define mmPSOC_GLOBAL_CONF_PAD_SEL_86 0x4C4BAD8 1024 1025#define mmPSOC_GLOBAL_CONF_PAD_SEL_87 0x4C4BADC 1026 1027#define mmPSOC_GLOBAL_CONF_PAD_SEL_88 0x4C4BAE0 1028 1029#define mmPSOC_GLOBAL_CONF_PAD_SEL_89 0x4C4BAE4 1030 1031#define mmPSOC_GLOBAL_CONF_PAD_SEL_90 0x4C4BAE8 1032 1033#define mmPSOC_GLOBAL_CONF_PAD_SEL_91 0x4C4BAEC 1034 1035#define mmPSOC_GLOBAL_CONF_PAD_SEL_92 0x4C4BAF0 1036 1037#define mmPSOC_GLOBAL_CONF_PAD_SEL_93 0x4C4BAF4 1038 1039#define mmPSOC_GLOBAL_CONF_PAD_SEL_94 0x4C4BAF8 1040 1041#define mmPSOC_GLOBAL_CONF_PAD_SEL_95 0x4C4BAFC 1042 1043#define mmPSOC_GLOBAL_CONF_SMI_ACCESS_EN 0x4C4BB00 1044 1045#define mmPSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN 0x4C4BB38 1046 1047#define mmPSOC_GLOBAL_CONF_SCRAM_PERM_SEL 0x4C4BB3C 1048 1049#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_0 0x4C4BB40 1050 1051#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_1 0x4C4BB44 1052 1053#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_2 0x4C4BB48 1054 1055#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_3 0x4C4BB4C 1056 1057#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_4 0x4C4BB50 1058 1059#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_5 0x4C4BB54 1060 1061#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_6 0x4C4BB58 1062 1063#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_7 0x4C4BB5C 1064 1065#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_8 0x4C4BB60 1066 1067#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_9 0x4C4BB64 1068 1069#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_10 0x4C4BB68 1070 1071#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_11 0x4C4BB6C 1072 1073#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_12 0x4C4BB70 1074 1075#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_13 0x4C4BB74 1076 1077#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_14 0x4C4BB78 1078 1079#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_15 0x4C4BB7C 1080 1081#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_16 0x4C4BB80 1082 1083#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_17 0x4C4BB84 1084 1085#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_18 0x4C4BB88 1086 1087#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_19 0x4C4BB8C 1088 1089#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_20 0x4C4BB90 1090 1091#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_21 0x4C4BB94 1092 1093#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_22 0x4C4BB98 1094 1095#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_23 0x4C4BB9C 1096 1097#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_24 0x4C4BBA0 1098 1099#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_25 0x4C4BBA4 1100 1101#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_26 0x4C4BBA8 1102 1103#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_27 0x4C4BBAC 1104 1105#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_28 0x4C4BBB0 1106 1107#define mmPSOC_GLOBAL_CONF_CORE_MODE 0x4C4BBB4 1108 1109#define mmPSOC_GLOBAL_CONF_EXTMEM_ID_LOC 0x4C4BBB8 1110 1111#define mmPSOC_GLOBAL_CONF_LBW_USER_CTRL 0x4C4BBC0 1112 1113#define mmPSOC_GLOBAL_CONF_ADC_STM_ID 0x4C4BBFC 1114 1115#define mmPSOC_GLOBAL_CONF_ADC_0 0x4C4BC00 1116 1117#define mmPSOC_GLOBAL_CONF_ADC_1 0x4C4BC04 1118 1119#define mmPSOC_GLOBAL_CONF_ADC_INT_MASK_0 0x4C4BC10 1120 1121#define mmPSOC_GLOBAL_CONF_ADC_INT_MASK_1 0x4C4BC14 1122 1123#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ_0 0x4C4BC20 1124 1125#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ_1 0x4C4BC24 1126 1127#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_0 0x4C4BC30 1128 1129#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_1 0x4C4BC34 1130 1131#define mmPSOC_GLOBAL_CONF_ADC_SAMPLES_0 0x4C4BC40 1132 1133#define mmPSOC_GLOBAL_CONF_ADC_SAMPLES_1 0x4C4BC44 1134 1135#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS_0 0x4C4BC50 1136 1137#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS_1 0x4C4BC54 1138 1139#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB_0 0x4C4BC60 1140 1141#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB_1 0x4C4BC64 1142 1143#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_0 0x4C4BC70 1144 1145#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_1 0x4C4BC74 1146 1147#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_0 0x4C4BC80 1148 1149#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_1 0x4C4BC84 1150 1151#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO_0 0x4C4BC90 1152 1153#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO_1 0x4C4BC94 1154 1155#define mmPSOC_GLOBAL_CONF_ADC_PID_SEL 0x4C4BC98 1156 1157#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK_0 0x4C4BCA0 1158 1159#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK_1 0x4C4BCA4 1160 1161#define mmPSOC_GLOBAL_CONF_ADC_CH_SEL_0 0x4C4BCA8 1162 1163#define mmPSOC_GLOBAL_CONF_ADC_CH_SEL_1 0x4C4BCAC 1164 1165#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_0 0x4C4BCC0 1166 1167#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_1 0x4C4BCC4 1168 1169#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_2 0x4C4BCC8 1170 1171#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_3 0x4C4BCCC 1172 1173#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_4 0x4C4BCD0 1174 1175#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_5 0x4C4BCD4 1176 1177#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_6 0x4C4BCD8 1178 1179#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_7 0x4C4BCDC 1180 1181#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_0 0x4C4BCE0 1182 1183#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_1 0x4C4BCE4 1184 1185#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_2 0x4C4BCE8 1186 1187#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_3 0x4C4BCEC 1188 1189#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_4 0x4C4BCF0 1190 1191#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_5 0x4C4BCF4 1192 1193#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_6 0x4C4BCF8 1194 1195#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_7 0x4C4BCFC 1196 1197#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_0 0x4C4BD00 1198 1199#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_1 0x4C4BD04 1200 1201#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_2 0x4C4BD08 1202 1203#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_3 0x4C4BD0C 1204 1205#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_4 0x4C4BD10 1206 1207#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_5 0x4C4BD14 1208 1209#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_6 0x4C4BD18 1210 1211#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_7 0x4C4BD1C 1212 1213#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_CTRL 0x4C4BD24 1214 1215#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L 0x4C4BD28 1216 1217#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H 0x4C4BD2C 1218 1219#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L 0x4C4BD30 1220 1221#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H 0x4C4BD34 1222 1223#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L 0x4C4BD38 1224 1225#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H 0x4C4BD3C 1226 1227#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L 0x4C4BD40 1228 1229#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H 0x4C4BD44 1230 1231#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L 0x4C4BD48 1232 1233#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H 0x4C4BD4C 1234 1235#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L 0x4C4BD50 1236 1237#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H 0x4C4BD54 1238 1239#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L 0x4C4BD58 1240 1241#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H 0x4C4BD5C 1242 1243#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L 0x4C4BD60 1244 1245#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H 0x4C4BD64 1246 1247#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL 0x4C4BD80 1248 1249#define mmPSOC_GLOBAL_CONF_RST_OUT_CTRL 0x4C4BD84 1250 1251#define mmPSOC_GLOBAL_CONF_MEM_CPY_CTRL 0x4C4BD90 1252 1253#define mmPSOC_GLOBAL_CONF_MEM_CPY_STATUS 0x4C4BD94 1254 1255#define mmPSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H 0x4C4BD98 1256 1257#define mmPSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L 0x4C4BD9C 1258 1259#define mmPSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H 0x4C4BDA0 1260 1261#define mmPSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L 0x4C4BDA4 1262 1263#define mmPSOC_GLOBAL_CONF_MEM_CPY_CTRL2 0x4C4BDA8 1264 1265#define mmPSOC_GLOBAL_CONF_MEM_CPY_CONST 0x4C4BDAC 1266 1267#define mmPSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H 0x4C4BDB0 1268 1269#define mmPSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L 0x4C4BDB4 1270 1271#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_CFG 0x4C4BDC0 1272 1273#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1 0x4C4BDC4 1274 1275#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0 0x4C4BDC8 1276 1277#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1 0x4C4BDCC 1278 1279#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2 0x4C4BDD0 1280 1281#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3 0x4C4BDD4 1282 1283#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4 0x4C4BDD8 1284 1285#define mmPSOC_GLOBAL_CONF_LBW_ARUSER_OVRD 0x4C4BDE0 1286 1287#define mmPSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN 0x4C4BDE4 1288 1289#define mmPSOC_GLOBAL_CONF_LBW_AWUSER_OVRD 0x4C4BDE8 1290 1291#define mmPSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN 0x4C4BDEC 1292 1293#define mmPSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2 0x4C4BDF0 1294 1295#define mmPSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2 0x4C4BDF4 1296 1297#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR 0x4C4BDF8 1298 1299#define mmPSOC_GLOBAL_CONF_MEM_CPY_PROT 0x4C4BE08 1300 1301#define mmPSOC_GLOBAL_CONF_ISOLATE_INPUTS 0x4C4BE10 1302 1303#define mmPSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL 0x4C4BE14 1304 1305#define mmPSOC_GLOBAL_CONF_ARC_JT_SEL 0x4C4BE28 1306 1307#define mmPSOC_GLOBAL_CONF_PLL_DUMP_CRTL 0x4C4BE2C 1308 1309#define mmPSOC_GLOBAL_CONF_MEM_CPY_AXUSER 0x4C4BE30 1310 1311#define mmPSOC_GLOBAL_CONF_BTL_AXUSER 0x4C4BE34 1312 1313#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0 0x4C4BE38 1314 1315#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1 0x4C4BE40 1316 1317#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2 0x4C4BE44 1318 1319#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3 0x4C4BE48 1320 1321#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_CTRL 0x4C4BE4C 1322 1323#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT 0x4C4BE50 1324 1325#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_INTR 0x4C4BE54 1326 1327#define mmPSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK 0x4C4BE58 1328 1329#define mmPSOC_GLOBAL_CONF_ECO_INTR_CAUSE 0x4C4BE60 1330 1331#define mmPSOC_GLOBAL_CONF_ECO_INTR_CLEAR 0x4C4BE64 1332 1333#define mmPSOC_GLOBAL_CONF_ECO_INTR_MASK 0x4C4BE68 1334 1335#define mmPSOC_GLOBAL_CONF_DFT_APB_CONTROL 0x4C4BE70 1336 1337#endif /* ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ */
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