FILE
psoc_global_conf_masks.h
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linux-6.19.14/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ 14#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ 15 16/* 17 ***************************************** 18 * PSOC_GLOBAL_CONF 19 * (Prototype: GLOBAL_CONF) 20 ***************************************** 21 */ 22 23/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */ 24#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0 25#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF 26 27/* PSOC_GLOBAL_CONF_PCI_FW_FSM */ 28#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0 29#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1 30 31/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */ 32#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0 33#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1 34#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_SHIFT 4 35#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_MASK 0x10 36#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_SHIFT 5 37#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_MASK 0x20 38#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_SHIFT 6 39#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_MASK 0x40 40#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_SHIFT 7 41#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_MASK 0x80 42#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_PRST_RST_IND_SHIFT 8 43#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_PRST_RST_IND_MASK 0x100 44#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FLR_RST_IND_SHIFT 9 45#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FLR_RST_IND_MASK 0x200 46#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FW_RST_IND_SHIFT 10 47#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FW_RST_IND_MASK 0x400 48#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_ECC_DERR_RST_IND_SHIFT 11 49#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_ECC_DERR_RST_IND_MASK 0x800 50 51/* PSOC_GLOBAL_CONF_BTM_FSM */ 52#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0 53#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0x1F 54 55/* PSOC_GLOBAL_CONF_BTL_ROM_DELAY */ 56#define PSOC_GLOBAL_CONF_BTL_ROM_DELAY_VAL_SHIFT 0 57#define PSOC_GLOBAL_CONF_BTL_ROM_DELAY_VAL_MASK 0xFFFF 58 59/* PSOC_GLOBAL_CONF_SW_BTM_FSM */ 60#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0 61#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0x1F 62 63/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */ 64#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT 0 65#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK 0x1F 66 67/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */ 68#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT 0 69#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK 0xFFFFFFFF 70 71/* PSOC_GLOBAL_CONF_QSPI_SPI */ 72#define PSOC_GLOBAL_CONF_QSPI_SPI_SEL_SHIFT 0 73#define PSOC_GLOBAL_CONF_QSPI_SPI_SEL_MASK 0x1 74 75/* PSOC_GLOBAL_CONF_SPI_MEM_EN */ 76#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SPI_SHIFT 0 77#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SPI_MASK 0x1 78#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_QSPI_SHIFT 1 79#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_QSPI_MASK 0x2 80 81/* PSOC_GLOBAL_CONF_PRSTN */ 82#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT 0 83#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1 84 85/* PSOC_GLOBAL_CONF_PCIE_EN */ 86#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT 0 87#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1 88 89/* PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR */ 90#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_SHIFT 0 91#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK 0x1 92 93/* PSOC_GLOBAL_CONF_SPI_IMG_STS */ 94#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_PRI_SHIFT 0 95#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_PRI_MASK 0x3 96#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_SEC_SHIFT 2 97#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_SEC_MASK 0xC 98#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_PRI_SHIFT 4 99#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_PRI_MASK 0x30 100#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SEC_SHIFT 6 101#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SEC_MASK 0xC0 102#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_PRI_SHIFT 8 103#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_PRI_MASK 0x300 104#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_SEC_SHIFT 10 105#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_SEC_MASK 0xC00 106#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_PRI_SHIFT 12 107#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_PRI_MASK 0x3000 108#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_PRI_SHIFT 14 109#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_PRI_MASK 0xC000 110#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_SEC_SHIFT 16 111#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_SEC_MASK 0x30000 112#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_SEC_SHIFT 18 113#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_SEC_MASK 0xC0000 114 115/* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */ 116#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT 0 117#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1 118#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT 1 119#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK 0x2 120#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT 2 121#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK 0x4 122#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT 3 123#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK 0x8 124#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT 4 125#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK 0x10 126#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT 5 127#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK 0x20 128#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT 6 129#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK 0x40 130#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT 7 131#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK 0x80 132#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT 8 133#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK 0x100 134 135/* PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD */ 136#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_SHIFT 0 137#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK 0x1 138 139/* PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST */ 140#define PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST_VAL_SHIFT 0 141#define PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST_VAL_MASK 0x1 142 143/* PSOC_GLOBAL_CONF_PHY_STABLE */ 144#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_SHIFT 0 145#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_MASK 0x1 146 147/* PSOC_GLOBAL_CONF_PRSTN_OVR */ 148#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_SHIFT 0 149#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_MASK 0x1 150#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_SHIFT 4 151#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_MASK 0x10 152 153/* PSOC_GLOBAL_CONF_ETR_FLUSH */ 154#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_SHIFT 0 155#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_MASK 0x1 156 157/* PSOC_GLOBAL_CONF_ANY_RST */ 158#define PSOC_GLOBAL_CONF_ANY_RST_IND_SHIFT 0 159#define PSOC_GLOBAL_CONF_ANY_RST_IND_MASK 0x1 160 161/* PSOC_GLOBAL_CONF_COLD_RST_FLOPS */ 162#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_SHIFT 0 163#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_MASK 0xFFFFFFFF 164 165/* PSOC_GLOBAL_CONF_DIS_RAZWI_ERR */ 166#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_SHIFT 0 167#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_MASK 0x1 168 169/* PSOC_GLOBAL_CONF_PCIE_PHY_RST_N */ 170#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_SHIFT 0 171#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_MASK 0x1 172#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_CLK_DIS_SHIFT 16 173#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_CLK_DIS_MASK 0x10000 174 175/* PSOC_GLOBAL_CONF_RAZWI_INTERRUPT */ 176#define PSOC_GLOBAL_CONF_RAZWI_INTERRUPT_INTR_SHIFT 0 177#define PSOC_GLOBAL_CONF_RAZWI_INTERRUPT_INTR_MASK 0x1 178 179/* PSOC_GLOBAL_CONF_RAZWI_MASK_INFO */ 180#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_MASK_SHIFT 0 181#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_MASK_MASK 0x1 182#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AR_SHIFT 1 183#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AR_MASK 0x2 184#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AW_SHIFT 2 185#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AW_MASK 0x4 186#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_SHIFT 4 187#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_MASK 0x3FF0 188#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_H_SHIFT 16 189#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_H_MASK 0xFFFF0000 190 191/* PSOC_GLOBAL_CONF_BTL_PROT */ 192#define PSOC_GLOBAL_CONF_BTL_PROT_AR_SHIFT 0 193#define PSOC_GLOBAL_CONF_BTL_PROT_AR_MASK 0x7 194#define PSOC_GLOBAL_CONF_BTL_PROT_AW_SHIFT 4 195#define PSOC_GLOBAL_CONF_BTL_PROT_AW_MASK 0x70 196 197/* PSOC_GLOBAL_CONF_BTL_ADDR_EXT */ 198#define PSOC_GLOBAL_CONF_BTL_ADDR_EXT_VAL_SHIFT 0 199#define PSOC_GLOBAL_CONF_BTL_ADDR_EXT_VAL_MASK 0xFFFFF 200 201/* PSOC_GLOBAL_CONF_BOOT_SEQ_TO */ 202#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_SHIFT 0 203#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_MASK 0x1 204 205/* PSOC_GLOBAL_CONF_RESET_DELAYS */ 206#define PSOC_GLOBAL_CONF_RESET_DELAYS_PRE_RESET_SHIFT 0 207#define PSOC_GLOBAL_CONF_RESET_DELAYS_PRE_RESET_MASK 0xFFFF 208#define PSOC_GLOBAL_CONF_RESET_DELAYS_GRAD_RESET_SHIFT 16 209#define PSOC_GLOBAL_CONF_RESET_DELAYS_GRAD_RESET_MASK 0xFFFF0000 210 211/* PSOC_GLOBAL_CONF_SCRATCHPAD */ 212#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT 0 213#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK 0xFFFFFFFF 214 215/* PSOC_GLOBAL_CONF_SEMAPHORE */ 216#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT 0 217#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK 0xFFFFFFFF 218 219/* PSOC_GLOBAL_CONF_CPU_BOOT_STATUS */ 220#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_SHIFT 0 221#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_MASK 0xFFFFFFFF 222 223/* PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU */ 224#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_SHIFT 0 225#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_MASK 0xFFFFFFFF 226 227/* PSOC_GLOBAL_CONF_SPL_SOURCE */ 228#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT 0 229#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK 0x7 230 231/* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */ 232#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT 0 233#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK 0x1 234#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT 1 235#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK 0x2 236#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT 2 237#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK 0x4 238#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT 3 239#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK 0x8 240#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT 4 241#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK 0x10 242#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT 5 243#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK 0x20 244#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT 6 245#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK 0x40 246#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT 7 247#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK 0x80 248#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT 8 249#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK 0x100 250#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT 9 251#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200 252#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT 10 253#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK 0x7C00 254#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT 15 255#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK 0x78000 256#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT 19 257#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK 0x80000 258 259/* PSOC_GLOBAL_CONF_I2C_SLV */ 260#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT 0 261#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK 0x1 262 263/* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */ 264#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_INTR_SHIFT 0 265#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_INTR_MASK 0x1 266 267/* PSOC_GLOBAL_CONF_TRACE_ADDR */ 268#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_SHIFT 0 269#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK 0xFFFFFF 270 271/* PSOC_GLOBAL_CONF_SMB_ALERT_CTRL */ 272#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M0_ALERT_MASK_SHIFT 0 273#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M0_ALERT_MASK_MASK 0xFF 274#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M1_ALERT_MASK_SHIFT 8 275#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M1_ALERT_MASK_MASK 0xFF00 276#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_SLV_ALERT_MASK_SHIFT 16 277#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_SLV_ALERT_MASK_MASK 0xFF0000 278 279/* PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE */ 280#define PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE_VAL_SHIFT 0 281#define PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE_VAL_MASK 0xFF 282 283/* PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR */ 284#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR_IND_SHIFT 0 285#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR_IND_MASK 0x1 286 287/* PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL */ 288#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_IND_SHIFT 0 289#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_IND_MASK 0x1 290#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_MASK_SHIFT 4 291#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_MASK_MASK 0x10 292 293/* PSOC_GLOBAL_CONF_TRACE_AXPROT */ 294#define PSOC_GLOBAL_CONF_TRACE_AXPROT_VAL_SHIFT 0 295#define PSOC_GLOBAL_CONF_TRACE_AXPROT_VAL_MASK 0x7 296 297/* PSOC_GLOBAL_CONF_TRACE_AWUSER */ 298#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_SHIFT 0 299#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_MASK 0xFFFFFFFF 300 301/* PSOC_GLOBAL_CONF_TRACE_ARUSER */ 302#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_SHIFT 0 303#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_MASK 0xFFFFFFFF 304 305/* PSOC_GLOBAL_CONF_BTL_STS */ 306#define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT 0 307#define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK 0x1 308#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT 4 309#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK 0x10 310#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT 8 311#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK 0xF00 312 313/* PSOC_GLOBAL_CONF_TIMEOUT_INTR */ 314#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT 0 315#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK 0x1 316#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT 1 317#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK 0x2 318#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT 2 319#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK 0x4 320#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT 3 321#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK 0x8 322#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT 4 323#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK 0x10 324#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT 5 325#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK 0x20 326#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT 6 327#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK 0x40 328#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT 7 329#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK 0x80 330#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_SHIFT 8 331#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_MASK 0x100 332#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_SHIFT 9 333#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_MASK 0x200 334 335/* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */ 336#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT 0 337#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK 0x1 338 339/* PSOC_GLOBAL_CONF_PERIPH_INTR */ 340#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT 0 341#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK 0x1 342#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT 1 343#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK 0x2 344#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT 2 345#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK 0x4 346#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT 3 347#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK 0x8 348#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT 4 349#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK 0x10 350#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT 5 351#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK 0x20 352#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT 6 353#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK 0x40 354#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT 7 355#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK 0x80 356#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT 12 357#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK 0x1000 358#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT 13 359#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK 0x2000 360#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT 16 361#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK 0x10000 362 363/* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */ 364#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT 0 365#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK 0x1 366 367/* PSOC_GLOBAL_CONF_AXI_ERR_INTR */ 368#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT 0 369#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK 0x1 370 371/* PSOC_GLOBAL_CONF_ARC_WD_INTR */ 372#define PSOC_GLOBAL_CONF_ARC_WD_INTR_IND_SHIFT 0 373#define PSOC_GLOBAL_CONF_ARC_WD_INTR_IND_MASK 0x3 374 375/* PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK */ 376#define PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK_VAL_SHIFT 0 377#define PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK_VAL_MASK 0x3 378 379/* PSOC_GLOBAL_CONF_DBG_APB_CTRL */ 380#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_SEL_SHIFT 0 381#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_SEL_MASK 0x1 382#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_VAL_SHIFT 1 383#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_VAL_MASK 0x2 384 385/* PSOC_GLOBAL_CONF_SPI_DMA_BAUDR */ 386#define PSOC_GLOBAL_CONF_SPI_DMA_BAUDR_VAL_SHIFT 0 387#define PSOC_GLOBAL_CONF_SPI_DMA_BAUDR_VAL_MASK 0xFFFF 388 389/* PSOC_GLOBAL_CONF_SPI_DMA_AWPROT */ 390#define PSOC_GLOBAL_CONF_SPI_DMA_AWPROT_VAL_SHIFT 0 391#define PSOC_GLOBAL_CONF_SPI_DMA_AWPROT_VAL_MASK 0x7 392 393/* PSOC_GLOBAL_CONF_SPI_DMA_AWUSER */ 394#define PSOC_GLOBAL_CONF_SPI_DMA_AWUSER_VAL_SHIFT 0 395#define PSOC_GLOBAL_CONF_SPI_DMA_AWUSER_VAL_MASK 0xFFFFFFFF 396 397/* PSOC_GLOBAL_CONF_SPI_DMA_CTRL */ 398#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_EN_SHIFT 0 399#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_EN_MASK 0x1 400#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_DST_SRAM_SHIFT 1 401#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_DST_SRAM_MASK 0x2 402#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_MEM_SIZE_SHIFT 4 403#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_MEM_SIZE_MASK 0x3FFF0 404#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_ADDR_SHIFT 18 405#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_ADDR_MASK 0xFFFC0000 406 407/* PSOC_GLOBAL_CONF_SPI_DMA_STATUS */ 408#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_DONE_SHIFT 0 409#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_DONE_MASK 0x1 410#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_ERROR_SHIFT 1 411#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_ERROR_MASK 0x2 412#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_COPIED_SHIFT 4 413#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_COPIED_MASK 0x3FFF0 414 415/* PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L */ 416#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L_VAL_SHIFT 0 417#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L_VAL_MASK 0xFFFFFFFF 418 419/* PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H */ 420#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H_VAL_SHIFT 0 421#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H_VAL_MASK 0xFFFFFFFF 422 423/* PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL */ 424#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WEN_SHIFT 0 425#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WEN_MASK 0x1 426#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_BYTE_SWAP_SHIFT 4 427#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_BYTE_SWAP_MASK 0x10 428#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRITE_CMD_SHIFT 8 429#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRITE_CMD_MASK 0xFF00 430#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WREN_CMD_SHIFT 16 431#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WREN_CMD_MASK 0xFF0000 432#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRDI_CMD_SHIFT 24 433#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRDI_CMD_MASK 0xFF000000 434 435/* PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL */ 436#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_EN_SHIFT 0 437#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_EN_MASK 0x1 438#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_RESP_ERR_SHIFT 1 439#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_RESP_ERR_MASK 0x2 440#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_SE_RANGE_SEL_SHIFT 4 441#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_SE_RANGE_SEL_MASK 0xFF0 442 443/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L */ 444#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L_VAL_SHIFT 0 445#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L_VAL_MASK 0xFFFFFFFF 446 447/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H */ 448#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H_VAL_SHIFT 0 449#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H_VAL_MASK 0xFF 450 451/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L */ 452#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L_VAL_SHIFT 0 453#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L_VAL_MASK 0xFFFFFFFF 454 455/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H */ 456#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H_VAL_SHIFT 0 457#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H_VAL_MASK 0xFF 458 459/* PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L */ 460#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L_VAL_SHIFT 0 461#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L_VAL_MASK 0xFFFFFFFF 462 463/* PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H */ 464#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H_VAL_SHIFT 0 465#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H_VAL_MASK 0xFF 466 467/* PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS */ 468#define PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS_VAL_SHIFT 0 469#define PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS_VAL_MASK 0xFFFFFFFF 470 471/* PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS */ 472#define PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS_VAL_SHIFT 0 473#define PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS_VAL_MASK 0xFFFFFFFF 474 475/* PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR */ 476#define PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR_VAL_SHIFT 0 477#define PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR_VAL_MASK 0xFFFFFFFF 478 479/* PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR */ 480#define PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR_VAL_SHIFT 0 481#define PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR_VAL_MASK 0xFFFFFFFF 482 483/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK */ 484#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_QSPI_SHIFT 0 485#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_QSPI_MASK 0x1 486#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_SPI_SHIFT 1 487#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_SPI_MASK 0x2 488 489/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE */ 490#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_QSPI_IND_SHIFT 0 491#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_QSPI_IND_MASK 0x1 492#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_SPI_IND_SHIFT 1 493#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_SPI_IND_MASK 0x2 494 495/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR */ 496#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_QSPI_VAL_SHIFT 0 497#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_QSPI_VAL_MASK 0x1 498#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_SPI_VAL_SHIFT 1 499#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_SPI_VAL_MASK 0x2 500 501/* PSOC_GLOBAL_CONF_MSTR_IF */ 502#define PSOC_GLOBAL_CONF_MSTR_IF_GRACEFULL_CLEAR_SHIFT 0 503#define PSOC_GLOBAL_CONF_MSTR_IF_GRACEFULL_CLEAR_MASK 0x1 504#define PSOC_GLOBAL_CONF_MSTR_IF_FORCE_BP_SHIFT 1 505#define PSOC_GLOBAL_CONF_MSTR_IF_FORCE_BP_MASK 0x2 506 507/* PSOC_GLOBAL_CONF_TARGETID */ 508#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT 1 509#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK 0xFFE 510#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT 16 511#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK 0xFFF0000 512#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT 28 513#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK 0xF0000000 514 515/* PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL */ 516#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_RD_SHIFT 0 517#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_RD_MASK 0xFF 518#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_WR_SHIFT 8 519#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_WR_MASK 0xFF00 520#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_FORCE_WR_BUF_SHIFT 16 521#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_FORCE_WR_BUF_MASK 0x10000 522 523/* PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2 */ 524#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_EN_SHIFT 0 525#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_EN_MASK 0x1 526#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_VAL_SHIFT 4 527#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_VAL_MASK 0xF0 528#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_EN_SHIFT 8 529#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_EN_MASK 0x100 530#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_VAL_SHIFT 12 531#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_VAL_MASK 0xF000 532#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_NO_WR_INFLIGHT_SHIFT 16 533#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_NO_WR_INFLIGHT_MASK 0x10000 534 535/* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */ 536#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT 0 537#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK 0x1 538 539/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L */ 540#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_0_SHIFT 1 541#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_0_MASK 0x2 542#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_MEM_REPAIR_CFG_SHIFT 2 543#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_MEM_REPAIR_CFG_MASK 0xC 544#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPOL_SHIFT 4 545#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPOL_MASK 0x10 546#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPHA_SHIFT 5 547#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPHA_MASK 0x20 548#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_EN_SHIFT 6 549#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_EN_MASK 0x40 550#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_ROM_EN_SHIFT 7 551#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_ROM_EN_MASK 0x80 552#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_SEL_SHIFT 8 553#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_SEL_MASK 0x3FFF00 554#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_1_SHIFT 22 555#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_1_MASK 0x400000 556#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_DIS_SHIFT 23 557#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_DIS_MASK 0x800000 558#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_I2C_SHIFT 24 559#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_I2C_MASK 0x1F000000 560#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_SPI_QSPI_SHIFT 29 561#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_SPI_QSPI_MASK 0x20000000 562#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPU_PLL_CFG_SHIFT 30 563#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPU_PLL_CFG_MASK 0xC0000000 564 565/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H */ 566#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SECURITY_BYPASS_SHIFT 0 567#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SECURITY_BYPASS_MASK 0x1 568#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SRIS_MODE_SHIFT 1 569#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SRIS_MODE_MASK 0x2 570#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_I2C_SLV_ADDR_SHIFT 2 571#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_I2C_SLV_ADDR_MASK 0x7C 572#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_RERERVED_STRAP_SHIFT 7 573#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_RERERVED_STRAP_MASK 0x380 574 575/* PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS */ 576#define PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS_PCIE_EN_SHIFT 0 577#define PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS_PCIE_EN_MASK 0x1 578 579/* PSOC_GLOBAL_CONF_MEM_REPAIR_DIV */ 580#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_SHIFT 0 581#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_MASK 0x1 582#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_SHIFT 8 583#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_MASK 0xFF00 584 585/* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */ 586#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT 0 587#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK 0x1 588 589/* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */ 590#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT 0 591#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK 0x1 592#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_SHIFT 4 593#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_MASK 0x10 594 595/* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */ 596#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT 0 597#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK 0x1 598#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT 1 599#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK 0x2 600 601/* PSOC_GLOBAL_CONF_MASK_REQ */ 602#define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT 0 603#define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK 0x1 604 605/* PSOC_GLOBAL_CONF_BSAC_CTRL */ 606#define PSOC_GLOBAL_CONF_BSAC_CTRL_ENABLE_SHIFT 0 607#define PSOC_GLOBAL_CONF_BSAC_CTRL_ENABLE_MASK 0x1 608#define PSOC_GLOBAL_CONF_BSAC_CTRL_HOLD_SHIFT 1 609#define PSOC_GLOBAL_CONF_BSAC_CTRL_HOLD_MASK 0x2 610#define PSOC_GLOBAL_CONF_BSAC_CTRL_DONE_SHIFT 4 611#define PSOC_GLOBAL_CONF_BSAC_CTRL_DONE_MASK 0x10 612#define PSOC_GLOBAL_CONF_BSAC_CTRL_STARTED_SHIFT 5 613#define PSOC_GLOBAL_CONF_BSAC_CTRL_STARTED_MASK 0x20 614#define PSOC_GLOBAL_CONF_BSAC_CTRL_APBERROR_SHIFT 6 615#define PSOC_GLOBAL_CONF_BSAC_CTRL_APBERROR_MASK 0x40 616#define PSOC_GLOBAL_CONF_BSAC_CTRL_FRF_SHIFT 8 617#define PSOC_GLOBAL_CONF_BSAC_CTRL_FRF_MASK 0x300 618#define PSOC_GLOBAL_CONF_BSAC_CTRL_TMOD_SHIFT 10 619#define PSOC_GLOBAL_CONF_BSAC_CTRL_TMOD_MASK 0xC00 620#define PSOC_GLOBAL_CONF_BSAC_CTRL_SPI_FRF_SHIFT 12 621#define PSOC_GLOBAL_CONF_BSAC_CTRL_SPI_FRF_MASK 0x3000 622 623/* PSOC_GLOBAL_CONF_BSAC_ADDR */ 624#define PSOC_GLOBAL_CONF_BSAC_ADDR_VAL_SHIFT 0 625#define PSOC_GLOBAL_CONF_BSAC_ADDR_VAL_MASK 0xFFFFFFF 626 627/* PSOC_GLOBAL_CONF_BSAC_DATA */ 628#define PSOC_GLOBAL_CONF_BSAC_DATA_VAL_SHIFT 0 629#define PSOC_GLOBAL_CONF_BSAC_DATA_VAL_MASK 0xFFFFFFFF 630 631/* PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL */ 632#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ADDR_SHIFT 0 633#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ADDR_MASK 0xFFFFFFF 634#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ENABLE_SHIFT 28 635#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ENABLE_MASK 0x10000000 636#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_DONE_SHIFT 29 637#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_DONE_MASK 0x20000000 638 639/* PSOC_GLOBAL_CONF_BSAC_POLLING_DATA */ 640#define PSOC_GLOBAL_CONF_BSAC_POLLING_DATA_VAL_SHIFT 0 641#define PSOC_GLOBAL_CONF_BSAC_POLLING_DATA_VAL_MASK 0xFFFFFFFF 642 643/* PSOC_GLOBAL_CONF_BSAC_POLLING_MASK */ 644#define PSOC_GLOBAL_CONF_BSAC_POLLING_MASK_VAL_SHIFT 0 645#define PSOC_GLOBAL_CONF_BSAC_POLLING_MASK_VAL_MASK 0xFFFFFFFF 646 647/* PSOC_GLOBAL_CONF_BTL_IMG */ 648#define PSOC_GLOBAL_CONF_BTL_IMG_SPI_IMAGE_FLIP_SHIFT 0 649#define PSOC_GLOBAL_CONF_BTL_IMG_SPI_IMAGE_FLIP_MASK 0x1 650#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_IMAGE_FLIP_SHIFT 1 651#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_IMAGE_FLIP_MASK 0x2 652#define PSOC_GLOBAL_CONF_BTL_IMG_PCIE_IMAGE_FLIP_SHIFT 2 653#define PSOC_GLOBAL_CONF_BTL_IMG_PCIE_IMAGE_FLIP_MASK 0x4 654#define PSOC_GLOBAL_CONF_BTL_IMG_SW_RST_RUN_PCIE_IMAGE_SHIFT 4 655#define PSOC_GLOBAL_CONF_BTL_IMG_SW_RST_RUN_PCIE_IMAGE_MASK 0x10 656#define PSOC_GLOBAL_CONF_BTL_IMG_SOFT_RST_RUN_PCIE_IMAGE_SHIFT 5 657#define PSOC_GLOBAL_CONF_BTL_IMG_SOFT_RST_RUN_PCIE_IMAGE_MASK 0x20 658#define PSOC_GLOBAL_CONF_BTL_IMG_WD_RST_RUN_PCIE_IMAGE_SHIFT 6 659#define PSOC_GLOBAL_CONF_BTL_IMG_WD_RST_RUN_PCIE_IMAGE_MASK 0x40 660#define PSOC_GLOBAL_CONF_BTL_IMG_MNL_RST_RUN_PCIE_IMAGE_SHIFT 7 661#define PSOC_GLOBAL_CONF_BTL_IMG_MNL_RST_RUN_PCIE_IMAGE_MASK 0x80 662#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_RUN_PCIE_IMAGE_SHIFT 8 663#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_RUN_PCIE_IMAGE_MASK 0x100 664#define PSOC_GLOBAL_CONF_BTL_IMG_FLR_RST_RUN_PCIE_IMAGE_SHIFT 9 665#define PSOC_GLOBAL_CONF_BTL_IMG_FLR_RST_RUN_PCIE_IMAGE_MASK 0x200 666#define PSOC_GLOBAL_CONF_BTL_IMG_FW_RST_RUN_PCIE_IMAGE_SHIFT 10 667#define PSOC_GLOBAL_CONF_BTL_IMG_FW_RST_RUN_PCIE_IMAGE_MASK 0x400 668 669/* PSOC_GLOBAL_CONF_PRSTN_MASK */ 670#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT 0 671#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK 0x1 672 673/* PSOC_GLOBAL_CONF_WD_MASK */ 674#define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT 0 675#define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK 0x1 676 677/* PSOC_GLOBAL_CONF_RST_SRC */ 678#define PSOC_GLOBAL_CONF_RST_SRC_COLD_RST_IND_SHIFT 0 679#define PSOC_GLOBAL_CONF_RST_SRC_COLD_RST_IND_MASK 0x1 680#define PSOC_GLOBAL_CONF_RST_SRC_MNL_RST_IND_SHIFT 1 681#define PSOC_GLOBAL_CONF_RST_SRC_MNL_RST_IND_MASK 0x2 682#define PSOC_GLOBAL_CONF_RST_SRC_PRSTN_RST_IND_SHIFT 2 683#define PSOC_GLOBAL_CONF_RST_SRC_PRSTN_RST_IND_MASK 0x4 684#define PSOC_GLOBAL_CONF_RST_SRC_SOFT_RST_IND_SHIFT 3 685#define PSOC_GLOBAL_CONF_RST_SRC_SOFT_RST_IND_MASK 0x8 686#define PSOC_GLOBAL_CONF_RST_SRC_WD_RST_IND_SHIFT 4 687#define PSOC_GLOBAL_CONF_RST_SRC_WD_RST_IND_MASK 0x10 688#define PSOC_GLOBAL_CONF_RST_SRC_FW_RST_IND_SHIFT 5 689#define PSOC_GLOBAL_CONF_RST_SRC_FW_RST_IND_MASK 0x20 690#define PSOC_GLOBAL_CONF_RST_SRC_SW_RST_IND_SHIFT 6 691#define PSOC_GLOBAL_CONF_RST_SRC_SW_RST_IND_MASK 0x40 692#define PSOC_GLOBAL_CONF_RST_SRC_FLR_RST_IND_SHIFT 7 693#define PSOC_GLOBAL_CONF_RST_SRC_FLR_RST_IND_MASK 0x80 694#define PSOC_GLOBAL_CONF_RST_SRC_ECC_DERR_RST_IND_SHIFT 8 695#define PSOC_GLOBAL_CONF_RST_SRC_ECC_DERR_RST_IND_MASK 0x100 696 697/* PSOC_GLOBAL_CONF_BOOT_STATE */ 698#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_SHIFT 0 699#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_MASK 0x1 700 701/* PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL */ 702#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SOFT_RST_MASK_SHIFT 0 703#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SOFT_RST_MASK_MASK 0x1 704#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SW_RST_MASK_SHIFT 4 705#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SW_RST_MASK_MASK 0x10 706 707/* PSOC_GLOBAL_CONF_PAD_1V8_CFG */ 708#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT 0 709#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK 0x7F 710 711/* PSOC_GLOBAL_CONF_PAD_3V3_CFG */ 712#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT 0 713#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK 0x7F 714 715/* PSOC_GLOBAL_CONF_BNK3V3_MS */ 716#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT 0 717#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK 0x3 718 719/* PSOC_GLOBAL_CONF_TPC_ISO */ 720#define PSOC_GLOBAL_CONF_TPC_ISO_ISO_EN_SHIFT 0 721#define PSOC_GLOBAL_CONF_TPC_ISO_ISO_EN_MASK 0x1FFFFFF 722 723/* PSOC_GLOBAL_CONF_VDEC_ISO */ 724#define PSOC_GLOBAL_CONF_VDEC_ISO_ISO_EN_SHIFT 0 725#define PSOC_GLOBAL_CONF_VDEC_ISO_ISO_EN_MASK 0x3FF 726 727/* PSOC_GLOBAL_CONF_NIC_ISO */ 728#define PSOC_GLOBAL_CONF_NIC_ISO_ISO_EN_SHIFT 0 729#define PSOC_GLOBAL_CONF_NIC_ISO_ISO_EN_MASK 0xFFF 730 731/* PSOC_GLOBAL_CONF_MME_ISO */ 732#define PSOC_GLOBAL_CONF_MME_ISO_MME0_EU_RO_ISO_SHIFT 0 733#define PSOC_GLOBAL_CONF_MME_ISO_MME0_EU_RO_ISO_MASK 0x3F 734#define PSOC_GLOBAL_CONF_MME_ISO_MME1_EU_RO_ISO_SHIFT 6 735#define PSOC_GLOBAL_CONF_MME_ISO_MME1_EU_RO_ISO_MASK 0xFC0 736#define PSOC_GLOBAL_CONF_MME_ISO_MME2_EU_RO_ISO_SHIFT 12 737#define PSOC_GLOBAL_CONF_MME_ISO_MME2_EU_RO_ISO_MASK 0x3F000 738#define PSOC_GLOBAL_CONF_MME_ISO_MME3_EU_RO_ISO_SHIFT 18 739#define PSOC_GLOBAL_CONF_MME_ISO_MME3_EU_RO_ISO_MASK 0xFC0000 740 741/* PSOC_GLOBAL_CONF_EDMA_ISO */ 742#define PSOC_GLOBAL_CONF_EDMA_ISO_ISO_EN_SHIFT 0 743#define PSOC_GLOBAL_CONF_EDMA_ISO_ISO_EN_MASK 0xFF 744 745/* PSOC_GLOBAL_CONF_HBM_ISO */ 746#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_XBAR_SHIFT 0 747#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_XBAR_MASK 0xFFF 748#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_HCH_SHIFT 16 749#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_HCH_MASK 0x3F0000 750 751/* PSOC_GLOBAL_CONF_XBAR_EDGE_ISO */ 752#define PSOC_GLOBAL_CONF_XBAR_EDGE_ISO_ISO_EN_SHIFT 0 753#define PSOC_GLOBAL_CONF_XBAR_EDGE_ISO_ISO_EN_MASK 0xF 754 755/* PSOC_GLOBAL_CONF_HIF_HMMU_ISO */ 756#define PSOC_GLOBAL_CONF_HIF_HMMU_ISO_ISO_EN_SHIFT 0 757#define PSOC_GLOBAL_CONF_HIF_HMMU_ISO_ISO_EN_MASK 0xFFFF 758 759/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS */ 760#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_FAILED_SHIFT 0 761#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_FAILED_MASK 0x1 762 763/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH */ 764#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_LSB_ADDR_SHIFT 0 765#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_LSB_ADDR_MASK 0xFFF 766#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PPROT_SHIFT 12 767#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PPROT_MASK 0x7000 768#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PWRITE_SHIFT 16 769#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PWRITE_MASK 0x10000 770#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_FENCE_SHIFT 17 771#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_FENCE_MASK 0x20000 772#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DROP_SHIFT 18 773#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DROP_MASK 0x40000 774#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DST_ID_SHIFT 20 775#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DST_ID_MASK 0x3F00000 776 777/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR */ 778#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_PWDATA_SHIFT 0 779#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_PWDATA_MASK 0xFFFFFFFF 780 781/* PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS */ 782#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_RES_READY_SHIFT 0 783#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_RES_READY_MASK 0x1 784#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_PSLVERR_SHIFT 4 785#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_PSLVERR_MASK 0x10 786 787/* PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP */ 788#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_PRDATA_SHIFT 0 789#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_PRDATA_MASK 0xFFFFFFFF 790 791/* PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR */ 792#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_BUFF_FULL_SHIFT 0 793#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_BUFF_FULL_MASK 0x1 794#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_BUFF_FULL_SHIFT 1 795#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_BUFF_FULL_MASK 0x2 796#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_ILLEGAL_SHIFT 2 797#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_ILLEGAL_MASK 0x4 798#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_DATA_OVRN_SHIFT 3 799#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_DATA_OVRN_MASK 0x8 800#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_SHIFT 4 801#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_MASK 0x10 802#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_QUAL_OVRN_SHIFT 5 803#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_QUAL_OVRN_MASK 0x20 804#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_POP_RES_WHILE_EMPTY_SHIFT 6 805#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_POP_RES_WHILE_EMPTY_MASK 0x40 806#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PUSH_REQ_WHILE_FULL_SHIFT 7 807#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PUSH_REQ_WHILE_FULL_MASK 0x80 808#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RX_TIMEOUT_SHIFT 8 809#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RX_TIMEOUT_MASK 0x100 810#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_TX_TIMEOUT_SHIFT 9 811#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_TX_TIMEOUT_MASK 0x200 812#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_ADDR_SHIFT 12 813#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_ADDR_MASK 0xFFF000 814#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DST_ID_SHIFT 24 815#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DST_ID_MASK 0x3F000000 816#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DROP_SHIFT 31 817#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DROP_MASK 0x80000000 818 819/* PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK */ 820#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_BUFF_FULL_SHIFT 0 821#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_BUFF_FULL_MASK 0x1 822#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_BUFF_FULL_SHIFT 1 823#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_BUFF_FULL_MASK 0x2 824#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_ILLEGAL_SHIFT 2 825#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_ILLEGAL_MASK 0x4 826#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_DATA_OVRN_SHIFT 3 827#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_DATA_OVRN_MASK 0x8 828#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PSLVERR_SHIFT 4 829#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PSLVERR_MASK 0x10 830#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_QUAL_OVRN_SHIFT 5 831#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_QUAL_OVRN_MASK 0x20 832#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_POP_RES_WHILE_EMPTY_SHIFT 6 833#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_POP_RES_WHILE_EMPTY_MASK 0x40 834#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PUSH_REQ_WHILE_FULL_SHIFT 7 835#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PUSH_REQ_WHILE_FULL_MASK 0x80 836#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RX_TIMEOUT_SHIFT 8 837#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RX_TIMEOUT_MASK 0x100 838#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_TX_TIMEOUT_SHIFT 9 839#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_TX_TIMEOUT_MASK 0x200 840#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_VALID_SHIFT 16 841#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_VALID_MASK 0x10000 842 843/* PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS */ 844#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_REQ_LL_USED_SHIFT 0 845#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_REQ_LL_USED_MASK 0x3F 846#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_RES_LL_USED_SHIFT 8 847#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_RES_LL_USED_MASK 0x1F00 848#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_OTF_FIFO_USED_SHIFT 16 849#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_OTF_FIFO_USED_MASK 0x3F0000 850 851/* PSOC_GLOBAL_CONF_ASIF_CORE_CFG */ 852#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_RISE_DELAY_SHIFT 0 853#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_RISE_DELAY_MASK 0x1F 854#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FALL_DELAY_SHIFT 8 855#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FALL_DELAY_MASK 0x1F00 856#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_DETECT_DELAY_SHIFT 16 857#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_DETECT_DELAY_MASK 0xF0000 858#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FLUSH_DESIGN_SHIFT 31 859#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FLUSH_DESIGN_MASK 0x80000000 860 861/* PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT */ 862#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_DATA_OVRN_CNT_SHIFT 0 863#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_DATA_OVRN_CNT_MASK 0xF 864#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_QUAL_OVRN_CNT_SHIFT 4 865#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_QUAL_OVRN_CNT_MASK 0xF0 866#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_DETECT_CYCLES_CNT_SHIFT 8 867#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_DETECT_CYCLES_CNT_MASK 0xF00 868#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_CNT_SHIFT 12 869#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_CNT_MASK 0xF000 870#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_CNT_SHIFT 16 871#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_CNT_MASK 0xF0000 872#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_FSM_SHIFT 20 873#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_FSM_MASK 0xF00000 874#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_FSM_SHIFT 24 875#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_FSM_MASK 0xF000000 876 877/* PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR */ 878#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_GLB_CLEAR_SHIFT 0 879#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_GLB_CLEAR_MASK 0x1 880#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_DATA_OVRN_CLR_SHIFT 1 881#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_DATA_OVRN_CLR_MASK 0x2 882#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_QUAL_OVRN_CLR_SHIFT 2 883#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_QUAL_OVRN_CLR_MASK 0x4 884#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_CLR_SHIFT 3 885#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_CLR_MASK 0x8 886#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_TX_CLR_SHIFT 4 887#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_TX_CLR_MASK 0x10 888 889/* PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG */ 890#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_EN_SHIFT 0 891#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_EN_MASK 0x1 892#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_EN_SHIFT 1 893#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_EN_MASK 0x2 894#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_RES_SHIFT 2 895#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_RES_MASK 0x4 896#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_RES_SHIFT 3 897#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_RES_MASK 0x8 898#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_VALUE_SHIFT 8 899#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_VALUE_MASK 0x3FF00 900#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_VALUE_SHIFT 20 901#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_VALUE_MASK 0x3FF00000 902 903/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE */ 904#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_IND_SHIFT 0 905#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_IND_MASK 0x1 906 907/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR */ 908#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_IND_SHIFT 0 909#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_IND_MASK 0x1 910 911/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK */ 912#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_VAL_SHIFT 0 913#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_VAL_MASK 0x1 914 915/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE */ 916#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_IND_SHIFT 0 917#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_IND_MASK 0x1 918 919/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR */ 920#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_IND_SHIFT 0 921#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_IND_MASK 0x1 922 923/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK */ 924#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_VAL_SHIFT 0 925#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_VAL_MASK 0x1 926 927/* PSOC_GLOBAL_CONF_PAD_DEFAULT */ 928#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT 0 929#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK 0xF 930 931/* PSOC_GLOBAL_CONF_PAD_SEL */ 932#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT 0 933#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK 0x3 934 935/* PSOC_GLOBAL_CONF_SMI_ACCESS_EN */ 936#define PSOC_GLOBAL_CONF_SMI_ACCESS_EN_VAL_SHIFT 0 937#define PSOC_GLOBAL_CONF_SMI_ACCESS_EN_VAL_MASK 0x1 938 939/* PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN */ 940#define PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN_VAL_SHIFT 0 941#define PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN_VAL_MASK 0x1 942 943/* PSOC_GLOBAL_CONF_SCRAM_PERM_SEL */ 944#define PSOC_GLOBAL_CONF_SCRAM_PERM_SEL_VAL_SHIFT 0 945#define PSOC_GLOBAL_CONF_SCRAM_PERM_SEL_VAL_MASK 0xF 946 947/* PSOC_GLOBAL_CONF_SCRAM_POLY_H3 */ 948#define PSOC_GLOBAL_CONF_SCRAM_POLY_H3_VAL_SHIFT 0 949#define PSOC_GLOBAL_CONF_SCRAM_POLY_H3_VAL_MASK 0x1FFFFFFF 950 951/* PSOC_GLOBAL_CONF_CORE_MODE */ 952#define PSOC_GLOBAL_CONF_CORE_MODE_VAL_SHIFT 0 953#define PSOC_GLOBAL_CONF_CORE_MODE_VAL_MASK 0x1 954 955/* PSOC_GLOBAL_CONF_EXTMEM_ID_LOC */ 956#define PSOC_GLOBAL_CONF_EXTMEM_ID_LOC_USER_SHRD_IND_LOC_SHIFT 24 957#define PSOC_GLOBAL_CONF_EXTMEM_ID_LOC_USER_SHRD_IND_LOC_MASK 0x3F000000 958 959/* PSOC_GLOBAL_CONF_LBW_USER_CTRL */ 960#define PSOC_GLOBAL_CONF_LBW_USER_CTRL_EN_SHIFT 0 961#define PSOC_GLOBAL_CONF_LBW_USER_CTRL_EN_MASK 0x1 962 963/* PSOC_GLOBAL_CONF_ADC_STM_ID */ 964#define PSOC_GLOBAL_CONF_ADC_STM_ID_STM_MSTR_ID_SHIFT 0 965#define PSOC_GLOBAL_CONF_ADC_STM_ID_STM_MSTR_ID_MASK 0x3F 966 967/* PSOC_GLOBAL_CONF_ADC */ 968#define PSOC_GLOBAL_CONF_ADC_INTR_SHIFT 0 969#define PSOC_GLOBAL_CONF_ADC_INTR_MASK 0xF 970 971/* PSOC_GLOBAL_CONF_ADC_INT_MASK */ 972#define PSOC_GLOBAL_CONF_ADC_INT_MASK_VAL_SHIFT 0 973#define PSOC_GLOBAL_CONF_ADC_INT_MASK_VAL_MASK 0xF 974 975/* PSOC_GLOBAL_CONF_ADC_CLK_FREQ */ 976#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_SHIFT 0 977#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_MASK 0xFF 978 979/* PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START */ 980#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_SHIFT 0 981#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_MASK 0xFF 982 983/* PSOC_GLOBAL_CONF_ADC_SAMPLES */ 984#define PSOC_GLOBAL_CONF_ADC_SAMPLES_DATA_SAMPLES_SHIFT 0 985#define PSOC_GLOBAL_CONF_ADC_SAMPLES_DATA_SAMPLES_MASK 0x1F 986#define PSOC_GLOBAL_CONF_ADC_SAMPLES_CLK_SAMPLES_SHIFT 8 987#define PSOC_GLOBAL_CONF_ADC_SAMPLES_CLK_SAMPLES_MASK 0x1F00 988 989/* PSOC_GLOBAL_CONF_ADC_TPH_CS */ 990#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_SHIFT 0 991#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_MASK 0xFF 992 993/* PSOC_GLOBAL_CONF_ADC_LSB_NMSB */ 994#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_SHIFT 0 995#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_MASK 0x1 996 997/* PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES */ 998#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_SHIFT 0 999#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_MASK 0x1 1000 1001/* PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE */ 1002#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_SHIFT 0 1003#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_MASK 0x1 1004#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_CH_SEL_SHIFT 4 1005#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_CH_SEL_MASK 0x30 1006 1007/* PSOC_GLOBAL_CONF_ADC_TDV_CSDO */ 1008#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_SHIFT 0 1009#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_MASK 0xFF 1010 1011/* PSOC_GLOBAL_CONF_ADC_PID_SEL */ 1012#define PSOC_GLOBAL_CONF_ADC_PID_SEL_ADC_SEL_SHIFT 0 1013#define PSOC_GLOBAL_CONF_ADC_PID_SEL_ADC_SEL_MASK 0x3 1014#define PSOC_GLOBAL_CONF_ADC_PID_SEL_CHANNEL_SEL_SHIFT 4 1015#define PSOC_GLOBAL_CONF_ADC_PID_SEL_CHANNEL_SEL_MASK 0x30 1016 1017/* PSOC_GLOBAL_CONF_ADC_TSU_CSCK */ 1018#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_SHIFT 0 1019#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_MASK 0xFF 1020 1021/* PSOC_GLOBAL_CONF_ADC_CH_SEL */ 1022#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_DELAY_SHIFT 0 1023#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_DELAY_MASK 0xFF 1024#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_MAX_SHIFT 8 1025#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_MAX_MASK 0x300 1026 1027/* PSOC_GLOBAL_CONF_ADC_WRITE_ADDR */ 1028#define PSOC_GLOBAL_CONF_ADC_WRITE_ADDR_VAL_SHIFT 0 1029#define PSOC_GLOBAL_CONF_ADC_WRITE_ADDR_VAL_MASK 0xFFFFFFFF 1030 1031/* PSOC_GLOBAL_CONF_ADC_CFG_DATA */ 1032#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_SHIFT 0 1033#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_MASK 0xFFFFFFFF 1034 1035/* PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL */ 1036#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_AUX_WR_EN_SHIFT 0 1037#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_AUX_WR_EN_MASK 0x1 1038#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_WR_EN_SHIFT 1 1039#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_WR_EN_MASK 0x2 1040#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_GRNT_SHIFT 12 1041#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_GRNT_MASK 0x1000 1042#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_DATA_SHIFT 13 1043#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_DATA_MASK 0x2000 1044#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_TS_SHIFT 14 1045#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_TS_MASK 0x4000 1046#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_MARKED_SHIFT 15 1047#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_MARKED_MASK 0x8000 1048#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_CAUSE_TRIG_SHIFT 16 1049#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_CAUSE_TRIG_MASK 0x10000 1050 1051/* PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL */ 1052#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_RRESP_VAL_SHIFT 0 1053#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_RRESP_VAL_MASK 0x3 1054#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_WIN_EN_SHIFT 4 1055#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_WIN_EN_MASK 0xF0 1056 1057/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L */ 1058#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L_VAL_SHIFT 12 1059#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L_VAL_MASK 0xFFFFF000 1060 1061/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H */ 1062#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H_VAL_SHIFT 0 1063#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H_VAL_MASK 0xFFFFFFFF 1064 1065/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L */ 1066#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L_VAL_SHIFT 12 1067#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L_VAL_MASK 0xFFFFF000 1068 1069/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H */ 1070#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H_VAL_SHIFT 0 1071#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H_VAL_MASK 0xFFFFFFFF 1072 1073/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L */ 1074#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L_VAL_SHIFT 12 1075#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L_VAL_MASK 0xFFFFF000 1076 1077/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H */ 1078#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H_VAL_SHIFT 0 1079#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H_VAL_MASK 0xFFFFFFFF 1080 1081/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L */ 1082#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L_VAL_SHIFT 12 1083#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L_VAL_MASK 0xFFFFF000 1084 1085/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H */ 1086#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H_VAL_SHIFT 0 1087#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H_VAL_MASK 0xFFFFFFFF 1088 1089/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L */ 1090#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L_VAL_SHIFT 12 1091#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L_VAL_MASK 0xFFFFF000 1092 1093/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H */ 1094#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H_VAL_SHIFT 0 1095#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H_VAL_MASK 0xFFFFFFFF 1096 1097/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L */ 1098#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L_VAL_SHIFT 12 1099#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L_VAL_MASK 0xFFFFF000 1100 1101/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H */ 1102#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H_VAL_SHIFT 0 1103#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H_VAL_MASK 0xFFFFFFFF 1104 1105/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L */ 1106#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L_VAL_SHIFT 12 1107#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L_VAL_MASK 0xFFFFF000 1108 1109/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H */ 1110#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H_VAL_SHIFT 0 1111#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H_VAL_MASK 0xFFFFFFFF 1112 1113/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L */ 1114#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L_VAL_SHIFT 12 1115#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L_VAL_MASK 0xFFFFF000 1116 1117/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H */ 1118#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H_VAL_SHIFT 0 1119#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H_VAL_MASK 0xFFFFFFFF 1120 1121/* PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL */ 1122#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_START_SHIFT 0 1123#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_START_MASK 0x1 1124#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_DONE_SHIFT 4 1125#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_DONE_MASK 0x10 1126 1127/* PSOC_GLOBAL_CONF_RST_OUT_CTRL */ 1128#define PSOC_GLOBAL_CONF_RST_OUT_CTRL_CLR_SHIFT 0 1129#define PSOC_GLOBAL_CONF_RST_OUT_CTRL_CLR_MASK 0x1 1130 1131/* PSOC_GLOBAL_CONF_MEM_CPY_CTRL */ 1132#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL_EN_SHIFT 0 1133#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL_EN_MASK 0x1 1134 1135/* PSOC_GLOBAL_CONF_MEM_CPY_STATUS */ 1136#define PSOC_GLOBAL_CONF_MEM_CPY_STATUS_DONE_SHIFT 0 1137#define PSOC_GLOBAL_CONF_MEM_CPY_STATUS_DONE_MASK 0x1 1138 1139/* PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H */ 1140#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H_VAL_SHIFT 0 1141#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H_VAL_MASK 0xFFFFFFFF 1142 1143/* PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L */ 1144#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L_VAL_SHIFT 0 1145#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L_VAL_MASK 0xFFFFFFFF 1146 1147/* PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H */ 1148#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H_VAL_SHIFT 0 1149#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H_VAL_MASK 0xFFFFFFFF 1150 1151/* PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L */ 1152#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L_VAL_SHIFT 0 1153#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L_VAL_MASK 0xFFFFFFFF 1154 1155/* PSOC_GLOBAL_CONF_MEM_CPY_CTRL2 */ 1156#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_MEM_SIZE_SHIFT 0 1157#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_MEM_SIZE_MASK 0xFFFF 1158#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_WR_OS_SHIFT 16 1159#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_WR_OS_MASK 0x3F0000 1160#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_RD_OS_SHIFT 24 1161#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_RD_OS_MASK 0x3F000000 1162#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_USE_CONST_SHIFT 31 1163#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_USE_CONST_MASK 0x80000000 1164 1165/* PSOC_GLOBAL_CONF_MEM_CPY_CONST */ 1166#define PSOC_GLOBAL_CONF_MEM_CPY_CONST_VAL_SHIFT 0 1167#define PSOC_GLOBAL_CONF_MEM_CPY_CONST_VAL_MASK 0xFFFFFFFF 1168 1169/* PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H */ 1170#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H_VAL_SHIFT 0 1171#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H_VAL_MASK 0xFFFFFFFF 1172 1173/* PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L */ 1174#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L_VAL_SHIFT 0 1175#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L_VAL_MASK 0xFFFFFFFF 1176 1177/* PSOC_GLOBAL_CONF_AXI_SPLIT_CFG */ 1178#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_RESP_OK_SHIFT 0 1179#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_RESP_OK_MASK 0x1 1180#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_WR_BUF_SHIFT 1 1181#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_WR_BUF_MASK 0x2 1182#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_RD_OS_SHIFT 8 1183#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_RD_OS_MASK 0xFF00 1184#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_WR_OS_SHIFT 16 1185#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_WR_OS_MASK 0xFF0000 1186 1187/* PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1 */ 1188#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_EN_SHIFT 0 1189#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_EN_MASK 0x7 1190#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_VAL_SHIFT 8 1191#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_VAL_MASK 0x700 1192#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_EN_SHIFT 16 1193#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_EN_MASK 0x70000 1194#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_VAL_SHIFT 24 1195#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_VAL_MASK 0x7000000 1196 1197/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0 */ 1198#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0_OVRD_RD_EN_31_0_SHIFT 0 1199#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0_OVRD_RD_EN_31_0_MASK 0xFFFFFFFF 1200 1201/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1 */ 1202#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1_OVRD_RD_31_0_SHIFT 0 1203#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1_OVRD_RD_31_0_MASK 0xFFFFFFFF 1204 1205/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2 */ 1206#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2_OVRD_WR_EN_31_0_SHIFT 0 1207#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2_OVRD_WR_EN_31_0_MASK 0xFFFFFFFF 1208 1209/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3 */ 1210#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3_OVRD_WR_31_0_SHIFT 0 1211#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3_OVRD_WR_31_0_MASK 0xFFFFFFFF 1212 1213/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4 */ 1214#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_EN_39_32_SHIFT 0 1215#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_EN_39_32_MASK 0xFF 1216#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_39_32_SHIFT 8 1217#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_39_32_MASK 0xFF00 1218#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_EN_39_32_SHIFT 16 1219#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_EN_39_32_MASK 0xFF0000 1220#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_39_32_SHIFT 24 1221#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_39_32_MASK 0xFF000000 1222 1223/* PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD */ 1224#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_VAL_SHIFT 0 1225#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_VAL_MASK 0xFFFFFFFF 1226 1227/* PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN */ 1228#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN_VAL_SHIFT 0 1229#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN_VAL_MASK 0xFFFFFFFF 1230 1231/* PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD */ 1232#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_VAL_SHIFT 0 1233#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_VAL_MASK 0xFFFFFFFF 1234 1235/* PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN */ 1236#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN_VAL_SHIFT 0 1237#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN_VAL_MASK 0xFFFFFFFF 1238 1239/* PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2 */ 1240#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_CAUSE_SHIFT 0 1241#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_CAUSE_MASK 0x1 1242#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_MASK_SHIFT 4 1243#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_MASK_MASK 0x10 1244#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_SHIFT 5 1245#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_MASK 0x20 1246#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_SEI_INTR_ID_SHIFT 8 1247#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_SEI_INTR_ID_MASK 0x7FFFFF00 1248 1249/* PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2 */ 1250#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_CAUSE_SHIFT 0 1251#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_CAUSE_MASK 0x1 1252#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_MASK_SHIFT 4 1253#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_MASK_MASK 0x10 1254#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_SHIFT 5 1255#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_MASK 0x20 1256#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_SEI_INTR_ID_SHIFT 8 1257#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_SEI_INTR_ID_MASK 0xFFFFF00 1258 1259/* PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR */ 1260#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_MAIN_IND_SHIFT 0 1261#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_MAIN_IND_MASK 0x1 1262#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_BOOTROM_IND_SHIFT 1 1263#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_BOOTROM_IND_MASK 0x2 1264 1265/* PSOC_GLOBAL_CONF_MEM_CPY_PROT */ 1266#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AR_SHIFT 0 1267#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AR_MASK 0x7 1268#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AW_SHIFT 4 1269#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AW_MASK 0x70 1270 1271/* PSOC_GLOBAL_CONF_ISOLATE_INPUTS */ 1272#define PSOC_GLOBAL_CONF_ISOLATE_INPUTS_EN_SHIFT 0 1273#define PSOC_GLOBAL_CONF_ISOLATE_INPUTS_EN_MASK 0x1 1274 1275/* PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL */ 1276#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_EN_SHIFT 0 1277#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_EN_MASK 0x1 1278#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_BRESP_SHIFT 1 1279#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_BRESP_MASK 0x6 1280#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_RRESP_SHIFT 5 1281#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_RRESP_MASK 0x60 1282 1283/* PSOC_GLOBAL_CONF_ARC_JT_SEL */ 1284#define PSOC_GLOBAL_CONF_ARC_JT_SEL_VAL_SHIFT 0 1285#define PSOC_GLOBAL_CONF_ARC_JT_SEL_VAL_MASK 0x1 1286 1287/* PSOC_GLOBAL_CONF_PLL_DUMP_CRTL */ 1288#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_PLL_SEL_SHIFT 0 1289#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_PLL_SEL_MASK 0x3F 1290#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_BIT_SEL_SHIFT 8 1291#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_BIT_SEL_MASK 0xF00 1292 1293/* PSOC_GLOBAL_CONF_MEM_CPY_AXUSER */ 1294#define PSOC_GLOBAL_CONF_MEM_CPY_AXUSER_VAL_SHIFT 0 1295#define PSOC_GLOBAL_CONF_MEM_CPY_AXUSER_VAL_MASK 0xFFFFFFFF 1296 1297/* PSOC_GLOBAL_CONF_BTL_AXUSER */ 1298#define PSOC_GLOBAL_CONF_BTL_AXUSER_VAL_SHIFT 0 1299#define PSOC_GLOBAL_CONF_BTL_AXUSER_VAL_MASK 0xFFFFFFFF 1300 1301/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0 */ 1302#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC0_SHIFT 0 1303#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC0_MASK 0x3F 1304#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC1_SHIFT 6 1305#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC1_MASK 0xFC0 1306#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC2_SHIFT 12 1307#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC2_MASK 0x3F000 1308#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_SHIFT 18 1309#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_MASK 0xFC0000 1310#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_SHIFT 24 1311#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_MASK 0x3F000000 1312 1313/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1 */ 1314#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC1_SHIFT 0 1315#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC1_MASK 0x3F 1316#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC2_SHIFT 6 1317#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC2_MASK 0xFC0 1318#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_PC_EN_SHIFT 12 1319#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_PC_EN_MASK 0x1000 1320#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_CNT_EN_SHIFT 13 1321#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_CNT_EN_MASK 0x2000 1322#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_SHIFT 14 1323#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_MASK 0x4000 1324#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_SHIFT 16 1325#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_MASK 0xFF0000 1326#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_HBM_NUM_SHIFT 24 1327#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_HBM_NUM_MASK 0x7000000 1328 1329/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2 */ 1330#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_SHIFT 0 1331#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_MASK 0xFFFF 1332#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_SHIFT 16 1333#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_MASK 0xFFFF0000 1334 1335/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3 */ 1336#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP0_SHIFT 0 1337#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP0_MASK 0x7 1338#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP1_SHIFT 3 1339#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP1_MASK 0x38 1340#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP2_SHIFT 6 1341#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP2_MASK 0x1C0 1342#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP3_SHIFT 9 1343#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP3_MASK 0xE00 1344#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP4_SHIFT 12 1345#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP4_MASK 0x7000 1346#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP5_SHIFT 15 1347#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP5_MASK 0x38000 1348 1349/* PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL */ 1350#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_EN_SHIFT 0 1351#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_EN_MASK 0x1 1352#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_AXI_RESP_SHIFT 4 1353#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_AXI_RESP_MASK 0x30 1354#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_HBW_SHIFT 8 1355#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_HBW_MASK 0x100 1356#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_LBW_SHIFT 9 1357#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_LBW_MASK 0x200 1358#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_HBW_SHIFT 12 1359#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_HBW_MASK 0x1000 1360#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_LBW_SHIFT 13 1361#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_LBW_MASK 0x2000 1362 1363/* PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT */ 1364#define PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT_VAL_SHIFT 0 1365#define PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT_VAL_MASK 0xFFFFFFFF 1366 1367/* PSOC_GLOBAL_CONF_AXI_DRAIN_INTR */ 1368#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_HBW_IND_SHIFT 0 1369#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_HBW_IND_MASK 0x1 1370#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_LBW_IND_SHIFT 1 1371#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_LBW_IND_MASK 0x2 1372 1373/* PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK */ 1374#define PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK_VAL_SHIFT 0 1375#define PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK_VAL_MASK 0x1 1376 1377/* PSOC_GLOBAL_CONF_ECO_INTR_CAUSE */ 1378#define PSOC_GLOBAL_CONF_ECO_INTR_CAUSE_IND_SHIFT 0 1379#define PSOC_GLOBAL_CONF_ECO_INTR_CAUSE_IND_MASK 0x1 1380 1381/* PSOC_GLOBAL_CONF_ECO_INTR_CLEAR */ 1382#define PSOC_GLOBAL_CONF_ECO_INTR_CLEAR_IND_SHIFT 0 1383#define PSOC_GLOBAL_CONF_ECO_INTR_CLEAR_IND_MASK 0x1 1384 1385/* PSOC_GLOBAL_CONF_ECO_INTR_MASK */ 1386#define PSOC_GLOBAL_CONF_ECO_INTR_MASK_VAL_SHIFT 0 1387#define PSOC_GLOBAL_CONF_ECO_INTR_MASK_VAL_MASK 0x1 1388 1389/* PSOC_GLOBAL_CONF_DFT_APB_CONTROL */ 1390#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_SPIF_MODE_SHIFT 0 1391#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_SPIF_MODE_MASK 0x1 1392#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_OUT_SHIFT 1 1393#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_OUT_MASK 0xFFFE 1394#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_IN_SHIFT 16 1395#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_IN_MASK 0xFFFF0000 1396 1397#endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */
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