pmmu_pif_regs.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2020 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_PMMU_PIF_REGS_H_
 14#define ASIC_REG_PMMU_PIF_REGS_H_
 15
 16/*
 17 *****************************************
 18 *   PMMU_PIF
 19 *   (Prototype: PIF)
 20 *****************************************
 21 */
 22
 23#define mmPMMU_PIF_WR_CORE_CREDITS_THRESHOLD 0x4D03000
 24
 25#define mmPMMU_PIF_RD_CORE_CREDITS_THRESHOLD 0x4D03004
 26
 27#define mmPMMU_PIF_CORE_CREDITS_THRESHOLD 0x4D03008
 28
 29#define mmPMMU_PIF_CORE_SEPARATION_DISABLE 0x4D0300C
 30
 31#define mmPMMU_PIF_DISABLE_E2E_CREDITS 0x4D03010
 32
 33#define mmPMMU_PIF_RATE_LIMITER_ENABLE 0x4D03014
 34
 35#define mmPMMU_PIF_RATE_LIMITER_TOKEN_RESET 0x4D03018
 36
 37#define mmPMMU_PIF_RATE_LIMITER_SATURATION 0x4D0301C
 38
 39#define mmPMMU_PIF_RATE_LIMITER_TIMEOUT_LSB 0x4D03020
 40
 41#define mmPMMU_PIF_RATE_LIMITER_TIMEOUT_MSB 0x4D03024
 42
 43#define mmPMMU_PIF_ARB_TYPE 0x4D03028
 44
 45#define mmPMMU_PIF_CLOCK_GATE_CONFIG 0x4D0302C
 46
 47#define mmPMMU_PIF_CLOCK_GATE_ACTIVE 0x4D03030
 48
 49#define mmPMMU_PIF_SPI_INTERRUPT_CAUSE 0x4D03034
 50
 51#define mmPMMU_PIF_SPI_INTERRUPT_CAUSE_MASK 0x4D03038
 52
 53#define mmPMMU_PIF_SPI_INTERRUPT_REG 0x4D0303C
 54
 55#define mmPMMU_PIF_SPI_INTERRUPT_MASK 0x4D03040
 56
 57#define mmPMMU_PIF_SEI_INTERRUPT_CAUSE 0x4D03044
 58
 59#define mmPMMU_PIF_SEI_INTERRUPT_CAUSE_MASK 0x4D03048
 60
 61#define mmPMMU_PIF_SEI_INTERRUPT_REG 0x4D0304C
 62
 63#define mmPMMU_PIF_SEI_INTERRUPT_MASK 0x4D03050
 64
 65#define mmPMMU_PIF_DEBUG_BUFFER_CNT_CTRL 0x4D03054
 66
 67#define mmPMMU_PIF_DEBUG_WR_BUF_CNT 0x4D03058
 68
 69#define mmPMMU_PIF_DEBUG_RD_BUF_CNT 0x4D0305C
 70
 71#define mmPMMU_PIF_DEBUG_WR_CORE_BUF_CNT 0x4D03060
 72
 73#define mmPMMU_PIF_DEBUG_RD_CORE_BUF_CNT 0x4D03070
 74
 75#define mmPMMU_PIF_DEBUG_WR_BUF_FULL 0x4D03080
 76
 77#define mmPMMU_PIF_DEBUG_RD_BUF_FULL 0x4D03084
 78
 79#define mmPMMU_PIF_E2E_ROUTING_CFG 0x4D03090
 80
 81#define mmPMMU_PIF_E2E_ROUTING_CFG2 0x4D03094
 82
 83#define mmPMMU_PIF_SPI_INTERRUPT_CLEAR 0x4D03100
 84
 85#define mmPMMU_PIF_SEI_INTERRUPT_CLEAR 0x4D03104
 86
 87#define mmPMMU_PIF_BASE_ADDR_PMMU 0x4D03200
 88
 89#define mmPMMU_PIF_ADDR_MASK_PMMU 0x4D03204
 90
 91#define mmPMMU_PIF_BASE_ADDR_PCI0 0x4D03208
 92
 93#define mmPMMU_PIF_ADDR_MASK_PCI0 0x4D0320C
 94
 95#define mmPMMU_PIF_BASE_ADDR_PCI2 0x4D03210
 96
 97#define mmPMMU_PIF_ADDR_MASK_PCI1 0x4D03214
 98
 99#define mmPMMU_PIF_BASE_ADDR_PCI1 0x4D03218
100
101#define mmPMMU_PIF_ADDR_MASK_PCI2 0x4D0321C
102
103#define mmPMMU_PIF_BASE_ADDR_TPC 0x4D03220
104
105#define mmPMMU_PIF_ADDR_MASK_TPC 0x4D03224
106
107#define mmPMMU_PIF_BASE_ADDR_DEC0 0x4D03228
108
109#define mmPMMU_PIF_ADDR_MASK_DEC0 0x4D0322C
110
111#define mmPMMU_PIF_BASE_ADDR_DEC1 0x4D03230
112
113#define mmPMMU_PIF_ADDR_MASK_DEC1 0x4D03234
114
115#define mmPMMU_PIF_PMMU_DBG_BASE_ADDR 0x4D03300
116
117#define mmPMMU_PIF_PMMU_DBG_ADDR_MASK 0x4D03304
118
119#define mmPMMU_PIF_PCI_DBG_BASE_ADDR 0x4D03308
120
121#define mmPMMU_PIF_PCI_DBG_ADDR_MASK 0x4D0330C
122
123#define mmPMMU_PIF_DEC0_DBG_BASE_ADDR 0x4D03310
124
125#define mmPMMU_PIF_DEC0_DBG_ADDR_MASK 0x4D03314
126
127#define mmPMMU_PIF_DEC1_DBG_BASE_ADDR 0x4D03318
128
129#define mmPMMU_PIF_DEC1_DBG_ADDR_MASK 0x4D0331C
130
131#define mmPMMU_PIF_TPC_DBG_BASE_ADDR 0x4D03320
132
133#define mmPMMU_PIF_TPC_DBG_ADDR_MASK 0x4D03324
134
135#endif /* ASIC_REG_PMMU_PIF_REGS_H_ */