pdma0_qm_masks.h

   1/* SPDX-License-Identifier: GPL-2.0
   2 *
   3 * Copyright 2016-2020 HabanaLabs, Ltd.
   4 * All Rights Reserved.
   5 *
   6 */
   7
   8/************************************
   9 ** This is an auto-generated file **
  10 **       DO NOT EDIT BELOW        **
  11 ************************************/
  12
  13#ifndef ASIC_REG_PDMA0_QM_MASKS_H_
  14#define ASIC_REG_PDMA0_QM_MASKS_H_
  15
  16/*
  17 *****************************************
  18 *   PDMA0_QM
  19 *   (Prototype: QMAN)
  20 *****************************************
  21 */
  22
  23/* PDMA0_QM_GLBL_CFG0 */
  24#define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
  25#define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
  26#define PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4
  27#define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
  28#define PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9
  29#define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
  30#define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT 14
  31#define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
  32
  33/* PDMA0_QM_GLBL_CFG1 */
  34#define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
  35#define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
  36#define PDMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4
  37#define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
  38#define PDMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9
  39#define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
  40#define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16
  41#define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
  42#define PDMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20
  43#define PDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
  44#define PDMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25
  45#define PDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000
  46
  47/* PDMA0_QM_GLBL_CFG2 */
  48#define PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_SHIFT 0
  49#define PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 0x1
  50#define PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_SHIFT 1
  51#define PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK 0x2
  52#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_SHIFT 4
  53#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_MASK 0x10
  54#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_SHIFT 5
  55#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_MASK 0x20
  56#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_SHIFT 6
  57#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_MASK 0x40
  58#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_SHIFT 7
  59#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_MASK 0x80
  60#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_SHIFT 8
  61#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_MASK 0x100
  62#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_SHIFT 9
  63#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_MASK 0x200
  64#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_SHIFT 10
  65#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_MASK 0x400
  66#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_SHIFT 11
  67#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_MASK 0x800
  68#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_SHIFT 12
  69#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_MASK 0x1000
  70#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_SHIFT 13
  71#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_MASK 0x2000
  72#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_SHIFT 14
  73#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_MASK 0x4000
  74#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_SHIFT 15
  75#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_MASK 0x8000
  76#define PDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_SHIFT 16
  77#define PDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_MASK 0x10000
  78
  79/* PDMA0_QM_GLBL_ERR_CFG */
  80#define PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0
  81#define PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF
  82#define PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4
  83#define PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0
  84#define PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9
  85#define PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00
  86#define PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16
  87#define PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000
  88#define PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20
  89#define PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000
  90#define PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25
  91#define PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000
  92#define PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31
  93#define PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000
  94
  95/* PDMA0_QM_GLBL_ERR_CFG1 */
  96#define PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT 0
  97#define PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_MASK 0x1
  98#define PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT 1
  99#define PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_MASK 0x2
 100#define PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT 2
 101#define PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_MASK 0x4
 102
 103/* PDMA0_QM_GLBL_ERR_ARC_HALT_EN */
 104#define PDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_SHIFT 0
 105#define PDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_MASK 0xFFFFFF
 106
 107/* PDMA0_QM_GLBL_AXCACHE */
 108#define PDMA0_QM_GLBL_AXCACHE_HBW_AR_SHIFT 0
 109#define PDMA0_QM_GLBL_AXCACHE_HBW_AR_MASK 0xF
 110#define PDMA0_QM_GLBL_AXCACHE_HBW_AW_SHIFT 16
 111#define PDMA0_QM_GLBL_AXCACHE_HBW_AW_MASK 0xF0000
 112#define PDMA0_QM_GLBL_AXCACHE_LBW_AW_SHIFT 20
 113#define PDMA0_QM_GLBL_AXCACHE_LBW_AW_MASK 0xF00000
 114#define PDMA0_QM_GLBL_AXCACHE_LBW_AR_SHIFT 24
 115#define PDMA0_QM_GLBL_AXCACHE_LBW_AR_MASK 0xF000000
 116
 117/* PDMA0_QM_GLBL_STS0 */
 118#define PDMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0
 119#define PDMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF
 120#define PDMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4
 121#define PDMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0
 122#define PDMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9
 123#define PDMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00
 124#define PDMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16
 125#define PDMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000
 126#define PDMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20
 127#define PDMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000
 128#define PDMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25
 129#define PDMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000
 130#define PDMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31
 131#define PDMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000
 132
 133/* PDMA0_QM_GLBL_STS1 */
 134#define PDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_SHIFT 0
 135#define PDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 0x1
 136#define PDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_SHIFT 1
 137#define PDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_MASK 0x2
 138
 139/* PDMA0_QM_GLBL_ERR_STS */
 140#define PDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_SHIFT 0
 141#define PDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_MASK 0x1
 142#define PDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_SHIFT 1
 143#define PDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_MASK 0x2
 144#define PDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_SHIFT 2
 145#define PDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_MASK 0x4
 146#define PDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_SHIFT 3
 147#define PDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_MASK 0x8
 148#define PDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_SHIFT 4
 149#define PDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_MASK 0x10
 150#define PDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_SHIFT 5
 151#define PDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_MASK 0x20
 152#define PDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_SHIFT 6
 153#define PDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_MASK 0x40
 154#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_SHIFT 8
 155#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_MASK 0x100
 156#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_SHIFT 9
 157#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_MASK 0x200
 158#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_SHIFT 10
 159#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_MASK 0x400
 160#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_SHIFT 11
 161#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_MASK 0x800
 162#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_SHIFT 12
 163#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_MASK 0x1000
 164#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_SHIFT 13
 165#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_MASK 0x2000
 166#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_SHIFT 14
 167#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_MASK 0x4000
 168#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_SHIFT 15
 169#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_MASK 0x8000
 170#define PDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_SHIFT 16
 171#define PDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_MASK 0x10000
 172#define PDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_SHIFT 17
 173#define PDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_MASK 0x20000
 174#define PDMA0_QM_GLBL_ERR_STS_RSVD_18_24_SHIFT 18
 175#define PDMA0_QM_GLBL_ERR_STS_RSVD_18_24_MASK 0x1FC0000
 176
 177/* PDMA0_QM_GLBL_ERR_STS_4 */
 178#define PDMA0_QM_GLBL_ERR_STS_4_RSVD0_SHIFT 0
 179#define PDMA0_QM_GLBL_ERR_STS_4_RSVD0_MASK 0x1
 180#define PDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_SHIFT 1
 181#define PDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_MASK 0x2
 182#define PDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_SHIFT 2
 183#define PDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_MASK 0x4
 184#define PDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_SHIFT 3
 185#define PDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_MASK 0x8
 186#define PDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_SHIFT 4
 187#define PDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_MASK 0x10
 188#define PDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_SHIFT 5
 189#define PDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_MASK 0x20
 190#define PDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_SHIFT 6
 191#define PDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_MASK 0x40
 192#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_SHIFT 8
 193#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_MASK 0x100
 194#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_SHIFT 9
 195#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_MASK 0x200
 196#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_SHIFT 10
 197#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_MASK 0x400
 198#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_SHIFT 11
 199#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_MASK 0x800
 200#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_SHIFT 12
 201#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_MASK 0x1000
 202#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_SHIFT 13
 203#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_MASK 0x2000
 204#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_SHIFT 14
 205#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_MASK 0x4000
 206#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_SHIFT 15
 207#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_MASK 0x8000
 208#define PDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_SHIFT 16
 209#define PDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_MASK 0x10000
 210#define PDMA0_QM_GLBL_ERR_STS_4_RSVD17_SHIFT 17
 211#define PDMA0_QM_GLBL_ERR_STS_4_RSVD17_MASK 0x20000
 212#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18
 213#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000
 214#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_SHIFT 19
 215#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_MASK 0x80000
 216#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_SHIFT 20
 217#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_MASK 0x100000
 218#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21
 219#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000
 220#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22
 221#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000
 222#define PDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_SHIFT 23
 223#define PDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_MASK 0x800000
 224#define PDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_SHIFT 24
 225#define PDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_MASK 0x1000000
 226
 227/* PDMA0_QM_GLBL_ERR_MSG_EN */
 228#define PDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_SHIFT 0
 229#define PDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_MASK 0x1
 230#define PDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_SHIFT 1
 231#define PDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_MASK 0x2
 232#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_SHIFT 2
 233#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_MASK 0x4
 234#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3
 235#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8
 236#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_SHIFT 4
 237#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_MASK 0x10
 238#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_SHIFT 5
 239#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_MASK 0x20
 240#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_SHIFT 6
 241#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_MASK 0x40
 242#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8
 243#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
 244#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9
 245#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200
 246#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10
 247#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400
 248#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11
 249#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
 250#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12
 251#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000
 252#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13
 253#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000
 254#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14
 255#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000
 256#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15
 257#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000
 258#define PDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_SHIFT 16
 259#define PDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_MASK 0x10000
 260#define PDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_SHIFT 17
 261#define PDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_MASK 0x20000
 262#define PDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_SHIFT 18
 263#define PDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_MASK 0x1FC0000
 264
 265/* PDMA0_QM_GLBL_ERR_MSG_EN_4 */
 266#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_SHIFT 0
 267#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_MASK 0x1
 268#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_SHIFT 1
 269#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_MASK 0x2
 270#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_SHIFT 2
 271#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_MASK 0x4
 272#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3
 273#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8
 274#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_SHIFT 4
 275#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_MASK 0x10
 276#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5
 277#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20
 278#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_SHIFT 6
 279#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_MASK 0x40
 280#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8
 281#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
 282#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9
 283#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200
 284#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10
 285#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400
 286#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11
 287#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
 288#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12
 289#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000
 290#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13
 291#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000
 292#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14
 293#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000
 294#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15
 295#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000
 296#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_SHIFT 16
 297#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_MASK 0x10000
 298#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_SHIFT 17
 299#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_MASK 0x20000
 300#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18
 301#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000
 302#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_SHIFT 19
 303#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_MASK 0x80000
 304#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_SHIFT 20
 305#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_MASK 0x100000
 306#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21
 307#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000
 308#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22
 309#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000
 310#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_SHIFT 23
 311#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_MASK 0x800000
 312#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_SHIFT 24
 313#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_MASK 0x1000000
 314
 315/* PDMA0_QM_GLBL_PROT */
 316#define PDMA0_QM_GLBL_PROT_PQF_SHIFT 0
 317#define PDMA0_QM_GLBL_PROT_PQF_MASK 0xF
 318#define PDMA0_QM_GLBL_PROT_CQF_SHIFT 4
 319#define PDMA0_QM_GLBL_PROT_CQF_MASK 0x1F0
 320#define PDMA0_QM_GLBL_PROT_CP_SHIFT 9
 321#define PDMA0_QM_GLBL_PROT_CP_MASK 0x3E00
 322#define PDMA0_QM_GLBL_PROT_ERR_SHIFT 14
 323#define PDMA0_QM_GLBL_PROT_ERR_MASK 0x4000
 324#define PDMA0_QM_GLBL_PROT_ARB_SHIFT 15
 325#define PDMA0_QM_GLBL_PROT_ARB_MASK 0x8000
 326#define PDMA0_QM_GLBL_PROT_PQC_SHIFT 16
 327#define PDMA0_QM_GLBL_PROT_PQC_MASK 0x10000
 328#define PDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_SHIFT 17
 329#define PDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_MASK 0x20000
 330#define PDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_SHIFT 18
 331#define PDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_MASK 0x40000
 332#define PDMA0_QM_GLBL_PROT_CQ_CTL_MSG_SHIFT 19
 333#define PDMA0_QM_GLBL_PROT_CQ_CTL_MSG_MASK 0x80000
 334#define PDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_SHIFT 20
 335#define PDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_MASK 0x100000
 336#define PDMA0_QM_GLBL_PROT_CP_WR_ARC_SHIFT 21
 337#define PDMA0_QM_GLBL_PROT_CP_WR_ARC_MASK 0x200000
 338#define PDMA0_QM_GLBL_PROT_ARC_CQF_SHIFT 22
 339#define PDMA0_QM_GLBL_PROT_ARC_CQF_MASK 0x400000
 340#define PDMA0_QM_GLBL_PROT_ARC_CORE_SHIFT 23
 341#define PDMA0_QM_GLBL_PROT_ARC_CORE_MASK 0x800000
 342
 343/* PDMA0_QM_PQ_BASE_LO */
 344#define PDMA0_QM_PQ_BASE_LO_VAL_SHIFT 0
 345#define PDMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF
 346
 347/* PDMA0_QM_PQ_BASE_HI */
 348#define PDMA0_QM_PQ_BASE_HI_VAL_SHIFT 0
 349#define PDMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF
 350
 351/* PDMA0_QM_PQ_SIZE */
 352#define PDMA0_QM_PQ_SIZE_VAL_SHIFT 0
 353#define PDMA0_QM_PQ_SIZE_VAL_MASK 0x1F
 354
 355/* PDMA0_QM_PQ_PI */
 356#define PDMA0_QM_PQ_PI_VAL_SHIFT 0
 357#define PDMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF
 358
 359/* PDMA0_QM_PQ_CI */
 360#define PDMA0_QM_PQ_CI_VAL_SHIFT 0
 361#define PDMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF
 362
 363/* PDMA0_QM_PQ_CFG0 */
 364#define PDMA0_QM_PQ_CFG0_FORCE_STALL_SHIFT 0
 365#define PDMA0_QM_PQ_CFG0_FORCE_STALL_MASK 0x1
 366
 367/* PDMA0_QM_PQ_CFG1 */
 368#define PDMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0
 369#define PDMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFF
 370#define PDMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16
 371#define PDMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000
 372
 373/* PDMA0_QM_PQ_STS0 */
 374#define PDMA0_QM_PQ_STS0_CREDIT_CNT_SHIFT 0
 375#define PDMA0_QM_PQ_STS0_CREDIT_CNT_MASK 0xFF
 376#define PDMA0_QM_PQ_STS0_FREE_CNT_SHIFT 8
 377#define PDMA0_QM_PQ_STS0_FREE_CNT_MASK 0xFF00
 378#define PDMA0_QM_PQ_STS0_INFLIGHT_CNT_SHIFT 16
 379#define PDMA0_QM_PQ_STS0_INFLIGHT_CNT_MASK 0xFF0000
 380
 381/* PDMA0_QM_PQ_STS1 */
 382#define PDMA0_QM_PQ_STS1_BUF_EMPTY_SHIFT 0
 383#define PDMA0_QM_PQ_STS1_BUF_EMPTY_MASK 0x1
 384#define PDMA0_QM_PQ_STS1_BUSY_SHIFT 1
 385#define PDMA0_QM_PQ_STS1_BUSY_MASK 0x2
 386
 387/* PDMA0_QM_CQ_CFG0 */
 388#define PDMA0_QM_CQ_CFG0_IF_B2B_EN_SHIFT 0
 389#define PDMA0_QM_CQ_CFG0_IF_B2B_EN_MASK 0x1
 390#define PDMA0_QM_CQ_CFG0_IF_MSG_EN_SHIFT 1
 391#define PDMA0_QM_CQ_CFG0_IF_MSG_EN_MASK 0x2
 392#define PDMA0_QM_CQ_CFG0_CTL_MSG_EN_SHIFT 2
 393#define PDMA0_QM_CQ_CFG0_CTL_MSG_EN_MASK 0x4
 394
 395/* PDMA0_QM_CQ_STS0 */
 396#define PDMA0_QM_CQ_STS0_CREDIT_CNT_SHIFT 0
 397#define PDMA0_QM_CQ_STS0_CREDIT_CNT_MASK 0xFF
 398#define PDMA0_QM_CQ_STS0_FREE_CNT_SHIFT 8
 399#define PDMA0_QM_CQ_STS0_FREE_CNT_MASK 0xFF00
 400#define PDMA0_QM_CQ_STS0_INFLIGHT_CNT_SHIFT 16
 401#define PDMA0_QM_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000
 402
 403/* PDMA0_QM_CQ_CFG1 */
 404#define PDMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0
 405#define PDMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFF
 406#define PDMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16
 407#define PDMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000
 408
 409/* PDMA0_QM_CQ_STS1 */
 410#define PDMA0_QM_CQ_STS1_BUF_EMPTY_SHIFT 0
 411#define PDMA0_QM_CQ_STS1_BUF_EMPTY_MASK 0x1
 412#define PDMA0_QM_CQ_STS1_BUSY_SHIFT 1
 413#define PDMA0_QM_CQ_STS1_BUSY_MASK 0x2
 414
 415/* PDMA0_QM_CQ_PTR_LO_0 */
 416#define PDMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0
 417#define PDMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF
 418
 419/* PDMA0_QM_CQ_PTR_HI_0 */
 420#define PDMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0
 421#define PDMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF
 422
 423/* PDMA0_QM_CQ_TSIZE_0 */
 424#define PDMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0
 425#define PDMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF
 426
 427/* PDMA0_QM_CQ_CTL_0 */
 428#define PDMA0_QM_CQ_CTL_0_UP_SHIFT 28
 429#define PDMA0_QM_CQ_CTL_0_UP_MASK 0xF0000000
 430
 431/* PDMA0_QM_CQ_PTR_LO_1 */
 432#define PDMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0
 433#define PDMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF
 434
 435/* PDMA0_QM_CQ_PTR_HI_1 */
 436#define PDMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0
 437#define PDMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF
 438
 439/* PDMA0_QM_CQ_TSIZE_1 */
 440#define PDMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0
 441#define PDMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF
 442
 443/* PDMA0_QM_CQ_CTL_1 */
 444#define PDMA0_QM_CQ_CTL_1_UP_SHIFT 28
 445#define PDMA0_QM_CQ_CTL_1_UP_MASK 0xF0000000
 446
 447/* PDMA0_QM_CQ_PTR_LO_2 */
 448#define PDMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0
 449#define PDMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF
 450
 451/* PDMA0_QM_CQ_PTR_HI_2 */
 452#define PDMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0
 453#define PDMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF
 454
 455/* PDMA0_QM_CQ_TSIZE_2 */
 456#define PDMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0
 457#define PDMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF
 458
 459/* PDMA0_QM_CQ_CTL_2 */
 460#define PDMA0_QM_CQ_CTL_2_UP_SHIFT 28
 461#define PDMA0_QM_CQ_CTL_2_UP_MASK 0xF0000000
 462
 463/* PDMA0_QM_CQ_PTR_LO_3 */
 464#define PDMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0
 465#define PDMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF
 466
 467/* PDMA0_QM_CQ_PTR_HI_3 */
 468#define PDMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0
 469#define PDMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF
 470
 471/* PDMA0_QM_CQ_TSIZE_3 */
 472#define PDMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0
 473#define PDMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF
 474
 475/* PDMA0_QM_CQ_CTL_3 */
 476#define PDMA0_QM_CQ_CTL_3_UP_SHIFT 28
 477#define PDMA0_QM_CQ_CTL_3_UP_MASK 0xF0000000
 478
 479/* PDMA0_QM_CQ_PTR_LO_4 */
 480#define PDMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0
 481#define PDMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF
 482
 483/* PDMA0_QM_CQ_PTR_HI_4 */
 484#define PDMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0
 485#define PDMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF
 486
 487/* PDMA0_QM_CQ_TSIZE_4 */
 488#define PDMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0
 489#define PDMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF
 490
 491/* PDMA0_QM_CQ_CTL_4 */
 492#define PDMA0_QM_CQ_CTL_4_UP_SHIFT 28
 493#define PDMA0_QM_CQ_CTL_4_UP_MASK 0xF0000000
 494
 495/* PDMA0_QM_CQ_TSIZE_STS */
 496#define PDMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0
 497#define PDMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF
 498
 499/* PDMA0_QM_CQ_PTR_LO_STS */
 500#define PDMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0
 501#define PDMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF
 502
 503/* PDMA0_QM_CQ_PTR_HI_STS */
 504#define PDMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0
 505#define PDMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF
 506
 507/* PDMA0_QM_CQ_IFIFO_STS */
 508#define PDMA0_QM_CQ_IFIFO_STS_CNT_SHIFT 0
 509#define PDMA0_QM_CQ_IFIFO_STS_CNT_MASK 0x7
 510#define PDMA0_QM_CQ_IFIFO_STS_RDY_SHIFT 4
 511#define PDMA0_QM_CQ_IFIFO_STS_RDY_MASK 0x10
 512#define PDMA0_QM_CQ_IFIFO_STS_CTL_STALL_SHIFT 8
 513#define PDMA0_QM_CQ_IFIFO_STS_CTL_STALL_MASK 0x100
 514
 515/* PDMA0_QM_CP_MSG_BASE0_ADDR_LO */
 516#define PDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0
 517#define PDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF
 518
 519/* PDMA0_QM_CP_MSG_BASE0_ADDR_HI */
 520#define PDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0
 521#define PDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF
 522
 523/* PDMA0_QM_CP_MSG_BASE1_ADDR_LO */
 524#define PDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0
 525#define PDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF
 526
 527/* PDMA0_QM_CP_MSG_BASE1_ADDR_HI */
 528#define PDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0
 529#define PDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF
 530
 531/* PDMA0_QM_CP_MSG_BASE2_ADDR_LO */
 532#define PDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0
 533#define PDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF
 534
 535/* PDMA0_QM_CP_MSG_BASE2_ADDR_HI */
 536#define PDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0
 537#define PDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF
 538
 539/* PDMA0_QM_CP_MSG_BASE3_ADDR_LO */
 540#define PDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0
 541#define PDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF
 542
 543/* PDMA0_QM_CP_MSG_BASE3_ADDR_HI */
 544#define PDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0
 545#define PDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF
 546
 547/* PDMA0_QM_CP_FENCE0_RDATA */
 548#define PDMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0
 549#define PDMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF
 550
 551/* PDMA0_QM_CP_FENCE1_RDATA */
 552#define PDMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0
 553#define PDMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF
 554
 555/* PDMA0_QM_CP_FENCE2_RDATA */
 556#define PDMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0
 557#define PDMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF
 558
 559/* PDMA0_QM_CP_FENCE3_RDATA */
 560#define PDMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0
 561#define PDMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF
 562
 563/* PDMA0_QM_CP_FENCE0_CNT */
 564#define PDMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0
 565#define PDMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF
 566
 567/* PDMA0_QM_CP_FENCE1_CNT */
 568#define PDMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0
 569#define PDMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF
 570
 571/* PDMA0_QM_CP_FENCE2_CNT */
 572#define PDMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0
 573#define PDMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF
 574
 575/* PDMA0_QM_CP_FENCE3_CNT */
 576#define PDMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0
 577#define PDMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF
 578
 579/* PDMA0_QM_CP_BARRIER_CFG */
 580#define PDMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0
 581#define PDMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF
 582#define PDMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16
 583#define PDMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000
 584
 585/* PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */
 586#define PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0
 587#define PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFF
 588
 589/* PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */
 590#define PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0
 591#define PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFF
 592
 593/* PDMA0_QM_CP_LDMA_TSIZE_OFFSET */
 594#define PDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0
 595#define PDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFF
 596
 597/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 */
 598#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_SHIFT 0
 599#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_MASK 0xFFFF
 600
 601/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 */
 602#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_SHIFT 0
 603#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_MASK 0xFFFF
 604
 605/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 */
 606#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_SHIFT 0
 607#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_MASK 0xFFFF
 608
 609/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 */
 610#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_SHIFT 0
 611#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_MASK 0xFFFF
 612
 613/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 */
 614#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_SHIFT 0
 615#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_MASK 0xFFFF
 616
 617/* PDMA0_QM_CP_STS */
 618#define PDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0
 619#define PDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFF
 620#define PDMA0_QM_CP_STS_ERDY_SHIFT 8
 621#define PDMA0_QM_CP_STS_ERDY_MASK 0x100
 622#define PDMA0_QM_CP_STS_SWITCH_EN_SHIFT 9
 623#define PDMA0_QM_CP_STS_SWITCH_EN_MASK 0x200
 624#define PDMA0_QM_CP_STS_MRDY_SHIFT 10
 625#define PDMA0_QM_CP_STS_MRDY_MASK 0x400
 626#define PDMA0_QM_CP_STS_SW_STOP_SHIFT 11
 627#define PDMA0_QM_CP_STS_SW_STOP_MASK 0x800
 628#define PDMA0_QM_CP_STS_FENCE_ID_SHIFT 12
 629#define PDMA0_QM_CP_STS_FENCE_ID_MASK 0x3000
 630#define PDMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 14
 631#define PDMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x4000
 632#define PDMA0_QM_CP_STS_FENCE_TARGET_SHIFT 16
 633#define PDMA0_QM_CP_STS_FENCE_TARGET_MASK 0x3FFF0000
 634#define PDMA0_QM_CP_STS_CUR_CQ_SHIFT 30
 635#define PDMA0_QM_CP_STS_CUR_CQ_MASK 0x40000000
 636
 637/* PDMA0_QM_CP_CURRENT_INST_LO */
 638#define PDMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0
 639#define PDMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF
 640
 641/* PDMA0_QM_CP_CURRENT_INST_HI */
 642#define PDMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0
 643#define PDMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF
 644
 645/* PDMA0_QM_CP_PRED */
 646#define PDMA0_QM_CP_PRED_VAL_SHIFT 0
 647#define PDMA0_QM_CP_PRED_VAL_MASK 0xFFFFFFFF
 648
 649/* PDMA0_QM_CP_PRED_UPEN */
 650#define PDMA0_QM_CP_PRED_UPEN_VAL_SHIFT 0
 651#define PDMA0_QM_CP_PRED_UPEN_VAL_MASK 0xFFFFFFFF
 652
 653/* PDMA0_QM_CP_DBG_0 */
 654#define PDMA0_QM_CP_DBG_0_CS_SHIFT 0
 655#define PDMA0_QM_CP_DBG_0_CS_MASK 0x1F
 656#define PDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 5
 657#define PDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x20
 658#define PDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 6
 659#define PDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x40
 660#define PDMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 7
 661#define PDMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x80
 662#define PDMA0_QM_CP_DBG_0_STALL_SHIFT 8
 663#define PDMA0_QM_CP_DBG_0_STALL_MASK 0x100
 664
 665/* PDMA0_QM_CP_CPDMA_UP_CRED */
 666#define PDMA0_QM_CP_CPDMA_UP_CRED_TH_SHIFT 0
 667#define PDMA0_QM_CP_CPDMA_UP_CRED_TH_MASK 0x3
 668#define PDMA0_QM_CP_CPDMA_UP_CRED_VAL_SHIFT 8
 669#define PDMA0_QM_CP_CPDMA_UP_CRED_VAL_MASK 0x300
 670
 671/* PDMA0_QM_CP_IN_DATA_LO */
 672#define PDMA0_QM_CP_IN_DATA_LO_VAL_SHIFT 0
 673#define PDMA0_QM_CP_IN_DATA_LO_VAL_MASK 0xFFFFFFFF
 674
 675/* PDMA0_QM_CP_IN_DATA_HI */
 676#define PDMA0_QM_CP_IN_DATA_HI_VAL_SHIFT 0
 677#define PDMA0_QM_CP_IN_DATA_HI_VAL_MASK 0xFFFFFFFF
 678
 679/* PDMA0_QM_PQC_HBW_BASE_LO */
 680#define PDMA0_QM_PQC_HBW_BASE_LO_VAL_SHIFT 0
 681#define PDMA0_QM_PQC_HBW_BASE_LO_VAL_MASK 0xFFFFFFFF
 682
 683/* PDMA0_QM_PQC_HBW_BASE_HI */
 684#define PDMA0_QM_PQC_HBW_BASE_HI_VAL_SHIFT 0
 685#define PDMA0_QM_PQC_HBW_BASE_HI_VAL_MASK 0xFFFFFFFF
 686
 687/* PDMA0_QM_PQC_SIZE */
 688#define PDMA0_QM_PQC_SIZE_VAL_SHIFT 0
 689#define PDMA0_QM_PQC_SIZE_VAL_MASK 0xFFFFFFFF
 690
 691/* PDMA0_QM_PQC_PI */
 692#define PDMA0_QM_PQC_PI_VAL_SHIFT 0
 693#define PDMA0_QM_PQC_PI_VAL_MASK 0xFFFFFFFF
 694
 695/* PDMA0_QM_PQC_LBW_WDATA */
 696#define PDMA0_QM_PQC_LBW_WDATA_VAL_SHIFT 0
 697#define PDMA0_QM_PQC_LBW_WDATA_VAL_MASK 0xFFFFFFFF
 698
 699/* PDMA0_QM_PQC_LBW_BASE_LO */
 700#define PDMA0_QM_PQC_LBW_BASE_LO_VAL_SHIFT 0
 701#define PDMA0_QM_PQC_LBW_BASE_LO_VAL_MASK 0xFFFFFFFF
 702
 703/* PDMA0_QM_PQC_LBW_BASE_HI */
 704#define PDMA0_QM_PQC_LBW_BASE_HI_VAL_SHIFT 0
 705#define PDMA0_QM_PQC_LBW_BASE_HI_VAL_MASK 0xFFFFFFFF
 706
 707/* PDMA0_QM_PQC_CFG */
 708#define PDMA0_QM_PQC_CFG_EN_SHIFT 0
 709#define PDMA0_QM_PQC_CFG_EN_MASK 0x1
 710#define PDMA0_QM_PQC_CFG_DIRECT_SHIFT 4
 711#define PDMA0_QM_PQC_CFG_DIRECT_MASK 0x10
 712
 713/* PDMA0_QM_PQC_SECURE_PUSH_IND */
 714#define PDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0
 715#define PDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3
 716
 717/* PDMA0_QM_ARB_MASK */
 718#define PDMA0_QM_ARB_MASK_VAL_SHIFT 0
 719#define PDMA0_QM_ARB_MASK_VAL_MASK 0xF
 720
 721/* PDMA0_QM_ARB_CFG_0 */
 722#define PDMA0_QM_ARB_CFG_0_PRIO_TYPE_SHIFT 0
 723#define PDMA0_QM_ARB_CFG_0_PRIO_TYPE_MASK 0x1
 724#define PDMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4
 725#define PDMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10
 726#define PDMA0_QM_ARB_CFG_0_EN_SHIFT 8
 727#define PDMA0_QM_ARB_CFG_0_EN_MASK 0x100
 728#define PDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 9
 729#define PDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x200
 730
 731/* PDMA0_QM_ARB_CHOICE_Q_PUSH */
 732#define PDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_SHIFT 0
 733#define PDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_MASK 0x3
 734
 735/* PDMA0_QM_ARB_WRR_WEIGHT */
 736#define PDMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0
 737#define PDMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFF
 738
 739/* PDMA0_QM_ARB_CFG_1 */
 740#define PDMA0_QM_ARB_CFG_1_CLR_SHIFT 0
 741#define PDMA0_QM_ARB_CFG_1_CLR_MASK 0x1
 742
 743/* PDMA0_QM_ARB_MST_AVAIL_CRED */
 744#define PDMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0
 745#define PDMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F
 746
 747/* PDMA0_QM_ARB_MST_CRED_INC */
 748#define PDMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0
 749#define PDMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF
 750
 751/* PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST */
 752#define PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_SHIFT 0
 753#define PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_MASK 0xFFFFFFFF
 754
 755/* PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */
 756#define PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0
 757#define PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF
 758
 759/* PDMA0_QM_ARB_MST_SLAVE_EN */
 760#define PDMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0
 761#define PDMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF
 762
 763/* PDMA0_QM_ARB_MST_SLAVE_EN_1 */
 764#define PDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_SHIFT 0
 765#define PDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_MASK 0xFFFFFFFF
 766
 767/* PDMA0_QM_ARB_SLV_CHOICE_WDT */
 768#define PDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_SHIFT 0
 769#define PDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_MASK 0xFFFFFFFF
 770
 771/* PDMA0_QM_ARB_SLV_ID */
 772#define PDMA0_QM_ARB_SLV_ID_VAL_SHIFT 0
 773#define PDMA0_QM_ARB_SLV_ID_VAL_MASK 0x7F
 774
 775/* PDMA0_QM_ARB_MST_QUIET_PER */
 776#define PDMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0
 777#define PDMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF
 778
 779/* PDMA0_QM_ARB_MSG_MAX_INFLIGHT */
 780#define PDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0
 781#define PDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F
 782
 783/* PDMA0_QM_ARB_BASE_LO */
 784#define PDMA0_QM_ARB_BASE_LO_VAL_SHIFT 0
 785#define PDMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF
 786
 787/* PDMA0_QM_ARB_BASE_HI */
 788#define PDMA0_QM_ARB_BASE_HI_VAL_SHIFT 0
 789#define PDMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF
 790
 791/* PDMA0_QM_ARB_STATE_STS */
 792#define PDMA0_QM_ARB_STATE_STS_VAL_SHIFT 0
 793#define PDMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF
 794
 795/* PDMA0_QM_ARB_CHOICE_FULLNESS_STS */
 796#define PDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_SHIFT 0
 797#define PDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_MASK 0x7F
 798
 799/* PDMA0_QM_ARB_MSG_STS */
 800#define PDMA0_QM_ARB_MSG_STS_FULL_SHIFT 0
 801#define PDMA0_QM_ARB_MSG_STS_FULL_MASK 0x1
 802#define PDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1
 803#define PDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2
 804
 805/* PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD */
 806#define PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_SHIFT 0
 807#define PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_MASK 0x3
 808
 809/* PDMA0_QM_ARB_ERR_CAUSE */
 810#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_SHIFT 0
 811#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_MASK 0x1
 812#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_SHIFT 1
 813#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_MASK 0x2
 814#define PDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2
 815#define PDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4
 816
 817/* PDMA0_QM_ARB_ERR_MSG_EN */
 818#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_SHIFT 0
 819#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_MASK 0x1
 820#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_SHIFT 1
 821#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_MASK 0x2
 822#define PDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2
 823#define PDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4
 824
 825/* PDMA0_QM_ARB_ERR_STS_DRP */
 826#define PDMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0
 827#define PDMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3
 828
 829/* PDMA0_QM_ARB_MST_CRED_STS */
 830#define PDMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0
 831#define PDMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F
 832#define PDMA0_QM_ARB_MST_CRED_STS_IDX_SHIFT 24
 833#define PDMA0_QM_ARB_MST_CRED_STS_IDX_MASK 0x1F000000
 834
 835/* PDMA0_QM_ARB_MST_CRED_STS_1 */
 836#define PDMA0_QM_ARB_MST_CRED_STS_1_VAL_SHIFT 0
 837#define PDMA0_QM_ARB_MST_CRED_STS_1_VAL_MASK 0x7F
 838#define PDMA0_QM_ARB_MST_CRED_STS_1_IDX_SHIFT 24
 839#define PDMA0_QM_ARB_MST_CRED_STS_1_IDX_MASK 0x1F000000
 840
 841/* PDMA0_QM_CSMR_STRICT_PRIO_CFG */
 842#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_SHIFT 0
 843#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_MASK 0x1
 844#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_SHIFT 4
 845#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_MASK 0x10
 846
 847/* PDMA0_QM_ARC_CQ_CFG0 */
 848#define PDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_SHIFT 0
 849#define PDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_MASK 0x1
 850#define PDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_SHIFT 1
 851#define PDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_MASK 0x2
 852#define PDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_SHIFT 2
 853#define PDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_MASK 0x4
 854
 855/* PDMA0_QM_ARC_CQ_CFG1 */
 856#define PDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_SHIFT 0
 857#define PDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_MASK 0xFF
 858#define PDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_SHIFT 16
 859#define PDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000
 860
 861/* PDMA0_QM_ARC_CQ_PTR_LO */
 862#define PDMA0_QM_ARC_CQ_PTR_LO_VAL_SHIFT 0
 863#define PDMA0_QM_ARC_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF
 864
 865/* PDMA0_QM_ARC_CQ_PTR_HI */
 866#define PDMA0_QM_ARC_CQ_PTR_HI_VAL_SHIFT 0
 867#define PDMA0_QM_ARC_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF
 868
 869/* PDMA0_QM_ARC_CQ_TSIZE */
 870#define PDMA0_QM_ARC_CQ_TSIZE_VAL_SHIFT 0
 871#define PDMA0_QM_ARC_CQ_TSIZE_VAL_MASK 0xFFFFFFFF
 872
 873/* PDMA0_QM_ARC_CQ_CTL */
 874#define PDMA0_QM_ARC_CQ_CTL_UP_SHIFT 28
 875#define PDMA0_QM_ARC_CQ_CTL_UP_MASK 0xF0000000
 876
 877/* PDMA0_QM_ARC_CQ_IFIFO_STS */
 878#define PDMA0_QM_ARC_CQ_IFIFO_STS_CNT_SHIFT 0
 879#define PDMA0_QM_ARC_CQ_IFIFO_STS_CNT_MASK 0x7
 880#define PDMA0_QM_ARC_CQ_IFIFO_STS_RDY_SHIFT 4
 881#define PDMA0_QM_ARC_CQ_IFIFO_STS_RDY_MASK 0x10
 882#define PDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_SHIFT 8
 883#define PDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_MASK 0x100
 884
 885/* PDMA0_QM_ARC_CQ_STS0 */
 886#define PDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_SHIFT 0
 887#define PDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_MASK 0xFF
 888#define PDMA0_QM_ARC_CQ_STS0_FREE_CNT_SHIFT 8
 889#define PDMA0_QM_ARC_CQ_STS0_FREE_CNT_MASK 0xFF00
 890#define PDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_SHIFT 16
 891#define PDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000
 892
 893/* PDMA0_QM_ARC_CQ_STS1 */
 894#define PDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_SHIFT 0
 895#define PDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_MASK 0x1
 896#define PDMA0_QM_ARC_CQ_STS1_BUSY_SHIFT 1
 897#define PDMA0_QM_ARC_CQ_STS1_BUSY_MASK 0x2
 898
 899/* PDMA0_QM_ARC_CQ_TSIZE_STS */
 900#define PDMA0_QM_ARC_CQ_TSIZE_STS_VAL_SHIFT 0
 901#define PDMA0_QM_ARC_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF
 902
 903/* PDMA0_QM_ARC_CQ_PTR_LO_STS */
 904#define PDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_SHIFT 0
 905#define PDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF
 906
 907/* PDMA0_QM_ARC_CQ_PTR_HI_STS */
 908#define PDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_SHIFT 0
 909#define PDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF
 910
 911/* PDMA0_QM_CP_WR_ARC_ADDR_HI */
 912#define PDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_SHIFT 0
 913#define PDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_MASK 0xFFFFFFFF
 914
 915/* PDMA0_QM_CP_WR_ARC_ADDR_LO */
 916#define PDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_SHIFT 0
 917#define PDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_MASK 0xFFFFFFFF
 918
 919/* PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI */
 920#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0
 921#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF
 922
 923/* PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO */
 924#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0
 925#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF
 926
 927/* PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI */
 928#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0
 929#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF
 930
 931/* PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO */
 932#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0
 933#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF
 934
 935/* PDMA0_QM_CQ_IFIFO_MSG_BASE_HI */
 936#define PDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0
 937#define PDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF
 938
 939/* PDMA0_QM_CQ_IFIFO_MSG_BASE_LO */
 940#define PDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0
 941#define PDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF
 942
 943/* PDMA0_QM_CQ_CTL_MSG_BASE_HI */
 944#define PDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0
 945#define PDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF
 946
 947/* PDMA0_QM_CQ_CTL_MSG_BASE_LO */
 948#define PDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0
 949#define PDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF
 950
 951/* PDMA0_QM_ADDR_OVRD */
 952#define PDMA0_QM_ADDR_OVRD_IDX_SHIFT 0
 953#define PDMA0_QM_ADDR_OVRD_IDX_MASK 0xFF
 954
 955/* PDMA0_QM_CQ_IFIFO_CI */
 956#define PDMA0_QM_CQ_IFIFO_CI_VAL_SHIFT 0
 957#define PDMA0_QM_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF
 958
 959/* PDMA0_QM_ARC_CQ_IFIFO_CI */
 960#define PDMA0_QM_ARC_CQ_IFIFO_CI_VAL_SHIFT 0
 961#define PDMA0_QM_ARC_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF
 962
 963/* PDMA0_QM_CQ_CTL_CI */
 964#define PDMA0_QM_CQ_CTL_CI_VAL_SHIFT 0
 965#define PDMA0_QM_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF
 966
 967/* PDMA0_QM_ARC_CQ_CTL_CI */
 968#define PDMA0_QM_ARC_CQ_CTL_CI_VAL_SHIFT 0
 969#define PDMA0_QM_ARC_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF
 970
 971/* PDMA0_QM_CP_CFG */
 972#define PDMA0_QM_CP_CFG_SWITCH_EN_SHIFT 0
 973#define PDMA0_QM_CP_CFG_SWITCH_EN_MASK 0x1
 974#define PDMA0_QM_CP_CFG_SWITCH_WD_EN_SHIFT 1
 975#define PDMA0_QM_CP_CFG_SWITCH_WD_EN_MASK 0x2
 976
 977/* PDMA0_QM_CP_EXT_SWITCH */
 978#define PDMA0_QM_CP_EXT_SWITCH_VAL_SHIFT 0
 979#define PDMA0_QM_CP_EXT_SWITCH_VAL_MASK 0x1
 980
 981/* PDMA0_QM_CP_SWITCH_WD_SET */
 982#define PDMA0_QM_CP_SWITCH_WD_SET_VAL_SHIFT 0
 983#define PDMA0_QM_CP_SWITCH_WD_SET_VAL_MASK 0xFFFFFFFF
 984
 985/* PDMA0_QM_CP_SWITCH_WD */
 986#define PDMA0_QM_CP_SWITCH_WD_VAL_SHIFT 0
 987#define PDMA0_QM_CP_SWITCH_WD_VAL_MASK 0xFFFFFFFF
 988
 989/* PDMA0_QM_ARC_LB_ADDR_BASE_LO */
 990#define PDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_SHIFT 0
 991#define PDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_MASK 0xFFFFFFFF
 992
 993/* PDMA0_QM_ARC_LB_ADDR_BASE_HI */
 994#define PDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_SHIFT 0
 995#define PDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_MASK 0xFFFFFFFF
 996
 997/* PDMA0_QM_ENGINE_BASE_ADDR_HI */
 998#define PDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_SHIFT 0
 999#define PDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF
1000
1001/* PDMA0_QM_ENGINE_BASE_ADDR_LO */
1002#define PDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_SHIFT 0
1003#define PDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF
1004
1005/* PDMA0_QM_ENGINE_ADDR_RANGE_SIZE */
1006#define PDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_SHIFT 0
1007#define PDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_MASK 0xFFFFFFFF
1008
1009/* PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI */
1010#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_SHIFT 0
1011#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF
1012
1013/* PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO */
1014#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_SHIFT 0
1015#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF
1016
1017/* PDMA0_QM_QM_BASE_ADDR_HI */
1018#define PDMA0_QM_QM_BASE_ADDR_HI_VAL_SHIFT 0
1019#define PDMA0_QM_QM_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF
1020
1021/* PDMA0_QM_QM_BASE_ADDR_LO */
1022#define PDMA0_QM_QM_BASE_ADDR_LO_VAL_SHIFT 0
1023#define PDMA0_QM_QM_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF
1024
1025/* PDMA0_QM_ARC_PQC_SECURE_PUSH_IND */
1026#define PDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0
1027#define PDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3
1028
1029/* PDMA0_QM_PQC_STS_0 */
1030#define PDMA0_QM_PQC_STS_0_COMP_DATA_SHIFT 0
1031#define PDMA0_QM_PQC_STS_0_COMP_DATA_MASK 0xFFFF
1032#define PDMA0_QM_PQC_STS_0_COMP_OFST_SHIFT 16
1033#define PDMA0_QM_PQC_STS_0_COMP_OFST_MASK 0xFFFF0000
1034
1035/* PDMA0_QM_PQC_STS_1 */
1036#define PDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_SHIFT 0
1037#define PDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_MASK 0xF
1038#define PDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_SHIFT 4
1039#define PDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_MASK 0x10
1040#define PDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_SHIFT 5
1041#define PDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_MASK 0x20
1042
1043/* PDMA0_QM_SEI_STATUS */
1044#define PDMA0_QM_SEI_STATUS_QM_INT_SHIFT 0
1045#define PDMA0_QM_SEI_STATUS_QM_INT_MASK 0x1
1046#define PDMA0_QM_SEI_STATUS_ARC_INT_SHIFT 1
1047#define PDMA0_QM_SEI_STATUS_ARC_INT_MASK 0x2
1048
1049/* PDMA0_QM_SEI_MASK */
1050#define PDMA0_QM_SEI_MASK_QM_INT_SHIFT 0
1051#define PDMA0_QM_SEI_MASK_QM_INT_MASK 0x1
1052#define PDMA0_QM_SEI_MASK_ARC_INT_SHIFT 1
1053#define PDMA0_QM_SEI_MASK_ARC_INT_MASK 0x2
1054
1055/* PDMA0_QM_GLBL_ERR_ADDR_LO */
1056#define PDMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0
1057#define PDMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF
1058
1059/* PDMA0_QM_GLBL_ERR_ADDR_HI */
1060#define PDMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0
1061#define PDMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF
1062
1063/* PDMA0_QM_GLBL_ERR_WDATA */
1064#define PDMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0
1065#define PDMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF
1066
1067/* PDMA0_QM_L2H_MASK_LO */
1068#define PDMA0_QM_L2H_MASK_LO_VAL_SHIFT 20
1069#define PDMA0_QM_L2H_MASK_LO_VAL_MASK 0xFFF00000
1070
1071/* PDMA0_QM_L2H_MASK_HI */
1072#define PDMA0_QM_L2H_MASK_HI_VAL_SHIFT 0
1073#define PDMA0_QM_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF
1074
1075/* PDMA0_QM_L2H_CMPR_LO */
1076#define PDMA0_QM_L2H_CMPR_LO_VAL_SHIFT 20
1077#define PDMA0_QM_L2H_CMPR_LO_VAL_MASK 0xFFF00000
1078
1079/* PDMA0_QM_L2H_CMPR_HI */
1080#define PDMA0_QM_L2H_CMPR_HI_VAL_SHIFT 0
1081#define PDMA0_QM_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF
1082
1083/* PDMA0_QM_LOCAL_RANGE_BASE */
1084#define PDMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0
1085#define PDMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF
1086
1087/* PDMA0_QM_LOCAL_RANGE_SIZE */
1088#define PDMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0
1089#define PDMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF
1090
1091/* PDMA0_QM_HBW_RD_RATE_LIM_CFG_1 */
1092#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0
1093#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF
1094#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31
1095#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000
1096
1097/* PDMA0_QM_LBW_WR_RATE_LIM_CFG_0 */
1098#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
1099#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
1100#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16
1101#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
1102
1103/* PDMA0_QM_LBW_WR_RATE_LIM_CFG_1 */
1104#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0
1105#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF
1106#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31
1107#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000
1108
1109/* PDMA0_QM_HBW_RD_RATE_LIM_CFG_0 */
1110#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
1111#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
1112#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16
1113#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
1114
1115/* PDMA0_QM_IND_GW_APB_CFG */
1116#define PDMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0
1117#define PDMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF
1118#define PDMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 31
1119#define PDMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000
1120
1121/* PDMA0_QM_IND_GW_APB_WDATA */
1122#define PDMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0
1123#define PDMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF
1124
1125/* PDMA0_QM_IND_GW_APB_RDATA */
1126#define PDMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0
1127#define PDMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF
1128
1129/* PDMA0_QM_IND_GW_APB_STATUS */
1130#define PDMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0
1131#define PDMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1
1132#define PDMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1
1133#define PDMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2
1134
1135/* PDMA0_QM_PERF_CNT_FREE_LO */
1136#define PDMA0_QM_PERF_CNT_FREE_LO_VAL_SHIFT 0
1137#define PDMA0_QM_PERF_CNT_FREE_LO_VAL_MASK 0xFFFFFFFF
1138
1139/* PDMA0_QM_PERF_CNT_FREE_HI */
1140#define PDMA0_QM_PERF_CNT_FREE_HI_VAL_SHIFT 0
1141#define PDMA0_QM_PERF_CNT_FREE_HI_VAL_MASK 0xFFFFFFFF
1142
1143/* PDMA0_QM_PERF_CNT_IDLE_LO */
1144#define PDMA0_QM_PERF_CNT_IDLE_LO_VAL_SHIFT 0
1145#define PDMA0_QM_PERF_CNT_IDLE_LO_VAL_MASK 0xFFFFFFFF
1146
1147/* PDMA0_QM_PERF_CNT_IDLE_HI */
1148#define PDMA0_QM_PERF_CNT_IDLE_HI_VAL_SHIFT 0
1149#define PDMA0_QM_PERF_CNT_IDLE_HI_VAL_MASK 0xFFFFFFFF
1150
1151/* PDMA0_QM_PERF_CNT_CFG */
1152#define PDMA0_QM_PERF_CNT_CFG_PQ_MASK_SHIFT 0
1153#define PDMA0_QM_PERF_CNT_CFG_PQ_MASK_MASK 0xF
1154#define PDMA0_QM_PERF_CNT_CFG_CQ_MASK_SHIFT 8
1155#define PDMA0_QM_PERF_CNT_CFG_CQ_MASK_MASK 0x1F00
1156#define PDMA0_QM_PERF_CNT_CFG_CP_MASK_SHIFT 16
1157#define PDMA0_QM_PERF_CNT_CFG_CP_MASK_MASK 0x1F0000
1158#define PDMA0_QM_PERF_CNT_CFG_AGENT_MASK_SHIFT 24
1159#define PDMA0_QM_PERF_CNT_CFG_AGENT_MASK_MASK 0x1000000
1160#define PDMA0_QM_PERF_CNT_CFG_EN_FREE_SHIFT 30
1161#define PDMA0_QM_PERF_CNT_CFG_EN_FREE_MASK 0x40000000
1162#define PDMA0_QM_PERF_CNT_CFG_EN_IDLE_SHIFT 31
1163#define PDMA0_QM_PERF_CNT_CFG_EN_IDLE_MASK 0x80000000
1164
1165#endif /* ASIC_REG_PDMA0_QM_MASKS_H_ */