pdma0_qm_arc_aux_regs.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2020 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_
 14#define ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_
 15
 16/*
 17 *****************************************
 18 *   PDMA0_QM_ARC_AUX
 19 *   (Prototype: QMAN_ARC_AUX)
 20 *****************************************
 21 */
 22
 23#define mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ 0x4C88100
 24
 25#define mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK 0x4C88104
 26
 27#define mmPDMA0_QM_ARC_AUX_RST_VEC_ADDR 0x4C88108
 28
 29#define mmPDMA0_QM_ARC_AUX_DBG_MODE 0x4C8810C
 30
 31#define mmPDMA0_QM_ARC_AUX_CLUSTER_NUM 0x4C88110
 32
 33#define mmPDMA0_QM_ARC_AUX_ARC_NUM 0x4C88114
 34
 35#define mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT 0x4C88118
 36
 37#define mmPDMA0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x4C8811C
 38
 39#define mmPDMA0_QM_ARC_AUX_CTI_AP_STS 0x4C88120
 40
 41#define mmPDMA0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4C88124
 42
 43#define mmPDMA0_QM_ARC_AUX_ARC_RST 0x4C88128
 44
 45#define mmPDMA0_QM_ARC_AUX_ARC_RST_REQ 0x4C8812C
 46
 47#define mmPDMA0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4C88130
 48
 49#define mmPDMA0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4C88134
 50
 51#define mmPDMA0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4C88138
 52
 53#define mmPDMA0_QM_ARC_AUX_PCIE_MSB_ADDR 0x4C8813C
 54
 55#define mmPDMA0_QM_ARC_AUX_CFG_LSB_ADDR 0x4C88140
 56
 57#define mmPDMA0_QM_ARC_AUX_CFG_MSB_ADDR 0x4C88144
 58
 59#define mmPDMA0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4C88150
 60
 61#define mmPDMA0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4C88154
 62
 63#define mmPDMA0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4C88158
 64
 65#define mmPDMA0_QM_ARC_AUX_HBM1_MSB_ADDR 0x4C8815C
 66
 67#define mmPDMA0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4C88160
 68
 69#define mmPDMA0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4C88164
 70
 71#define mmPDMA0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4C88168
 72
 73#define mmPDMA0_QM_ARC_AUX_HBM3_MSB_ADDR 0x4C8816C
 74
 75#define mmPDMA0_QM_ARC_AUX_HBM0_OFFSET 0x4C88170
 76
 77#define mmPDMA0_QM_ARC_AUX_HBM1_OFFSET 0x4C88174
 78
 79#define mmPDMA0_QM_ARC_AUX_HBM2_OFFSET 0x4C88178
 80
 81#define mmPDMA0_QM_ARC_AUX_HBM3_OFFSET 0x4C8817C
 82
 83#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4C88180
 84
 85#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4C88184
 86
 87#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4C88188
 88
 89#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x4C8818C
 90
 91#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4C88190
 92
 93#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4C88194
 94
 95#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4C88198
 96
 97#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x4C8819C
 98
 99#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x4C881A0
100
101#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x4C881A4
102
103#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x4C881A8
104
105#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x4C881AC
106
107#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x4C881B0
108
109#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x4C881B4
110
111#define mmPDMA0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x4C881B8
112
113#define mmPDMA0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x4C881BC
114
115#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_0 0x4C881C0
116
117#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_1 0x4C881C4
118
119#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_2 0x4C881C8
120
121#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_3 0x4C881CC
122
123#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_4 0x4C881D0
124
125#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_5 0x4C881D4
126
127#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_6 0x4C881D8
128
129#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_7 0x4C881DC
130
131#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_0 0x4C881E0
132
133#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_1 0x4C881E4
134
135#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_2 0x4C881E8
136
137#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_3 0x4C881EC
138
139#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_4 0x4C881F0
140
141#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_5 0x4C881F4
142
143#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_6 0x4C881F8
144
145#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_7 0x4C881FC
146
147#define mmPDMA0_QM_ARC_AUX_SW_INTR_0 0x4C88200
148
149#define mmPDMA0_QM_ARC_AUX_SW_INTR_1 0x4C88204
150
151#define mmPDMA0_QM_ARC_AUX_SW_INTR_2 0x4C88208
152
153#define mmPDMA0_QM_ARC_AUX_SW_INTR_3 0x4C8820C
154
155#define mmPDMA0_QM_ARC_AUX_SW_INTR_4 0x4C88210
156
157#define mmPDMA0_QM_ARC_AUX_SW_INTR_5 0x4C88214
158
159#define mmPDMA0_QM_ARC_AUX_SW_INTR_6 0x4C88218
160
161#define mmPDMA0_QM_ARC_AUX_SW_INTR_7 0x4C8821C
162
163#define mmPDMA0_QM_ARC_AUX_SW_INTR_8 0x4C88220
164
165#define mmPDMA0_QM_ARC_AUX_SW_INTR_9 0x4C88224
166
167#define mmPDMA0_QM_ARC_AUX_SW_INTR_10 0x4C88228
168
169#define mmPDMA0_QM_ARC_AUX_SW_INTR_11 0x4C8822C
170
171#define mmPDMA0_QM_ARC_AUX_SW_INTR_12 0x4C88230
172
173#define mmPDMA0_QM_ARC_AUX_SW_INTR_13 0x4C88234
174
175#define mmPDMA0_QM_ARC_AUX_SW_INTR_14 0x4C88238
176
177#define mmPDMA0_QM_ARC_AUX_SW_INTR_15 0x4C8823C
178
179#define mmPDMA0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4C88280
180
181#define mmPDMA0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4C88284
182
183#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4C88290
184
185#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4C88294
186
187#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4C88298
188
189#define mmPDMA0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x4C8829C
190
191#define mmPDMA0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x4C882A0
192
193#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x4C882A4
194
195#define mmPDMA0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x4C882A8
196
197#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_STS 0x4C882B0
198
199#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x4C882B4
200
201#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x4C882B8
202
203#define mmPDMA0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x4C882BC
204
205#define mmPDMA0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x4C882C0
206
207#define mmPDMA0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x4C882C4
208
209#define mmPDMA0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x4C882C8
210
211#define mmPDMA0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x4C882CC
212
213#define mmPDMA0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x4C882D0
214
215#define mmPDMA0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x4C882E0
216
217#define mmPDMA0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x4C882E4
218
219#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x4C882E8
220
221#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x4C882EC
222
223#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x4C882F0
224
225#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x4C882F4
226
227#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0 0x4C88300
228
229#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_1 0x4C88304
230
231#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_2 0x4C88308
232
233#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_3 0x4C8830C
234
235#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_4 0x4C88310
236
237#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_5 0x4C88314
238
239#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_6 0x4C88318
240
241#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_7 0x4C8831C
242
243#define mmPDMA0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4C88320
244
245#define mmPDMA0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4C88324
246
247#define mmPDMA0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4C88328
248
249#define mmPDMA0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x4C8832C
250
251#define mmPDMA0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4C88330
252
253#define mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4C88334
254
255#define mmPDMA0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4C88338
256
257#define mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x4C8833C
258
259#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4C88350
260
261#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4C88354
262
263#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4C88358
264
265#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x4C8835C
266
267#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4C88360
268
269#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4C88364
270
271#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4C88368
272
273#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x4C8836C
274
275#define mmPDMA0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4C88370
276
277#define mmPDMA0_QM_ARC_AUX_CBU_LOCK_OVR 0x4C88374
278
279#define mmPDMA0_QM_ARC_AUX_CBU_PROT_OVR 0x4C88378
280
281#define mmPDMA0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x4C8837C
282
283#define mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4C88380
284
285#define mmPDMA0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4C88384
286
287#define mmPDMA0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x4C8838C
288
289#define mmPDMA0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4C88390
290
291#define mmPDMA0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4C88400
292
293#define mmPDMA0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4C88404
294
295#define mmPDMA0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4C88408
296
297#define mmPDMA0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x4C8840C
298
299#define mmPDMA0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4C88420
300
301#define mmPDMA0_QM_ARC_AUX_LBU_LOCK_OVR 0x4C88424
302
303#define mmPDMA0_QM_ARC_AUX_LBU_PROT_OVR 0x4C88428
304
305#define mmPDMA0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x4C8842C
306
307#define mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4C88430
308
309#define mmPDMA0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4C88434
310
311#define mmPDMA0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x4C8843C
312
313#define mmPDMA0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4C88440
314
315#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4C88500
316
317#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4C88504
318
319#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4C88508
320
321#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x4C8850C
322
323#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4C88510
324
325#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4C88514
326
327#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4C88518
328
329#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x4C8851C
330
331#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4C88520
332
333#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4C88524
334
335#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4C88528
336
337#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x4C8852C
338
339#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4C88530
340
341#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4C88534
342
343#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4C88538
344
345#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x4C8853C
346
347#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4C88540
348
349#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4C88544
350
351#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4C88548
352
353#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x4C8854C
354
355#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4C88550
356
357#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4C88554
358
359#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4C88558
360
361#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x4C8855C
362
363#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4C88560
364
365#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4C88564
366
367#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4C88568
368
369#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x4C8856C
370
371#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4C88570
372
373#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4C88574
374
375#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4C88578
376
377#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x4C8857C
378
379#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4C88580
380
381#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4C88584
382
383#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4C88588
384
385#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x4C8858C
386
387#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4C88590
388
389#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4C88594
390
391#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4C88598
392
393#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x4C8859C
394
395#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x4C885A0
396
397#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x4C885A4
398
399#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x4C885A8
400
401#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x4C885AC
402
403#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x4C885B0
404
405#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x4C885B4
406
407#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x4C885B8
408
409#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x4C885BC
410
411#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x4C885C0
412
413#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x4C885C4
414
415#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x4C885C8
416
417#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x4C885CC
418
419#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x4C885D0
420
421#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x4C885D4
422
423#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x4C885D8
424
425#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x4C885DC
426
427#define mmPDMA0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x4C885E0
428
429#define mmPDMA0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x4C885E4
430
431#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4C88620
432
433#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4C88624
434
435#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4C88628
436
437#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4C88630
438
439#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4C88634
440
441#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4C88638
442
443#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x4C8863C
444
445#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4C88640
446
447#define mmPDMA0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4C88644
448
449#define mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4C88648
450
451#define mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x4C8864C
452
453#define mmPDMA0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4C88650
454
455#define mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4C88654
456
457#define mmPDMA0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4C88658
458
459#define mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x4C8865C
460
461#define mmPDMA0_QM_ARC_AUX_AUX2APB_PROT 0x4C88700
462
463#define mmPDMA0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4C88704
464
465#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4C88708
466
467#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x4C8870C
468
469#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4C88710
470
471#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4C88714
472
473#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4C88718
474
475#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x4C8871C
476
477#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4C88720
478
479#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4C88724
480
481#define mmPDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4C88728
482
483#define mmPDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x4C8872C
484
485#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4C88730
486
487#define mmPDMA0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4C88734
488
489#define mmPDMA0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4C88738
490
491#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x4C8873C
492
493#define mmPDMA0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4C88740
494
495#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4C88750
496
497#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4C88754
498
499#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4C88758
500
501#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x4C8875C
502
503#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4C88760
504
505#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4C88764
506
507#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4C88768
508
509#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x4C8876C
510
511#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4C88770
512
513#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4C88774
514
515#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4C88778
516
517#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x4C8877C
518
519#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4C88780
520
521#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4C88784
522
523#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4C88788
524
525#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x4C8878C
526
527#define mmPDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4C88790
528
529#define mmPDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4C88794
530
531#define mmPDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4C88798
532
533#define mmPDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x4C8879C
534
535#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4C88800
536
537#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4C88804
538
539#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4C88808
540
541#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_3 0x4C8880C
542
543#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4C88810
544
545#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4C88814
546
547#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4C88818
548
549#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_7 0x4C8881C
550
551#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4C88820
552
553#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4C88824
554
555#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4C88828
556
557#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_11 0x4C8882C
558
559#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4C88830
560
561#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4C88834
562
563#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4C88838
564
565#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_15 0x4C8883C
566
567#define mmPDMA0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4C88840
568
569#define mmPDMA0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4C88844
570
571#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4C88848
572
573#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x4C8884C
574
575#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4C88850
576
577#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4C88854
578
579#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4C88900
580
581#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4C88904
582
583#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4C88908
584
585#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x4C8890C
586
587#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4C88910
588
589#define mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4C88920
590
591#endif /* ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_ */